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ARM: k2g-gp-evm: update to rgmii pinmux configuration

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This patch updates pinmux configuration for K2G GP EVM based on
data generated by the pinmux tool at
https://dev.ti.com/pinmux/app.html#/default

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Murali Karicheri
2019-02-21 12:02:02 -05:00
committed by Tom Rini
parent c7206e9789
commit b15311c90b
1 changed files with 17 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
board/ti/ks2_evm/mux-k2g.h
View File

@@ -125,21 +125,23 @@ struct pin_cfg k2g_evm_pin_cfg[] = {
{ 70, MODE(0) }, /* SOC_MMC1_SDWP */
{ 71, MODE(0) }, /* MMC1POW TP124 */
/* RGMII */
{ 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */
{ 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */
{ 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */
{ 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */
{ 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */
{ 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */
{ 85, MODE(1) }, /* SOC_RGMII_TXCLK */
{ 91, MODE(1) }, /* SOC_RGMII_TXD3 */
{ 92, MODE(1) }, /* SOC_RGMII_TXD2 */
{ 93, MODE(1) }, /* SOC_RGMII_TXD1 */
{ 94, MODE(1) }, /* SOC_RGMII_TXD0 */
{ 95, MODE(1) }, /* SOC_RGMII_TXCTL */
{ 98, MODE(0) }, /* SOC_MDIO_DATA */
{ 99, MODE(0) }, /* SOC_MDIO_CLK */
/* EMAC */
{ 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
{ 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
{ 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
{ 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
{ 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
{ 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
{ 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
{ 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
{ 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
{ 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
{ 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
{ 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
/* MDIO */
{ 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
{ 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
/* PWM */
{ 73, MODE(4) }, /* SOC_EHRPWM3A */