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stm32mp: update the mmu configuration for SPL and prereloc

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Overidde the weak function dram_bank_mmu_setup() to set the DDR
(preloc case) or the SYSRAM (in SPL case) executable before to enable
the MMU and configure DACR.

This weak function is called in dcache_enable/mmu_setup.

This patchs avoids a permission access issue when the DDR is marked
executable (by calling mmu_set_region_dcache_behaviour with
DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission
activation with DACR in dcache_enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Patrick Delaunay
2021-02-05 13:53:33 +01:00
committed by Tom Rini
parent 1419e5b516
commit aad8414794
1 changed files with 30 additions and 10 deletions
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40
arch/arm/mach-stm32mp/cpu.c
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@@ -211,6 +211,35 @@ u32 get_bootmode(void)
TAMP_BOOT_MODE_SHIFT;
}
/*
* weak function overidde: set the DDR/SYSRAM executable before to enable the
* MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
*/
void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
int i;
phys_addr_t start;
phys_size_t size;
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
} else if (gd->flags & GD_FLG_RELOC) {
/* bd->bi_dram is available only after relocation */
start = bd->bi_dram[bank].start;
size = bd->bi_dram[bank].size;
} else {
/* mark cacheable and executable the beggining of the DDR */
start = STM32_DDR_BASE;
size = CONFIG_DDR_CACHEABLE_SIZE;
}
for (i = start >> MMU_SECTION_SHIFT;
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
/*
* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
* MMU/TLB is updated in enable_caches() for U-Boot after relocation
@@ -226,17 +255,8 @@ static void early_enable_caches(void)
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (unsigned long)&early_tlb;
/* enable MMU (default configuration) */
dcache_enable();
if (IS_ENABLED(CONFIG_SPL_BUILD))
mmu_set_region_dcache_behaviour(
ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
DCACHE_DEFAULT_OPTION);
else
mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
CONFIG_DDR_CACHEABLE_SIZE,
DCACHE_DEFAULT_OPTION);
}
/*