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i.MX7ULP: Fix PCC register bits mask and offset issue

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The offset for FRAC and the mask for PCD are not correct.
If we set FRAC, we can't get the right frequency. Fix them
to correct value.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
2019-07-22 01:24:47 +00:00
committed by Stefano Babic
parent 3ed6734e69
commit a0f4f7ee60
1 changed files with 2 additions and 2 deletions
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4
arch/arm/include/asm/arch-mx7ulp/pcc.h
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@@ -289,10 +289,10 @@ enum pcc3_entry {
#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
#define PCC_PCS_OFFSET 24
#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
#define PCC_FRAC_OFFSET 4
#define PCC_FRAC_OFFSET 3
#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
#define PCC_PCD_OFFSET 0
#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET)
#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
enum pcc_clksrc_type {