Convert CONFIG_FSL_IFC to Kconfig
This converts the following to Kconfig: CONFIG_FSL_IFC This is done via select statements to match previous logic. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
@@ -1,5 +1,6 @@
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config ARCH_LS1021A
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bool
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select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_ERRATUM_A008378
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@@ -59,6 +59,7 @@ config ARCH_LS1043A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select GICV2
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@@ -94,6 +95,7 @@ config ARCH_LS1043A
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config ARCH_LS1046A
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bool
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select ARMV8_SET_SMPEN
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select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select GICV2
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@@ -134,6 +136,7 @@ config ARCH_LS1088A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select FSL_IFC
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select GICV3
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@@ -182,6 +185,7 @@ config ARCH_LS2080A
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select ARM_ERRATA_828024
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select ARM_ERRATA_829520
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select ARM_ERRATA_833471
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select FSL_IFC
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select GICV3
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@@ -1084,9 +1084,6 @@ config SYS_PPC64
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config SYS_PPC_E500_USE_DEBUG_TLB
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bool
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config FSL_IFC
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bool
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config FSL_ELBC
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bool
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@@ -500,4 +500,7 @@ config ESM_PMIC
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Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
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typically to reboot the board in error condition.
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config FSL_IFC
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bool
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endmenu
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@@ -134,6 +134,7 @@ config NAND_FSL_ELBC
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config NAND_FSL_IFC
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bool "Support Freescale Integrated Flash Controller NAND driver"
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select FSL_IFC
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help
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Enable the Freescale Integrated Flash Controller NAND driver.
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@@ -40,7 +40,6 @@
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* IFC Definitions
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*/
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/* NOR Flash Definitions */
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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@@ -76,7 +76,6 @@ unsigned long get_board_sys_clk(void);
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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@@ -89,7 +89,6 @@
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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@@ -122,7 +122,6 @@
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#ifndef SPL_NO_IFC
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#if defined(CONFIG_TFABOOT) || \
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(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
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#define CONFIG_FSL_IFC
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/*
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* CONFIG_SYS_FLASH_BASE has the final address (core view)
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* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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@@ -17,8 +17,6 @@
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#define CONFIG_SYS_UBOOT_BASE 0x40100000
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/* IFC */
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#define CONFIG_FSL_IFC
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/*
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* NAND Flash Definitions
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*/
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@@ -43,7 +43,6 @@ unsigned long get_board_sys_clk(void);
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/* IFC */
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_IFC
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/*
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* CONFIG_SYS_FLASH_BASE has the final address (core view)
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* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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@@ -27,14 +27,6 @@
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#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
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#endif
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#ifndef SPL_NO_IFC
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/* IFC */
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#define CONFIG_FSL_IFC
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/*
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* NAND Flash Definitions
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*/
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#endif
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#define CONFIG_SYS_NAND_BASE 0x7e800000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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@@ -63,11 +63,6 @@
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
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#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
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/* IFC */
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#define CONFIG_FSL_IFC
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#endif
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/*
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* During booting, IFC is mapped at the region of 0x30000000.
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* But this region is limited to 256MB. To accommodate NOR, promjet
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@@ -74,9 +74,6 @@
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
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/* IFC */
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#define CONFIG_FSL_IFC
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/*
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* During booting, IFC is mapped at the region of 0x30000000.
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* But this region is limited to 256MB. To accommodate NOR, promjet
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