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Add support for SL8245 board

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This commit is contained in:
wdenk
2003-06-27 22:44:25 +00:00
parent 8bde7f776c
commit 91a0ce965d
11 changed files with 1056 additions and 24 deletions
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16
CHANGELOG
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@@ -2,24 +2,16 @@
Changes since U-Boot 0.4.0:
======================================================================
* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
* Add support for SL8245 board
======================================================================
Changes for U-Boot 0.4.0:
======================================================================
* Patches by Robert Schwebel, 26 Jun 2003:
- csb226 configuration updated
- credits for logodl port updated
- innokom configuration updated
- logodl tree update, still with coding style inconsistencies
- added OCM for ppc405 warning to README
- logdl
- csb226
- innokom
* Patch by Pantelis Antoniou, 25 Jun 2003:
update NetVia with V2 board support

4
MAINTAINERS
View File

@@ -3,10 +3,7 @@
# Regular Maintainers for U-Boot board support: #
# #
# For any board without permanent maintainer, please contact #
# for PowerPC systems: #
# Wolfgang Denk <wd@denx.de> #
# for ARM systems: #
# Marius Gröger <mag@sysgo.de> #
# and Cc: the <U-Boot-Users@lists.sourceforge.net> mailing lists. #
# #
# Note: lists sorted by Maintainer Name #
@@ -83,6 +80,7 @@ Wolfgang Denk <wd@denx.de>
CU824 MPC8240
Sandpoint8240 MPC8240
SL8245 MPC8245
ATC MPC8250
PM825 MPC8250

12
MAKEALL
View File

@@ -45,10 +45,10 @@ LIST_8xx=" \
LIST_4xx=" \
ADCIOP AR405 ASH405 BUBINGA405EP \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 DASA_SIM \
DU405 EBONY ERIC MIP405 \
MIP405T ML2 OCRTC ORSG \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 DASA_SIM \
DU405 EBONY ERIC MIP405 \
MIP405T ML2 OCRTC ORSG \
PCI405 PIP405 PMC405 W7OLMC \
W7OLMG WALNUT405 \
"
@@ -58,9 +58,9 @@ LIST_4xx=" \
#########################################################################
LIST_824x=" \
A3000 BMW CPC45 CU824 \
A3000 BMW CPC45 CU824 \
MOUSSE MUSENKI OXC PN62 \
Sandpoint8240 Sandpoint8245 utx8245 \
Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
"
#########################################################################

6
Makefile
View File

@@ -134,8 +134,7 @@ u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
u-boot: depend subdirs $(OBJS) $(LIBS) $(LDSCRIPT)
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
$(LD) $(LDFLAGS) $(OBJS) \
--start-group $(LIBS) --end-group \
-Map u-boot.map -o u-boot
@@ -543,6 +542,9 @@ Sandpoint8240_config: unconfig
Sandpoint8245_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x sandpoint
SL8245_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x sl8245
utx8245_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x utx8245

40
board/sl8245/Makefile Normal file
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@@ -0,0 +1,40 @@
#
# (C) Copyright 2001 - 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

30
board/sl8245/config.mk Normal file
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@@ -0,0 +1,30 @@
#
# (C) Copyright 2001 - 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# SL8245 board
#
TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

488
board/sl8245/flash.c Normal file
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@@ -0,0 +1,488 @@
/*
* (C) Copyright 2001 - 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc824x.h>
#include <asm/processor.h>
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
#define FLASH_BANK_SIZE 0x800000
#define MAIN_SECT_SIZE 0x40000
#define PARAM_SECT1_SIZE 0x20000
#define PARAM_SECT23_SIZE 0x8000
#define PARAM_SECT4_SIZE 0x10000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
static int write_data (flash_info_t *info, ulong dest, ulong *data);
static void write_via_fpu(vu_long *addr, ulong *data);
static __inline__ unsigned long get_msr(void);
static __inline__ void set_msr(unsigned long msr);
/*---------------------------------------------------------------------*/
#undef DEBUG_FLASH
/*---------------------------------------------------------------------*/
#ifdef DEBUG_FLASH
#define DEBUGF(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGF(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
#define __align__ __attribute__ ((aligned (8)))
static __align__ ulong precmd0[2] = { 0x00aa00aa, 0x00aa00aa };
static __align__ ulong precmd1[2] = { 0x00550055, 0x00550055 };
static __align__ ulong cmdid[2] = { 0x00900090, 0x00900090 };
static __align__ ulong cmderase[2] = { 0x00800080, 0x00800080 };
static __align__ ulong cmdersusp[2] = { 0x00b000b0, 0x00b000b0 };
static __align__ ulong cmdsecter[2] = { 0x00300030, 0x00300030 };
static __align__ ulong cmdprog[2] = { 0x00a000a0, 0x00a000a0 };
static __align__ ulong cmdres[2] = { 0x00f000f0, 0x00f000f0 };
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
write_via_fpu (&addr[0xaaa], precmd0);
write_via_fpu (&addr[0x554], precmd1);
write_via_fpu (&addr[0xaaa], cmdid);
DEBUGF ("Flash bank # %d:\n"
"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
"\tDevice ID @ 0x%08lX: 0x%08lX\n",
i,
(ulong) (&addr[0]), addr[0],
(ulong) (&addr[2]), addr[2]);
if ((addr[0] == addr[1]) && (addr[0] == AMD_MANUFACT) &&
(addr[2] == addr[3]) && (addr[2] == AMD_ID_LV160T)) {
flash_info[i].flash_id = (FLASH_MAN_AMD & FLASH_VENDMASK) |
(FLASH_AM160T & FLASH_TYPEMASK);
} else {
flash_info[i].flash_id = FLASH_UNKNOWN;
write_via_fpu (addr, cmdres);
goto Done;
}
DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
write_via_fpu (addr, cmdres);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
for (j = 0; j < 32; j++) {
flash_info[i].start[j] = CFG_FLASH_BASE +
i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE;
}
flash_info[i].start[32] =
flash_info[i].start[31] + PARAM_SECT1_SIZE;
flash_info[i].start[33] =
flash_info[i].start[32] + PARAM_SECT23_SIZE;
flash_info[i].start[34] =
flash_info[i].start[33] + PARAM_SECT23_SIZE;
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
flash_protect ( FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[1]);
#else
flash_protect ( FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
#else
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
#endif
Done:
return size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
switch ((i = info->flash_id & FLASH_VENDMASK)) {
case (FLASH_MAN_AMD & FLASH_VENDMASK):
printf ("Intel: ");
break;
default:
printf ("Unknown Vendor 0x%04x ", i);
break;
}
switch ((i = info->flash_id & FLASH_TYPEMASK)) {
case (FLASH_AM160T & FLASH_TYPEMASK):
printf ("AM29LV160BT (16Mbit)\n");
break;
default:
printf ("Unknown Chip Type 0x%04x\n", i);
goto Done;
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
Done:
return;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
DEBUGF ("Erase flash bank %d sect %d ... %d\n",
info - &flash_info[0], s_first, s_last);
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(FLASH_MAN_AMD & FLASH_VENDMASK)) {
printf ("Can erase only AMD flash types - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
start = get_timer (0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *) (info->start[sect]);
DEBUGF ("Erase sect %d @ 0x%08lX\n", sect, (ulong) addr);
/* Disable interrupts which might cause a timeout
* here.
*/
flag = disable_interrupts ();
write_via_fpu (&addr[0xaaa], precmd0);
write_via_fpu (&addr[0x554], precmd1);
write_via_fpu (&addr[0xaaa], cmderase);
write_via_fpu (&addr[0xaaa], precmd0);
write_via_fpu (&addr[0x554], precmd1);
write_via_fpu (&addr[0xaaa], cmdsecter);
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while (((addr[0] & 0x00800080) != 0x00800080) ||
((addr[1] & 0x00800080) != 0x00800080)) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
write_via_fpu (addr, cmdersusp);
write_via_fpu (addr, cmdres);
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
write_via_fpu (addr, cmdres);
}
}
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
#define FLASH_WIDTH 8 /* flash bus width in bytes */
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, cp, msr;
int l, rc, i;
ulong data[2];
ulong *datah = &data[0];
ulong *datal = &data[1];
DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
addr, (ulong) src, cnt);
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
msr = get_msr ();
set_msr (msr | MSR_FP);
wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
*datah = *datal = 0;
for (i = 0, cp = wp; i < l; i++, cp++) {
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | (*(uchar *) cp);
}
for (; i < FLASH_WIDTH && cnt > 0; ++i) {
char tmp;
tmp = *src;
src++;
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | tmp;
--cnt;
++cp;
}
for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
}
*datal = (*datah << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, data)) != 0) {
set_msr (msr);
return (rc);
}
wp += FLASH_WIDTH;
}
/*
* handle FLASH_WIDTH aligned part
*/
while (cnt >= FLASH_WIDTH) {
*datah = *(ulong *) src;
*datal = *(ulong *) (src + 4);
if ((rc = write_data (info, wp, data)) != 0) {
set_msr (msr);
return (rc);
}
wp += FLASH_WIDTH;
cnt -= FLASH_WIDTH;
src += FLASH_WIDTH;
}
if (cnt == 0) {
set_msr (msr);
return (0);
}
/*
* handle unaligned tail bytes
*/
*datah = *datal = 0;
for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
char tmp;
tmp = *src;
src++;
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | tmp;
--cnt;
}
for (; i < FLASH_WIDTH; ++i, ++cp) {
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | (*(uchar *) cp);
}
rc = write_data (info, wp, data);
set_msr (msr);
return (rc);
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t * info, ulong dest, ulong * data)
{
vu_long *chip = (vu_long *) (info->start[0]);
vu_long *addr = (vu_long *) dest;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if (((addr[0] & data[0]) != data[0]) ||
((addr[1] & data[1]) != data[1])) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
write_via_fpu (&chip[0xaaa], precmd0);
write_via_fpu (&chip[0x554], precmd1);
write_via_fpu (&chip[0xaaa], cmdprog);
write_via_fpu (addr, data);
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
start = get_timer (0);
while (((addr[0] & 0x00800080) != (data[0] & 0x00800080)) ||
((addr[1] & 0x00800080) != (data[1] & 0x00800080))) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
write_via_fpu (chip, cmdres);
return (1);
}
}
write_via_fpu (chip, cmdres);
return (0);
}
/*-----------------------------------------------------------------------
*/
static void write_via_fpu (vu_long * addr, ulong * data)
{
__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
}
/*-----------------------------------------------------------------------
*/
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
return msr;
}
static __inline__ void set_msr (unsigned long msr)
{
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
}

86
board/sl8245/sl8245.c Normal file
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@@ -0,0 +1,86 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc824x.h>
int checkboard (void)
{
ulong busfreq = get_bus_freq(0);
char buf[32];
printf("Board: SL8245, local bus @ %s MHz\n", strmhz(buf, busfreq));
return 0;
}
long int initdram (int board_type)
{
#ifndef CFG_RAMBOOT
int i, cnt;
volatile uchar * base= CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
#else
return CFG_MAX_RAM_SIZE;
#endif
}

128
board/sl8245/u-boot.lds Normal file
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@@ -0,0 +1,128 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc824x/start.o (.text)
lib_ppc/board.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

268
include/configs/SL8245.h Normal file
View File

@@ -0,0 +1,268 @@
/*
* (C) Copyright 2001 - 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* ------------------------------------------------------------------------- */
/*
* Configuration settings for the SL8245 board.
*/
/* ------------------------------------------------------------------------- */
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_SL8245 1
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BOOTDELAY 5
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~CFG_CMD_NET )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#undef CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size
*/
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_MAXARGS 8 /* Max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00400000 /* Default load address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */
#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM }
#define CFG_RESET_ADDRESS 0xFFF00100
#define CFG_EUMB_ADDR 0xFC000000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
/* Maximum amount of RAM.
*/
#define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256 MB of (S)DRAM */
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#undef CFG_RAMBOOT
#else
#define CFG_RAMBOOT
#endif
/*
* NS16550 Configuration
*/
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area
*/
#define CFG_GBL_DATA_SIZE 128
#define CFG_INIT_RAM_ADDR 0x40000000
#define CFG_INIT_RAM_END 0x1000
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
* For the detail description refer to the MPC8240 user's manual.
*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external frequency to pll */
#define CFG_HZ 1000
/* Bit-field values for MCCR1.
*/
#define CFG_ROMNAL 0
#define CFG_ROMFAL 7
#define CFG_BANK0_ROW 2
/* Bit-field values for MCCR2.
*/
#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
*/
#define CFG_BSTOPRE 192
/* Bit-field values for MCCR3.
*/
#define CFG_REFREC 2 /* Refresh to activate interval */
/* Bit-field values for MCCR4.
*/
#define CFG_PRETOACT 2 /* Precharge to activate interval */
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
#define CFG_ACTORW 3 /* FIXME was 2 */
#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM 1
#define CFG_REGDIMM 0
#define CFG_ODCR 0xff /* configures line driver impedances, */
/* see 8245 book for bit definitions */
#define CFG_PGMAX 0x32 /* how long the 8245 retains the */
/* currently accessed page in memory */
/* see 8245 book for details */
/* Memory bank settings.
* Only bits 20-29 are actually used from these vales to set the
* start/end addresses. The upper two bits will always be 0, and the lower
* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
* address. Refer to the MPC8240 book.
*/
#define CFG_BANK0_START 0x00000000
#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE 1
#define CFG_BANK1_START 0x3ff00000
#define CFG_BANK1_END 0x3fffffff
#define CFG_BANK1_ENABLE 0
#define CFG_BANK2_START 0x3ff00000
#define CFG_BANK2_END 0x3fffffff
#define CFG_BANK2_ENABLE 0
#define CFG_BANK3_START 0x3ff00000
#define CFG_BANK3_END 0x3fffffff
#define CFG_BANK3_ENABLE 0
#define CFG_BANK4_START 0x3ff00000
#define CFG_BANK4_END 0x3fffffff
#define CFG_BANK4_ENABLE 0
#define CFG_BANK5_START 0x3ff00000
#define CFG_BANK5_END 0x3fffffff
#define CFG_BANK5_ENABLE 0
#define CFG_BANK6_START 0x3ff00000
#define CFG_BANK6_END 0x3fffffff
#define CFG_BANK6_ENABLE 0
#define CFG_BANK7_START 0x3ff00000
#define CFG_BANK7_END 0x3fffffff
#define CFG_BANK7_ENABLE 0
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors per flash */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* Warining: environment is not EMBEDDED in the U-Boot code.
* It's stored in flash separately.
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0xFFFF0000
#define CFG_ENV_SIZE 0x00010000 /* Size of the Environment */
#define CFG_ENV_SECT_SIZE 0x00010000 /* Size of the Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */

2
include/version.h
View File

@@ -24,6 +24,6 @@
#ifndef __VERSION_H__
#define __VERSION_H__
#define U_BOOT_VERSION "U-Boot 0.4.1"
#define U_BOOT_VERSION "U-Boot 0.4.1-stable"
#endif /* __VERSION_H__ */