Merge tag 'u-boot-stm32-mcu-20190514' of https://github.com/pchotard/u-boot

STM32 MCUs update:
_ Add MPU region for SPI NOR memory mapped region
_ Add missing QSPI flash compatible for STM32 F7 boards
_ Update spi-tx-bus-width and spi-rx-bus-width properties
_ Add QSPI support for STM32F469 Discovery board

arch/arm/dts/stm32746g-eval-u-boot.dtsi

@@ -177,12 +177,14 @@
 };
 
 &qspi {
+	reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
 	qflash0: n25q512a {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
 		spi-max-frequency = <108000000>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 		reg = <0>;
 	};
 };

arch/arm/dts/stm32f469-disco-u-boot.dtsi

@@ -23,6 +23,7 @@
 		gpio8 = &gpioi;
 		gpio9 = &gpioj;
 		gpio10 = &gpiok;
+		spi0 = &qspi;
 	};
 
 	soc {
@@ -64,6 +65,19 @@
 			       st,sdram-refcount = < 1292 >;
 		       };
 		};
+
+		qspi: quadspi@A0001000 {
+			compatible = "st,stm32-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+			reg-names = "qspi", "qspi_mm";
+			interrupts = <91>;
+			spi-max-frequency = <108000000>;
+			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
+			resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
+			pinctrl-0 = <&qspi_pins>;
+		};
 	};
 };
 
@@ -205,6 +219,18 @@
 		};
 	};
 
+	qspi_pins: qspi@0 {
+		pins {
+			pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */
+				 <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
+				 <STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */
+				 <STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */
+				 <STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */
+				 <STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */
+			slew-rate = <2>;
+		};
+	};
+
 	usart3_pins_a: usart3@0	{
 		u-boot,dm-pre-reloc;
 		pins1 {
@@ -227,3 +253,16 @@
 &syscfg {
 	u-boot,dm-pre-reloc;
 };
+
+&qspi {
+	reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
+	flash0: n25q128a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <108000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+	};
+};

arch/arm/dts/stm32f746-disco-u-boot.dtsi

@@ -234,14 +234,14 @@
 };
 
 &qspi {
+	reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
 	qflash0: n25q128a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q128a13", "jedec,spi-nor";
+		compatible = "jedec,spi-nor";
 		spi-max-frequency = <108000000>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
-		memory-map = <0x90000000 0x1000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 		reg = <0>;
 	};
 };

arch/arm/dts/stm32f769-disco-u-boot.dtsi

@@ -155,10 +155,13 @@
 };
 
 &qspi {
+	reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
 	flash0: mx66l51235l {
 		#address-cells = <1>;
 		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
 		spi-max-frequency = <108000000>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		reg = <0>;
 	};

arch/arm/mach-stm32/soc.c

@@ -21,6 +21,9 @@ int arch_cpu_init(void)
 		O_I_WB_RD_WR_ALLOC, REGION_16MB },
 #endif
 
+		{ 0x90000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+		SHARED_WRITE_BUFFERED, REGION_256MB },
+
 #if defined(CONFIG_STM32F7) || defined(CONFIG_STM32H7)
 		{ 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
 		O_I_WB_RD_WR_ALLOC, REGION_512MB },

configs/stm32f469-discovery_defconfig

@@ -16,6 +16,7 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_GPT=y
 # CONFIG_RANDOM_UUID is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_CACHE=y
@@ -25,4 +26,12 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
 CONFIG_DM_MMC=y
 CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y

drivers/spi/Kconfig

@@ -222,7 +222,7 @@ config SPI_SUNXI
 
 config STM32_QSPI
 	bool "STM32F7 QSPI driver"
-	depends on STM32F7 || ARCH_STM32MP
+	depends on STM32F4 || STM32F7 || ARCH_STM32MP
 	help
 	  Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash chips on platforms embedding