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mach-imx: bootaux: add dcache flushing before enabling M4

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This patch fixes the issue with broken bootaux command,
when M4 binary is loaded and data cache isn't flushed
before M4 core is enabled.

Reproducing:
> tftpboot ${loadaddr} ${board_name}/hello_world.bin
> cp.b ${loadaddr} 0x7F8000 $filesize
> bootaux 0x7F8000

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
This commit is contained in:
Igor Opaniuk
2019-11-28 15:56:20 +02:00
committed by Stefano Babic
parent 0ba1b4de0e
commit 89038264bb
1 changed files with 3 additions and 0 deletions
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3
arch/arm/mach-imx/imx_bootaux.c
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@@ -9,6 +9,7 @@
#include <command.h>
#include <imx_sip.h>
#include <linux/compiler.h>
#include <cpu_func.h>
int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
{
@@ -27,6 +28,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
flush_dcache_all();
/* Enable M4 */
#ifdef CONFIG_IMX8M
call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0);