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Merge tag 'u-boot-stm32-20201125' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

Browse Source 
- STM32 MCU's DT update
- Add DHCOM based STM32MP15x PicoITX board
- Correct ALIGN macro usage for on syram for SPL dcache support
- Fixes on DHCOM: uSD card-detect GPIO and Drop QSPI CS2
- Fix compilation issue for spl_mmc_boot_partition
- Fix MTD partitions for serial boot
- Add support of MCU HOLD BOOT with reset for stm32 remoteproc
  (prepare alligneent with  kernel DT)
- Correct bias information and support in STM32 soc and STMFX
- Support optional vbus in usbphyc
- Update FIT examples to avoid kernel zImage relocation before decompression
This commit is contained in:
Tom Rini
2020-11-25 11:00:52 -05:00
parent d361eafe82 60a2dd6aa2
commit 7889951d0f
44 changed files with 610 additions and 259 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/Makefile
View File

@@ -965,6 +965,7 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157c-odyssey.dtb \
stm32mp15xx-dhcom-drc02.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb

4
arch/arm/dts/armv7-m.dtsi
View File

@@ -1,5 +1,4 @@
#include "skeleton.dtsi"
// SPDX-License-Identifier: GPL-2.0
/ {
nvic: interrupt-controller@e000e100 {
compatible = "arm,armv7m-nvic";
@@ -22,4 +21,3 @@
ranges;
};
};

6
arch/arm/dts/stm32429i-eval-u-boot.dtsi
View File

@@ -136,7 +136,7 @@
};
&pinctrl {
usart1_pins_a: usart1@0 {
usart1_pins_a: usart1-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
@@ -217,3 +217,7 @@
};
};
};
&timer5 {
u-boot,dm-pre-reloc;
};

21
arch/arm/dts/stm32429i-eval.dts
View File

@@ -19,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@00000000 {
device_type = "memory";
reg = <0x00000000 0x2000000>;
};
@@ -54,19 +54,26 @@
regulator-max-microvolt = <3300000>;
};
vdd_panel: vdd-panel {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
leds {
compatible = "gpio-leds";
green {
led-green {
gpios = <&gpiog 6 1>;
linux,default-trigger = "heartbeat";
};
orange {
led-orange {
gpios = <&gpiog 7 1>;
};
red {
led-red {
gpios = <&gpiog 10 1>;
};
blue {
led-blue {
gpios = <&gpiog 12 1>;
};
};
@@ -97,6 +104,7 @@
panel_rgb: panel-rgb {
compatible = "ampire,am-480272h3tmqw-t01h";
power-supply = <&vdd_panel>;
status = "okay";
port {
panel_in_rgb: endpoint {
@@ -191,9 +199,8 @@
&ltdc {
status = "okay";
pinctrl-0 = <&ltdc_pins>;
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-names = "default";
dma-ranges;
port {
ltdc_out_rgb: endpoint {

4
arch/arm/dts/stm32746g-eval-u-boot.dtsi
View File

@@ -165,7 +165,7 @@
};
};
usart1_pins_a: usart1@0 {
usart1_pins_a: usart1-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
@@ -178,7 +178,7 @@
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
qflash0: n25q512a {
qflash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

13
arch/arm/dts/stm32746g-eval.dts
View File

@@ -19,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x2000000>;
};
@@ -30,17 +30,17 @@
leds {
compatible = "gpio-leds";
green {
led-green {
gpios = <&gpiof 10 1>;
linux,default-trigger = "heartbeat";
};
orange {
led-orange {
gpios = <&stmfx_pinctrl 17 1>;
};
red {
led-red {
gpios = <&gpiob 7 1>;
};
blue {
led-blue {
gpios = <&stmfx_pinctrl 19 1>;
};
};
@@ -59,7 +59,6 @@
joystick {
compatible = "gpio-keys";
#size-cells = <0>;
pinctrl-0 = <&joystick_pins>;
pinctrl-names = "default";
button-0 {
@@ -130,7 +129,7 @@
interrupts = <8 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&gpioi>;
stmfx_pinctrl: stmfx-pin-controller {
stmfx_pinctrl: pinctrl {
compatible = "st,stmfx-0300-pinctrl";
gpio-controller;
#gpio-cells = <2>;

107
arch/arm/dts/stm32f4-pinctrl.dtsi
View File

@@ -127,7 +127,7 @@
st,bank-name = "GPIOK";
};
usart1_pins_a: usart1@0 {
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -140,7 +140,7 @@
};
};
usart3_pins_a: usart3@0 {
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
@@ -153,7 +153,7 @@
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
usbotg_fs_pins_a: usbotg-fs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
@@ -164,7 +164,7 @@
};
};
usbotg_fs_pins_b: usbotg_fs@1 {
usbotg_fs_pins_b: usbotg-fs-1 {
pins {
pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
@@ -175,7 +175,7 @@
};
};
usbotg_hs_pins_a: usbotg_hs@0 {
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -195,7 +195,7 @@
};
};
ethernet_mii: mii@0 {
ethernet_mii: mii-0 {
pins {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
@@ -215,13 +215,13 @@
};
};
adc3_in8_pin: adc@200 {
adc3_in8_pin: adc-200 {
pins {
pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
};
};
pwm1_pins: pwm@1 {
pwm1_pins: pwm1-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
@@ -229,14 +229,14 @@
};
};
pwm3_pins: pwm@3 {
pwm3_pins: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
};
};
i2c1_pins: i2c1@0 {
i2c1_pins: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
@@ -246,7 +246,7 @@
};
};
ltdc_pins: ltdc@0 {
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
@@ -280,7 +280,86 @@
};
};
dcmi_pins: dcmi@0 {
ltdc_pins_b: ltdc-1 {
pins {
pinmux = <STM32_PINMUX('C', 6, AF14)>,
/* LCD_HSYNC */
<STM32_PINMUX('A', 4, AF14)>,
/* LCD_VSYNC */
<STM32_PINMUX('G', 7, AF14)>,
/* LCD_CLK */
<STM32_PINMUX('C', 10, AF14)>,
/* LCD_R2 */
<STM32_PINMUX('B', 0, AF9)>,
/* LCD_R3 */
<STM32_PINMUX('A', 11, AF14)>,
/* LCD_R4 */
<STM32_PINMUX('A', 12, AF14)>,
/* LCD_R5 */
<STM32_PINMUX('B', 1, AF9)>,
/* LCD_R6*/
<STM32_PINMUX('G', 6, AF14)>,
/* LCD_R7 */
<STM32_PINMUX('A', 6, AF14)>,
/* LCD_G2 */
<STM32_PINMUX('G', 10, AF9)>,
/* LCD_G3 */
<STM32_PINMUX('B', 10, AF14)>,
/* LCD_G4 */
<STM32_PINMUX('D', 6, AF14)>,
/* LCD_B2 */
<STM32_PINMUX('G', 11, AF14)>,
/* LCD_B3*/
<STM32_PINMUX('B', 11, AF14)>,
/* LCD_G5 */
<STM32_PINMUX('C', 7, AF14)>,
/* LCD_G6 */
<STM32_PINMUX('D', 3, AF14)>,
/* LCD_G7 */
<STM32_PINMUX('G', 12, AF9)>,
/* LCD_B4 */
<STM32_PINMUX('A', 3, AF14)>,
/* LCD_B5 */
<STM32_PINMUX('B', 8, AF14)>,
/* LCD_B6 */
<STM32_PINMUX('B', 9, AF14)>,
/* LCD_B7 */
<STM32_PINMUX('F', 10, AF14)>;
/* LCD_DE */
slew-rate = <2>;
};
};
spi5_pins: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF5)>,
/* SPI5_CLK */
<STM32_PINMUX('F', 9, AF5)>;
/* SPI5_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 8, AF5)>;
/* SPI5_MISO */
bias-disable;
};
};
i2c3_pins: i2c3-0 {
pins {
pinmux = <STM32_PINMUX('C', 9, AF4)>,
/* I2C3_SDA */
<STM32_PINMUX('A', 8, AF4)>;
/* I2C3_SCL */
bias-disable;
drive-open-drain;
slew-rate = <3>;
};
};
dcmi_pins: dcmi-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
@@ -303,7 +382,7 @@
};
};
sdio_pins: sdio_pins@0 {
sdio_pins: sdio-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
@@ -316,7 +395,7 @@
};
};
sdio_pins_od: sdio_pins_od@0 {
sdio_pins_od: sdio-pins-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */

6
arch/arm/dts/stm32f429-disco-u-boot.dtsi
View File

@@ -123,7 +123,7 @@
};
&pinctrl {
usart1_pins_a: usart1@0 {
usart1_pins_a: usart1-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
@@ -192,3 +192,7 @@
&rcc {
u-boot,dm-pre-reloc;
};
&timer5 {
u-boot,dm-pre-reloc;
};

99
arch/arm/dts/stm32f429-disco.dts
View File

@@ -7,6 +7,8 @@
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32F429i-DISCO board";
@@ -17,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@90000000 {
device_type = "memory";
reg = <0x90000000 0x800000>;
};
@@ -28,10 +30,10 @@
leds {
compatible = "gpio-leds";
red {
led-red {
gpios = <&gpiog 14 0>;
};
green {
led-green {
gpios = <&gpiog 13 0>;
linux,default-trigger = "heartbeat";
};
@@ -66,12 +68,103 @@
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <100000>;
status = "okay";
stmpe811@41 {
compatible = "st,stmpe811";
reg = <0x41>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpioa>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 12-bit ADC */
st,mod-12b = <1>;
/* internal ADC reference */
st,ref-sel = <0>;
/* ADC converstion time: 80 clocks */
st,sample-time = <4>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
st,ave-ctrl = <3>;
/* 7 length fractional part in z */
st,fraction-z = <7>;
/*
* 50 mA typical 80 mA max touchscreen drivers
* current limit value
*/
st,i-drive = <1>;
/* 1 ms panel driver settling time */
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
stmpe_adc {
compatible = "st,stmpe-adc";
/* forbid to use ADC channels 3-0 (touch) */
st,norequest-mask = <0x0F>;
};
};
};
&ltdc {
status = "okay";
pinctrl-0 = <&ltdc_pins_b>;
pinctrl-names = "default";
port {
ltdc_out_rgb: endpoint {
remote-endpoint = <&panel_in_rgb>;
};
};
};
&rtc {
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSI>;
status = "okay";
};
&spi5 {
status = "okay";
pinctrl-0 = <&spi5_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
l3gd20: l3gd20@0 {
compatible = "st,l3gd20-gyro";
spi-max-frequency = <10000000>;
st,drdy-int-pin = <2>;
interrupt-parent = <&gpioa>;
interrupts = <1 IRQ_TYPE_EDGE_RISING>,
<2 IRQ_TYPE_EDGE_RISING>;
reg = <0>;
status = "okay";
};
display: display@1{
/* Connect panel-ilitek-9341 to ltdc */
compatible = "st,sf-tc240t-9370-t";
reg = <1>;
spi-3wire;
spi-max-frequency = <10000000>;
dc-gpios = <&gpiod 13 0>;
port {
panel_in_rgb: endpoint {
remote-endpoint = <&ltdc_out_rgb>;
};
};
};
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

30
arch/arm/dts/stm32f429.dtsi
View File

@@ -39,7 +39,7 @@
};
soc {
romem: nvmem@1fff7800 {
romem: efuse@1fff7800 {
compatible = "st,stm32f4-otp";
reg = <0x1fff7800 0x400>;
#address-cells = <1>;
@@ -277,12 +277,10 @@
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@@ -362,6 +360,18 @@
status = "disabled";
};
i2c3: i2c@40005c00 {
compatible = "st,stm32f4-i2c";
reg = <0x40005c00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dac: dac@40007400 {
compatible = "st,stm32f4-dac-core";
reg = <0x40007400 0x400>;
@@ -374,14 +384,14 @@
dac1: dac@1 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
#io-channel-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
#io-channel-cells = <1>;
reg = <2>;
status = "disabled";
};
@@ -546,8 +556,8 @@
status = "disabled";
};
syscfg: system-config@40013800 {
compatible = "syscon";
syscfg: syscon@40013800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
};
@@ -620,6 +630,9 @@
reg = <0x40015000 0x400>;
interrupts = <85>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
dmas = <&dma2 3 2 0x400 0x0>,
<&dma2 4 2 0x400 0x0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -634,7 +647,7 @@
};
pwrcfg: power-config@40007000 {
compatible = "syscon";
compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
};
@@ -748,7 +761,6 @@
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
interrupts = <80>;
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
};

26
arch/arm/dts/stm32f469-disco-u-boot.dtsi
View File

@@ -66,7 +66,7 @@
};
};
qspi: quadspi@A0001000 {
qspi: spi@A0001000 {
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -220,7 +220,7 @@
};
};
usart3_pins_a: usart3@0 {
usart3_pins_a: usart3-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
@@ -235,17 +235,9 @@
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
};
&syscfg {
u-boot,dm-pre-reloc;
};
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
flash0: n25q128a {
flash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -255,3 +247,15 @@
reg = <0>;
};
};
&rcc {
u-boot,dm-pre-reloc;
};
&syscfg {
u-boot,dm-pre-reloc;
};
&timer5 {
u-boot,dm-pre-reloc;
};

19
arch/arm/dts/stm32f469-disco.dts
View File

@@ -19,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@00000000 {
device_type = "memory";
reg = <0x00000000 0x1000000>;
};
@@ -35,23 +35,30 @@
regulator-max-microvolt = <3300000>;
};
vdd_dsi: vdd-dsi {
compatible = "regulator-fixed";
regulator-name = "vdd_dsi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
leds {
compatible = "gpio-leds";
green {
led-green {
gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
orange {
led-orange {
gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
};
red {
led-red {
gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
};
blue {
led-blue {
gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
};
};
@@ -114,6 +121,7 @@
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
power-supply = <&vdd_dsi>;
status = "okay";
port {
@@ -125,7 +133,6 @@
};
&ltdc {
dma-ranges;
status = "okay";
port {

1
arch/arm/dts/stm32f469.dtsi
View File

@@ -8,7 +8,6 @@
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
interrupts = <92>;
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;

22
arch/arm/dts/stm32f7-pinctrl.dtsi
View File

@@ -127,7 +127,7 @@
st,bank-name = "GPIOK";
};
cec_pins_a: cec@0 {
cec_pins_a: cec-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
slew-rate = <0>;
@@ -136,7 +136,7 @@
};
};
usart1_pins_a: usart1@0 {
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -149,7 +149,7 @@
};
};
usart1_pins_b: usart1@1 {
usart1_pins_b: usart1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -162,7 +162,7 @@
};
};
i2c1_pins_b: i2c1@0 {
i2c1_pins_b: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
@@ -172,7 +172,7 @@
};
};
usbotg_hs_pins_a: usbotg-hs@0 {
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -192,7 +192,7 @@
};
};
usbotg_hs_pins_b: usbotg-hs@1 {
usbotg_hs_pins_b: usbotg-hs-1 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -212,7 +212,7 @@
};
};
usbotg_fs_pins_a: usbotg-fs@0 {
usbotg_fs_pins_a: usbotg-fs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
@@ -223,7 +223,7 @@
};
};
sdio_pins_a: sdio_pins_a@0 {
sdio_pins_a: sdio-pins-a-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
@@ -236,7 +236,7 @@
};
};
sdio_pins_od_a: sdio_pins_od_a@0 {
sdio_pins_od_a: sdio-pins-od-a-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
@@ -254,7 +254,7 @@
};
};
sdio_pins_b: sdio_pins_b@0 {
sdio_pins_b: sdio-pins-b-0 {
pins {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
@@ -267,7 +267,7 @@
};
};
sdio_pins_od_b: sdio_pins_od_b@0 {
sdio_pins_od_b: sdio-pins-od-b-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */

3
arch/arm/dts/stm32f7-u-boot.dtsi
View File

@@ -26,7 +26,6 @@
interrupt-names = "macirq", "eth_wake_irq";
snps,pbl = <8>;
snps,mixed-burst;
dma-ranges;
pinctrl-0 = <&ethernet_mii>;
phy-mode = "rmii";
phy-handle = <&phy0>;
@@ -43,7 +42,7 @@
};
};
qspi: quadspi@A0001000 {
qspi: spi@A0001000 {
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;

8
arch/arm/dts/stm32f746-disco-u-boot.dtsi
View File

@@ -212,7 +212,7 @@
};
};
usart1_pins_b: usart1@1 {
usart1_pins_b: usart1-1 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
@@ -229,7 +229,7 @@
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
qflash0: n25q128a {
qflash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -239,7 +239,3 @@
reg = <0>;
};
};
&timer5 {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/stm32f746-disco.dts
View File

@@ -19,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x800000>;
};

12
arch/arm/dts/stm32f746.dtsi
View File

@@ -264,12 +264,10 @@
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@@ -461,8 +459,8 @@
status = "disabled";
};
syscfg: system-config@40013800 {
compatible = "syscon";
syscfg: syscon@40013800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
};
@@ -529,7 +527,7 @@
};
pwrcfg: power-config@40007000 {
compatible = "syscon";
compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
};
@@ -551,7 +549,7 @@
assigned-clock-rates = <1000000>;
};
dma1: dma@40026000 {
dma1: dma-controller@40026000 {
compatible = "st,stm32-dma";
reg = <0x40026000 0x400>;
interrupts = <11>,
@@ -567,7 +565,7 @@
status = "disabled";
};
dma2: dma@40026400 {
dma2: dma-controller@40026400 {
compatible = "st,stm32-dma";
reg = <0x40026400 0x400>;
interrupts = <56>,

4
arch/arm/dts/stm32f769-disco-u-boot.dtsi
View File

@@ -215,7 +215,7 @@
};
};
usart1_pins_a: usart1@0 {
usart1_pins_a: usart1-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
@@ -228,7 +228,7 @@
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
flash0: mx66l51235l {
flash0: mx66l51235l@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

6
arch/arm/dts/stm32f769-disco.dts
View File

@@ -19,7 +19,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x1000000>;
};
@@ -30,11 +30,11 @@
leds {
compatible = "gpio-leds";
green {
led-green {
gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
red {
led-red {
gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
};
};

6
arch/arm/dts/stm32h7-u-boot.dtsi
View File

@@ -39,7 +39,7 @@
/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI
* firsct bank is bank@0
* first bank is bank@0
* second bank is bank@1
*/
bank1: bank@1 {
@@ -218,3 +218,7 @@
&sdmmc1 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&timer5 {
u-boot,dm-pre-reloc;
};

10
arch/arm/dts/stm32h743-pinctrl.dtsi
View File

@@ -163,7 +163,7 @@
#interrupt-cells = <2>;
};
i2c1_pins_a: i2c1@0 {
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
<STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
@@ -173,7 +173,7 @@
};
};
ethernet_rmii: rmii@0 {
ethernet_rmii: rmii-0 {
pins {
pinmux = <STM32_PINMUX('G', 11, AF11)>,
<STM32_PINMUX('G', 13, AF11)>,
@@ -256,7 +256,7 @@
};
};
usart1_pins: usart1@0 {
usart1_pins: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
bias-disable;
@@ -269,7 +269,7 @@
};
};
usart2_pins: usart2@0 {
usart2_pins: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
bias-disable;
@@ -282,7 +282,7 @@
};
};
usbotg_hs_pins_a: usbotg-hs@0 {
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */

37
arch/arm/dts/stm32h743.dtsi
View File

@@ -74,6 +74,7 @@
compatible = "st,stm32h7-spi";
reg = <0x40003800 0x400>;
interrupts = <36>;
resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
clocks = <&rcc SPI2_CK>;
status = "disabled";
@@ -85,12 +86,13 @@
compatible = "st,stm32h7-spi";
reg = <0x40003c00 0x400>;
interrupts = <51>;
resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
clocks = <&rcc SPI3_CK>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
compatible = "st,stm32h7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
@@ -144,21 +146,21 @@
dac1: dac@1 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
#io-channel-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
#io-channel-cells = <1>;
reg = <2>;
status = "disabled";
};
};
usart1: serial@40011000 {
compatible = "st,stm32f7-uart";
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
@@ -171,6 +173,7 @@
compatible = "st,stm32h7-spi";
reg = <0x40013000 0x400>;
interrupts = <35>;
resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
clocks = <&rcc SPI1_CK>;
status = "disabled";
};
@@ -181,6 +184,7 @@
compatible = "st,stm32h7-spi";
reg = <0x40013400 0x400>;
interrupts = <84>;
resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
clocks = <&rcc SPI4_CK>;
status = "disabled";
};
@@ -191,11 +195,12 @@
compatible = "st,stm32h7-spi";
reg = <0x40015000 0x400>;
interrupts = <85>;
resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
clocks = <&rcc SPI5_CK>;
status = "disabled";
};
dma1: dma@40020000 {
dma1: dma-controller@40020000 {
compatible = "st,stm32-dma";
reg = <0x40020000 0x400>;
interrupts = <11>,
@@ -213,7 +218,7 @@
status = "disabled";
};
dma2: dma@40020400 {
dma2: dma-controller@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
interrupts = <56>,
@@ -293,7 +298,17 @@
status = "disabled";
};
mdma1: dma@52000000 {
ltdc: display-controller@50001000 {
compatible = "st,stm32-ltdc";
reg = <0x50001000 0x200>;
interrupts = <88>, <89>;
resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
clocks = <&rcc LTDC_CK>;
clock-names = "lcd";
status = "disabled";
};
mdma1: dma-controller@52000000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
interrupts = <122>;
@@ -325,8 +340,8 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
};
syscfg: system-config@58000400 {
compatible = "syscon";
syscfg: syscon@58000400 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x58000400 0x400>;
};
@@ -336,6 +351,7 @@
compatible = "st,stm32h7-spi";
reg = <0x58001400 0x400>;
interrupts = <86>;
resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
clocks = <&rcc SPI6_CK>;
status = "disabled";
};
@@ -451,7 +467,6 @@
assigned-clock-parents = <&rcc LSE_CK>;
interrupt-parent = <&exti>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@@ -466,7 +481,7 @@
};
pwrcfg: power-config@58024800 {
compatible = "syscon";
compatible = "st,stm32-power-config", "syscon";
reg = <0x58024800 0x400>;
};

2
arch/arm/dts/stm32h743i-disco.dts
View File

@@ -17,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@d0000000 {
device_type = "memory";
reg = <0xd0000000 0x2000000>;
};

2
arch/arm/dts/stm32h743i-eval.dts
View File

@@ -53,7 +53,7 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@d0000000 {
device_type = "memory";
reg = <0xd0000000 0x2000000>;
};

7
arch/arm/dts/stm32mp15-u-boot.dtsi
View File

@@ -159,6 +159,13 @@
u-boot,dm-pre-proper;
};
/* temp = waiting kernel update */
&m4_rproc {
resets = <&rcc MCU_R>,
<&rcc MCU_HOLD_BOOT_R>;
reset-names = "mcu_rst", "hold_boot";
};
&pinctrl {
u-boot,dm-pre-reloc;
};

14
arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcom-u-boot.dtsi"
/ {
aliases {
/delete-property/ ethernet1;
};
};
/delete-node/ &ksz8851;

93
arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts Normal file
View File

@@ -0,0 +1,93 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcom.dtsi"
/ {
model = "DH Electronics STM32MP15xx DHCOM PicoITX";
compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx";
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc {
status = "disabled";
};
&dac {
status = "disabled";
};
&gpioa {
/*
* NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
* port power. This signal should be handled by USB power sequencing
* in order to turn on port power when USB bus is powered up, but so
* far there is no such functionality.
*/
usb-port-power {
gpio-hog;
gpios = <13 GPIO_ACTIVE_LOW>;
output-low;
line-name = "usb-port-power";
};
};
&i2c2 { /* On board-to-board connector (optional) */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c5 { /* On board-to-board connector */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};

15
arch/arm/dts/stm32mp15xx-dhcom.dtsi
View File

@@ -299,8 +299,8 @@
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -314,15 +314,6 @@
#address-cells = <1>;
#size-cells = <1>;
};
flash1: mx66l51235l@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&rng1 {
@@ -338,7 +329,7 @@
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,sig-dir;
st,neg-edge;

4
arch/arm/mach-stm32mp/cpu.c
View File

@@ -226,8 +226,8 @@ static void early_enable_caches(void)
if (IS_ENABLED(CONFIG_SPL_BUILD))
mmu_set_region_dcache_behaviour(
ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
DCACHE_DEFAULT_OPTION);
else
mmu_set_region_dcache_behaviour(STM32_DDR_BASE,

2
arch/arm/mach-stm32mp/spl.c
View File

@@ -55,6 +55,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
int spl_mmc_boot_partition(const u32 boot_device)
{
switch (boot_device) {
@@ -66,6 +67,7 @@ int spl_mmc_boot_partition(const u32 boot_device)
return -EINVAL;
}
}
#endif
#ifdef CONFIG_SPL_DISPLAY_PRINT
void spl_display_print(void)

22
board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
View File

@@ -31,6 +31,14 @@
arch = "arm";
compression = "none";
};
fdt-3 {
description = ".dtb";
data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
};
};
configurations {
@@ -64,6 +72,20 @@
fdt = "fdt-2";
};
config-5 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-picoitx_somrev0_boardrev0";
loadables = "uboot";
fdt = "fdt-3";
};
config-6 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-picoitx_somrev1_boardrev0";
loadables = "uboot";
fdt = "fdt-3";
};
/* Add 587-100..587-400 with fdt-2..fdt-4 here */
};
};

18
board/st/stm32mp1/fit_copro_kernel_dtb.its
View File

@@ -1,6 +1,20 @@
/*
* Compilation:
* mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
*
* M4 firmware to load with remoteproc: rproc-m4-fw.elf
*
* Files in linux build dir:
* - arch/arm/boot/zImage
* - arch/arm/boot/dts/stm32mp157c-dk2.dtb
* - arch/arm/boot/dts/stm32mp157c-ev1.dtb
*
* load mmc 0:4 $kernel_addr_r fit_copro_kernel_dtb.itb
* bootm $kernel_addr_r
* bootm $kernel_addr_r#dk2
* bootm $kernel_addr_r#ev1
* bootm $kernel_addr_r#dk2-m4
* bootm $kernel_addr_r#ev1-m4
*/
/dts-v1/;
@@ -29,8 +43,8 @@
arch = "arm";
os = "linux";
compression = "none";
load = <0xC0008000>;
entry = <0xC0008000>;
load = <0xC4000000>;
entry = <0xC4000000>;
hash-1 {
algo = "sha1";
};

6
board/st/stm32mp1/fit_kernel_dtb.its
View File

@@ -3,7 +3,7 @@
* mkimage -f fit_kernel_dtb.its fit_kernel_dtb.itb
*
* Files in linux build dir:
* - arch/arm/boot/zImage
* - arch/arm/boot/Image (gzipped in Image.gz)
* - arch/arm/boot/dts/stm32mp157c-dk2.dtb
* - arch/arm/boot/dts/stm32mp157c-ev1.dtb
*
@@ -23,11 +23,11 @@
images {
kernel {
description = "Linux kernel";
data = /incbin/("zImage");
data = /incbin/("Image.gz");
type = "kernel";
arch = "arm";
os = "linux";
compression = "none";
compression = "gzip";
load = <0xC0008000>;
entry = <0xC0008000>;
hash-1 {

9
board/st/stm32mp1/stm32mp1.c
View File

@@ -848,9 +848,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
{ "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, },
{ "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, },
};
char *boot_device;
if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
/* Check the boot-source and don't update MTD for serial or usb boot */
boot_device = env_get("boot_device");
if (!boot_device ||
(strcmp(boot_device, "serial") && strcmp(boot_device, "usb")))
if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
return 0;
}

2
configs/stm32mp15_dhcom_basic_defconfig
View File

@@ -57,7 +57,7 @@ CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02"
CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y

2
doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt
View File

@@ -45,6 +45,8 @@ Required properties:
- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
port#1 and must be <1> for PHY port#2, to select USB controller
Optional properties:
- vbus-supply: phandle to the regulator providing 5V vbus to the USB connector
Example:
usbphyc: usb-phy@5a006000 {

28
drivers/gpio/stm32_gpio.c
View File

@@ -212,11 +212,11 @@ static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
} else if (flags & GPIOD_IS_IN) {
stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
if (flags & GPIOD_PULL_UP)
stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
else if (flags & GPIOD_PULL_DOWN)
stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
}
if (flags & GPIOD_PULL_UP)
stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
else if (flags & GPIOD_PULL_DOWN)
stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
return 0;
}
@@ -243,16 +243,16 @@ static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
break;
case STM32_GPIO_MODE_IN:
dir_flags |= GPIOD_IS_IN;
switch (stm32_gpio_get_pupd(regs, idx)) {
case STM32_GPIO_PUPD_UP:
dir_flags |= GPIOD_PULL_UP;
break;
case STM32_GPIO_PUPD_DOWN:
dir_flags |= GPIOD_PULL_DOWN;
break;
default:
break;
}
break;
default:
break;
}
switch (stm32_gpio_get_pupd(regs, idx)) {
case STM32_GPIO_PUPD_UP:
dir_flags |= GPIOD_PULL_UP;
break;
case STM32_GPIO_PUPD_DOWN:
dir_flags |= GPIOD_PULL_DOWN;
break;
default:
break;

33
drivers/phy/phy-stm32-usbphyc.c
View File

@@ -59,6 +59,7 @@ struct stm32_usbphyc {
struct udevice *vdda1v8;
struct stm32_usbphyc_phy {
struct udevice *vdd;
struct udevice *vbus;
bool init;
bool powered;
} phys[MAX_PHYS];
@@ -244,6 +245,11 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy)
if (ret)
return ret;
}
if (usbphyc_phy->vbus) {
ret = regulator_set_enable(usbphyc_phy->vbus, true);
if (ret)
return ret;
}
usbphyc_phy->powered = true;
@@ -262,6 +268,11 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy)
if (stm32_usbphyc_is_powered(usbphyc))
return 0;
if (usbphyc_phy->vbus) {
ret = regulator_set_enable(usbphyc_phy->vbus, false);
if (ret)
return ret;
}
if (usbphyc_phy->vdd) {
ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
if (ret)
@@ -271,7 +282,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy)
return 0;
}
static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
static int stm32_usbphyc_get_regulator(ofnode node,
char *supply_name,
struct udevice **regulator)
{
@@ -281,19 +292,14 @@ static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
ret = ofnode_parse_phandle_with_args(node, supply_name,
NULL, 0, 0,
&regulator_phandle);
if (ret) {
dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
if (ret)
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
regulator_phandle.node,
regulator);
if (ret) {
dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
if (ret)
return ret;
}
return 0;
}
@@ -380,10 +386,17 @@ static int stm32_usbphyc_probe(struct udevice *dev)
usbphyc_phy->init = false;
usbphyc_phy->powered = false;
ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
ret = stm32_usbphyc_get_regulator(node, "phy-supply",
&usbphyc_phy->vdd);
if (ret)
if (ret) {
dev_err(dev, "Can't get phy-supply regulator\n");
return ret;
}
ret = stm32_usbphyc_get_regulator(node, "vbus-supply",
&usbphyc_phy->vbus);
if (ret)
usbphyc_phy->vbus = NULL;
node = dev_read_next_subnode(node);
}

13
drivers/pinctrl/pinctrl-stmfx.c
View File

@@ -343,8 +343,8 @@ static int stmfx_pinctrl_get_pins_count(struct udevice *dev)
}
/*
* STMFX pins[15:0] are called "gpio[15:0]"
* and STMFX pins[23:16] are called "agpio[7:0]"
* STMFX pins[15:0] are called "stmfx_gpio[15:0]"
* and STMFX pins[23:16] are called "stmfx_agpio[7:0]"
*/
#define MAX_PIN_NAME_LEN 7
static char pin_name[MAX_PIN_NAME_LEN];
@@ -352,9 +352,9 @@ static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < STMFX_MAX_GPIO)
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_gpio%u", selector);
else
snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16);
snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_agpio%u", selector - 16);
return pin_name;
}
@@ -408,8 +408,11 @@ static int stmfx_pinctrl_bind(struct udevice *dev)
{
struct stmfx_pinctrl *plat = dev_get_platdata(dev);
/* subnode name is not explicit: use father name */
device_set_name(dev, dev->parent->name);
return device_bind_driver_to_node(dev->parent,
"stmfx-gpio", "stmfx-gpio",
"stmfx-gpio", dev->parent->name,
dev_ofnode(dev), &plat->gpio);
};

24
drivers/pinctrl/pinctrl_stm32.c
View File

@@ -48,15 +48,15 @@ static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
"alt function",
};
static const char * const pinmux_output[] = {
[STM32_GPIO_PUPD_NO] = "bias-disable",
[STM32_GPIO_PUPD_UP] = "bias-pull-up",
[STM32_GPIO_PUPD_DOWN] = "bias-pull-down",
static const char * const pinmux_bias[] = {
[STM32_GPIO_PUPD_NO] = "",
[STM32_GPIO_PUPD_UP] = "pull-up",
[STM32_GPIO_PUPD_DOWN] = "pull-down",
};
static const char * const pinmux_input[] = {
[STM32_GPIO_OTYPE_PP] = "drive-push-pull",
[STM32_GPIO_OTYPE_OD] = "drive-open-drain",
[STM32_GPIO_OTYPE_PP] = "push-pull",
[STM32_GPIO_OTYPE_OD] = "open-drain",
};
static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
@@ -213,6 +213,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
selector, gpio_idx, mode);
priv = dev_get_priv(gpio_dev);
pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
switch (mode) {
@@ -224,20 +225,19 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
pinmux_bias[pupd]);
break;
case GPIOF_OUTPUT:
pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) &
PUPD_MASK;
snprintf(buf, size, "%s %s %s",
pinmux_mode[mode], pinmux_output[pupd],
pinmux_mode[mode], pinmux_bias[pupd],
label ? label : "");
break;
case GPIOF_INPUT:
otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
snprintf(buf, size, "%s %s %s",
snprintf(buf, size, "%s %s %s %s",
pinmux_mode[mode], pinmux_input[otype],
label ? label : "");
pinmux_bias[pupd], label ? label : "");
break;
}

108
drivers/remoteproc/stm32_copro.c
View File

@@ -8,30 +8,21 @@
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
#include <regmap.h>
#include <remoteproc.h>
#include <reset.h>
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#define RCC_GCR_HOLD_BOOT 0
#define RCC_GCR_RELEASE_BOOT 1
/**
* struct stm32_copro_privdata - power processor private data
* @reset_ctl: reset controller handle
* @hold_boot_regmap: regmap for remote processor reset hold boot
* @hold_boot_offset: offset of the register controlling the hold boot setting
* @hold_boot_mask: bitmask of the register for the hold boot field
* @hold_boot: hold boot controller handle
* @rsc_table_addr: resource table address
*/
struct stm32_copro_privdata {
struct reset_ctl reset_ctl;
struct regmap *hold_boot_regmap;
uint hold_boot_offset;
uint hold_boot_mask;
struct reset_ctl hold_boot;
ulong rsc_table_addr;
};
@@ -43,69 +34,27 @@ struct stm32_copro_privdata {
static int stm32_copro_probe(struct udevice *dev)
{
struct stm32_copro_privdata *priv;
struct regmap *regmap;
const fdt32_t *cell;
int len, ret;
int ret;
priv = dev_get_priv(dev);
regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-holdboot");
if (IS_ERR(regmap)) {
dev_err(dev, "unable to find holdboot regmap (%ld)\n",
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
cell = dev_read_prop(dev, "st,syscfg-holdboot", &len);
if (len < 3 * sizeof(fdt32_t)) {
dev_err(dev, "holdboot offset and mask not available\n");
return -EINVAL;
}
priv->hold_boot_regmap = regmap;
priv->hold_boot_offset = fdtdec_get_number(cell + 1, 1);
priv->hold_boot_mask = fdtdec_get_number(cell + 2, 1);
ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
ret = reset_get_by_name(dev, "mcu_rst", &priv->reset_ctl);
if (ret) {
dev_err(dev, "failed to get reset (%d)\n", ret);
return ret;
}
ret = reset_get_by_name(dev, "hold_boot", &priv->hold_boot);
if (ret) {
dev_err(dev, "failed to get hold boot (%d)\n", ret);
return ret;
}
dev_dbg(dev, "probed\n");
return 0;
}
/**
* stm32_copro_set_hold_boot() - Hold boot bit management
* @dev: corresponding STM32 remote processor device
* @hold: hold boot value
* @return 0 if all went ok, else corresponding -ve error
*/
static int stm32_copro_set_hold_boot(struct udevice *dev, bool hold)
{
struct stm32_copro_privdata *priv;
uint val;
int ret;
priv = dev_get_priv(dev);
val = hold ? RCC_GCR_HOLD_BOOT : RCC_GCR_RELEASE_BOOT;
/*
* Note: shall run an SMC call (STM32_SMC_RCC) if platform is secured.
* To be updated when the code for this SMC service is available which
* is not the case for the time being.
*/
ret = regmap_update_bits(priv->hold_boot_regmap, priv->hold_boot_offset,
priv->hold_boot_mask, val);
if (ret)
dev_err(dev, "failed to set hold boot\n");
return ret;
}
/**
* stm32_copro_device_to_virt() - Convert device address to virtual address
* @dev: corresponding STM32 remote processor device
@@ -149,9 +98,11 @@ static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size)
priv = dev_get_priv(dev);
ret = stm32_copro_set_hold_boot(dev, true);
if (ret)
ret = reset_assert(&priv->hold_boot);
if (ret) {
dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret);
return ret;
}
ret = reset_assert(&priv->reset_ctl);
if (ret) {
@@ -180,23 +131,26 @@ static int stm32_copro_start(struct udevice *dev)
priv = dev_get_priv(dev);
/* move hold boot from true to false start the copro */
ret = stm32_copro_set_hold_boot(dev, false);
if (ret)
ret = reset_deassert(&priv->hold_boot);
if (ret) {
dev_err(dev, "Unable to deassert hold boot (ret=%d)\n", ret);
return ret;
}
/*
* Once copro running, reset hold boot flag to avoid copro
* rebooting autonomously
* rebooting autonomously (error should never occur)
*/
ret = stm32_copro_set_hold_boot(dev, true);
writel(ret ? TAMP_COPRO_STATE_OFF : TAMP_COPRO_STATE_CRUN,
TAMP_COPRO_STATE);
if (!ret)
/* Store rsc_address in bkp register */
writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS);
ret = reset_assert(&priv->hold_boot);
if (ret)
dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret);
return ret;
/* indicates that copro is running */
writel(TAMP_COPRO_STATE_CRUN, TAMP_COPRO_STATE);
/* Store rsc_address in bkp register */
writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS);
return 0;
}
/**
@@ -211,9 +165,11 @@ static int stm32_copro_reset(struct udevice *dev)
priv = dev_get_priv(dev);
ret = stm32_copro_set_hold_boot(dev, true);
if (ret)
ret = reset_assert(&priv->hold_boot);
if (ret) {
dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret);
return ret;
}
ret = reset_assert(&priv->reset_ctl);
if (ret) {

17
drivers/reset/stm32-reset.c
View File

@@ -14,6 +14,9 @@
#include <asm/io.h>
#include <linux/bitops.h>
/* offset of register without set/clear management */
#define RCC_MP_GCR_OFFSET 0x10C
/* reset clear offset for STM32MP RCC */
#define RCC_CL 0x4
@@ -40,8 +43,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)
reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
/* reset assert is done in rcc set register */
writel(BIT(offset), priv->base + bank);
if (bank != RCC_MP_GCR_OFFSET)
/* reset assert is done in rcc set register */
writel(BIT(offset), priv->base + bank);
else
clrbits_le32(priv->base + bank, BIT(offset));
else
setbits_le32(priv->base + bank, BIT(offset));
@@ -57,8 +63,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
/* reset deassert is done in rcc clr register */
writel(BIT(offset), priv->base + bank + RCC_CL);
if (bank != RCC_MP_GCR_OFFSET)
/* reset deassert is done in rcc clr register */
writel(BIT(offset), priv->base + bank + RCC_CL);
else
setbits_le32(priv->base + bank, BIT(offset));
else
clrbits_le32(priv->base + bank, BIT(offset));

1
include/dt-bindings/reset/stm32mp1-resets.h
View File

@@ -7,6 +7,7 @@
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
#define _DT_BINDINGS_STM32MP1_RESET_H_
#define MCU_HOLD_BOOT_R 2144
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080