Merge tag 'u-boot-amlogic-20210514' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro - usb: dwc3-meson-g12a: skip phy on -ENODATA aswell - net: dwmac_meson8b: do not set TX delay in TXID & RXID - net: designware: meson8b: add g12a compatible
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7
arch/arm/dts/meson-g12b-gtking-pro-u-boot.dtsi
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7
arch/arm/dts/meson-g12b-gtking-pro-u-boot.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include "meson-g12-common-u-boot.dtsi"
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7
arch/arm/dts/meson-g12b-gtking-u-boot.dtsi
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arch/arm/dts/meson-g12b-gtking-u-boot.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include "meson-g12-common-u-boot.dtsi"
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@@ -59,8 +59,6 @@ static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata)
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switch (edata->phy_interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* Set RGMII mode */
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setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
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AXG_ETH_REG_0_TX_PHASE(1) |
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@@ -69,6 +67,15 @@ static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata)
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AXG_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
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setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
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AXG_ETH_REG_0_TX_RATIO(4) |
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AXG_ETH_REG_0_PHY_CLK_EN |
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AXG_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set RMII mode */
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out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
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@@ -90,8 +97,6 @@ static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata)
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switch (edata->phy_interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* Set RGMII mode */
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setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
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GX_ETH_REG_0_TX_PHASE(1) |
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@@ -101,6 +106,16 @@ static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata)
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
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setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
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GX_ETH_REG_0_TX_RATIO(4) |
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GX_ETH_REG_0_PHY_CLK_EN |
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GX_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set RMII mode */
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out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
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@@ -133,6 +148,7 @@ static int dwmac_meson8b_probe(struct udevice *dev)
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static const struct udevice_id dwmac_meson8b_ids[] = {
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{ .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx },
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{ .compatible = "amlogic,meson-g12a-dwmac", .data = (ulong)dwmac_setup_axg },
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{ .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg },
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{ }
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};
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@@ -298,7 +298,7 @@ static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
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for (i = 0 ; i < PHY_COUNT ; ++i) {
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ret = generic_phy_get_by_name(priv->dev, phy_names[i],
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&priv->phys[i]);
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if (ret == -ENOENT)
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if (ret == -ENOENT || ret == -ENODATA)
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continue;
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if (ret)
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