eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: socfpga: Adjust NAND register layout on Arria10

Browse Source 
Adjust the NAND register size on Arria10 to reflect reality.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Marek Vasut
2018-05-07 22:22:26 +02:00
parent 42f4b83b52
commit 64eeb15854
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/socfpga_arria10.dtsi
View File

@@ -637,8 +637,8 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
reg = <0xffb90000 0x72000>,
<0xffb80000 0x10000>;
reg = <0xffb90000 0x20>,
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 99 4>;
dma-mask = <0xffffffff>;