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Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

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This commit is contained in:
Tom Rini
2021-12-03 09:02:49 -05:00
parent 5b9ee01685 c0ffc12a70
commit 558002a0f2
19 changed files with 1516 additions and 409 deletions
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13
arch/riscv/cpu/fu740/Kconfig
View File

@@ -40,3 +40,16 @@ config SIFIVE_FU740
imply DM_I2C
imply SYS_I2C_OCORES
imply SPL_I2C
if ENV_IS_IN_SPI_FLASH
config ENV_OFFSET
default 0x505000
config ENV_SIZE
default 0x20000
config ENV_SECT_SIZE
default 0x10000
endif # ENV_IS_IN_SPI_FLASH

11
arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
View File

@@ -16,6 +16,10 @@
u-boot,dm-spl;
};
config {
u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */
};
hfclk {
u-boot,dm-spl;
};
@@ -30,6 +34,13 @@
clocks = <&rtcclk>;
};
&qspi0 {
u-boot,dm-spl;
flash@0 {
u-boot,dm-spl;
};
};
&spi0 {
mmc@0 {
u-boot,dm-spl;

526
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
View File

@@ -1,417 +1,157 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020 Microchip Technology Inc */
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
/dts-v1/;
#include "dt-bindings/clock/microchip-mpfs-clock.h"
#include "microchip-mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip MPFS Icicle Kit";
compatible = "microchip,mpfs-icicle-kit";
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
serial0 = &uart0;
ethernet0 = &emac1;
serial1 = &uart1;
ethernet0 = &mac1;
};
chosen {
stdout-path = "serial0";
stdout-path = "serial1";
};
cpucomplex: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpus {
timebase-frequency = <RTCCLK_FREQ>;
cpu0: cpu@0 {
clocks = <&clkcfg CLK_CPU>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
status = "disabled";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu0intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
clocks = <&clkcfg CLK_CPU>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu1intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
clocks = <&clkcfg CLK_CPU>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu2intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
clocks = <&clkcfg CLK_CPU>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu3intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
clocks = <&clkcfg CLK_CPU>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu4intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
clock-output-names = "msspllclk";
};
ddr: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
clocks = <&clkcfg CLK_DDRC>;
};
soc: soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "microchip,mpfs-icicle-kit", "simple-bus";
reserved-memory {
ranges;
clint0: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&cpu0intc 3 &cpu0intc 7
&cpu1intc 3 &cpu1intc 7
&cpu2intc 3 &cpu2intc 7
&cpu3intc 3 &cpu3intc 7
&cpu4intc 3 &cpu4intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
clock-frequency = <RTCCLK_FREQ>;
};
cachecontroller: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1 2 3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,max-priority = <7>;
riscv,ndev = <186>;
interrupt-controller;
interrupts-extended = <
&cpu0intc 11
&cpu1intc 11 &cpu1intc 9
&cpu2intc 11 &cpu2intc 9
&cpu3intc 11 &cpu3intc 9
&cpu4intc 11 &cpu4intc 9>;
};
uart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <90>;
clocks = <&clkcfg CLK_MMUART0>;
status = "okay";
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg-names = "mss_sysreg";
clocks = <&refclk>;
#clock-cells = <1>;
clock-output-names = "cpu", "axi", "ahb", "envm",
"mac0", "mac1", "mmc", "timer",
"mmuart0", "mmuart1", "mmuart2",
"mmuart3", "mmuart4", "spi0", "spi1",
"i2c0", "i2c1", "can0", "can1", "usb",
"reserved", "rtc", "qspi", "gpio0",
"gpio1", "gpio2", "ddrc", "fic0",
"fic1", "fic2", "fic3", "athena",
"cfm";
};
emmc: mmc@20008000 {
compatible = "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88 89>;
pinctrl-names = "default";
clocks = <&clkcfg CLK_MMC>;
bus-width = <4>;
cap-mmc-highspeed;
mmc-ddr-3_3v;
max-frequency = <200000000>;
non-removable;
no-sd;
no-sdio;
voltage-ranges = <3300 3300>;
status = "okay";
};
sdcard: sd@20008000 {
compatible = "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>;
pinctrl-names = "default";
clocks = <&clkcfg CLK_MMC>;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
card-detect-delay = <200>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <200000000>;
status = "disabled";
};
uart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <91>;
clocks = <&clkcfg CLK_MMUART1>;
status = "okay";
};
uart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <92>;
clocks = <&clkcfg CLK_MMUART2>;
status = "okay";
};
uart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <93>;
clocks = <&clkcfg CLK_MMUART3>;
status = "okay";
};
i2c0: i2c@2010a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "microchip,mpfs-mss-i2c";
reg = <0x0 0x2010a000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <58>;
clocks = <&clkcfg CLK_I2C0>;
status = "disabled";
};
i2c1: i2c@2010b000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "microchip,mpfs-mss-i2c";
reg = <0x0 0x2010b000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <61>;
clocks = <&clkcfg CLK_I2C1>;
status = "disabled";
pac193x@10 {
compatible = "microchip,pac1934";
reg = <0x10>;
samp-rate = <64>;
status = "disabled";
ch1: channel0 {
uohms-shunt-res = <10000>;
rail-name = "VDD";
channel_enabled;
};
ch2: channel1 {
uohms-shunt-res = <10000>;
rail-name = "VDDA25";
channel_enabled;
};
ch3: channel2 {
uohms-shunt-res = <10000>;
rail-name = "VDD25";
channel_enabled;
};
ch4: channel3 {
uohms-shunt-res = <10000>;
rail-name = "VDDA";
channel_enabled;
};
};
};
emac0: ethernet@20110000 {
compatible = "microchip,mpfs-mss-gem";
reg = <0x0 0x20110000 0x0 0x2000>;
interrupt-parent = <&plic>;
interrupts = <64 65 66 67>;
local-mac-address = [56 34 00 FC 00 02];
phy-mode = "sgmii";
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
clock-names = "pclk", "hclk";
status = "disabled";
#size-cells = <2>;
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&phy0>;
phy0: ethernet-phy@8 {
reg = <8>;
ti,fifo-depth = <0x01>;
};
fabricbuf0: fabricbuf@0 {
compatible = "shared-dma-pool";
reg = <0x0 0xae000000 0x0 0x2000000>;
label = "fabricbuf0-ddr-c";
};
emac1: ethernet@20112000 {
compatible = "microchip,mpfs-mss-gem";
reg = <0x0 0x20112000 0x0 0x2000>;
interrupt-parent = <&plic>;
interrupts = <70 71 72 73>;
local-mac-address = [00 00 00 00 00 00];
phy-mode = "sgmii";
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
ti,fifo-depth = <0x01>;
};
fabricbuf1: fabricbuf@1 {
compatible = "shared-dma-pool";
reg = <0x0 0xc0000000 0x0 0x8000000>;
label = "fabricbuf1-ddr-nc";
};
gpio: gpio@20122000 {
compatible = "microchip,mpfs-mss-gpio";
interrupt-parent = <&plic>;
interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34 35 36 37 38 39
40 41 42 43 44>;
gpio-controller;
clocks = <&clkcfg CLK_GPIO2>;
reg = <0x00 0x20122000 0x0 0x1000>;
reg-names = "control";
#gpio-cells = <2>;
status = "disabled";
fabricbuf2: fabricbuf@2 {
compatible = "shared-dma-pool";
reg = <0x0 0xd8000000 0x0 0x8000000>;
label = "fabricbuf2-ddr-nc-wcb";
};
};
udmabuf0 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf-ddr-c0";
minor-number = <0>;
size = <0x0 0x2000000>;
memory-region = <&fabricbuf0>;
sync-mode = <3>;
};
udmabuf1 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf-ddr-nc0";
minor-number = <1>;
size = <0x0 0x8000000>;
memory-region = <&fabricbuf1>;
sync-mode = <3>;
};
udmabuf2 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf-ddr-nc-wcb0";
minor-number = <2>;
size = <0x0 0x8000000>;
memory-region = <&fabricbuf2>;
sync-mode = <3>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2e000000>;
clocks = <&clkcfg CLK_DDRC>;
status = "okay";
};
ddrc_cache_hi: memory@1000000000 {
device_type = "memory";
reg = <0x10 0x0 0x0 0x40000000>;
clocks = <&clkcfg CLK_DDRC>;
status = "okay";
};
};
&uart1 {
status = "okay";
};
&mmc {
status = "okay";
bus-width = <4>;
disable-wp;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
pac193x: pac193x@10 {
compatible = "microchip,pac1934";
reg = <0x10>;
samp-rate = <64>;
status = "okay";
ch1: channel0 {
uohms-shunt-res = <10000>;
rail-name = "VDDREG";
channel_enabled;
};
ch2: channel1 {
uohms-shunt-res = <10000>;
rail-name = "VDDA25";
channel_enabled;
};
ch3: channel2 {
uohms-shunt-res = <10000>;
rail-name = "VDD25";
channel_enabled;
};
ch4: channel3 {
uohms-shunt-res = <10000>;
rail-name = "VDDA_REG";
channel_enabled;
};
};
};
&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
ti,fifo-depth = <0x1>;
};
};

571
arch/riscv/dts/microchip-mpfs.dtsi Normal file
View File

@@ -0,0 +1,571 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
#include "dt-bindings/clock/microchip-mpfs-clock.h"
#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h"
#include "dt-bindings/interrupt-controller/riscv-hart.h"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PolarFire SoC";
compatible = "microchip,mpfs";
chosen {
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "microchip,mpfs-soc", "simple-bus";
ranges;
clint: clint@2000000 {
compatible = "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended =
<&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
&cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
&cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
&cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
&cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
};
cachecontroller: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_L2_METADATA_CORR
PLIC_INT_L2_METADATA_UNCORR
PLIC_INT_L2_DATA_CORR>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
};
pdma: pdma@3000000 {
compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
#dma-cells = <1>;
};
plic: interrupt-controller@c000000 {
compatible = "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
#interrupt-cells = <1>;
riscv,ndev = <186>;
interrupt-controller;
interrupts-extended = <&cpu0_intc HART_INT_M_EXT
&cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
&cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
&cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
&cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
};
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
clock-output-names = "msspllclk";
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg-names = "mss_sysreg";
clocks = <&refclk>;
#clock-cells = <1>;
clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
"mac0", "mac1", "mmc", "timer", /* 4-7 */
"mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
"mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
"i2c1", "can0", "can1", "usb", /* 16-19 */
"rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
"gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
"fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
};
/* Common node entry for eMMC/SD */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
clocks = <&clkcfg CLK_MMC>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>;
max-frequency = <200000000>;
status = "disabled";
};
uart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART0>;
clocks = <&clkcfg CLK_MMUART0>;
status = "disabled"; /* Reserved for the HSS */
};
uart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART1>;
clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
uart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART2>;
clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
uart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART3>;
clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
uart4: serial@20106000 {
compatible = "ns16550a";
reg = <0x0 0x20106000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART4>;
clocks = <&clkcfg CLK_MMUART4>;
status = "disabled";
};
spi0: spi@20108000 {
compatible = "microchip,mpfs-spi";
reg = <0x0 0x20108000 0x0 0x1000>;
clocks = <&clkcfg CLK_SPI0>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_SPI0>;
num-cs = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@20109000 {
compatible = "microchip,mpfs-spi";
reg = <0x0 0x20109000 0x0 0x1000>;
clocks = <&clkcfg CLK_SPI1>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_SPI1>;
num-cs = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@2010a000 {
compatible = "microchip,mpfs-i2c";
reg = <0x0 0x2010a000 0x0 0x1000>;
clocks = <&clkcfg CLK_I2C0>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_I2C0_MAIN>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@2010b000 {
compatible = "microchip,mpfs-i2c";
reg = <0x0 0x2010b000 0x0 0x1000>;
clocks = <&clkcfg CLK_I2C1>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_I2C1_MAIN>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can0: can@2010c000 {
compatible = "microchip,mpfs-can-uio";
reg = <0x0 0x2010c000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN0>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_CAN0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can1: can@2010d000 {
compatible = "microchip,mpfs-can-uio";
reg = <0x0 0x2010d000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN1>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_CAN1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MAC0_INT
PLIC_INT_MAC0_QUEUE1
PLIC_INT_MAC0_QUEUE2
PLIC_INT_MAC0_QUEUE3
PLIC_INT_MAC0_EMAC
PLIC_INT_MAC0_MMSL>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MAC1_INT
PLIC_INT_MAC1_QUEUE1
PLIC_INT_MAC1_QUEUE2
PLIC_INT_MAC1_QUEUE3
PLIC_INT_MAC1_EMAC
PLIC_INT_MAC1_MMSL>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gpio0: gpio@20120000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20120000 0x0 0x1000>;
reg-names = "control";
clocks = <&clkcfg CLK_GPIO0>;
interrupt-parent = <&plic>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio@20121000 {
compatible = "microchip,mpfs-gpio";
reg = <000 0x20121000 0x0 0x1000>;
reg-names = "control";
clocks = <&clkcfg CLK_GPIO1>;
interrupt-parent = <&plic>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio@20122000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
reg-names = "control";
clocks = <&clkcfg CLK_GPIO2>;
interrupt-parent = <&plic>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
rtc: rtc@20124000 {
compatible = "microchip,mpfs-rtc";
reg = <0x0 0x20124000 0x0 0x1000>;
clocks = <&clkcfg CLK_RTC>;
clock-names = "rtc";
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
usb: usb@20201000 {
compatible = "microchip,mpfs-usb-host";
reg = <0x0 0x20201000 0x0 0x1000>;
reg-names = "mc","control";
clocks = <&clkcfg CLK_USB>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
interrupt-names = "dma","mc";
dr_mode = "host";
status = "disabled";
};
qspi: qspi@21000000 {
compatible = "microchip,mpfs-qspi";
reg = <0x0 0x21000000 0x0 0x1000>;
clocks = <&clkcfg CLK_QSPI>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_QSPI>;
num-cs = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mbox: mailbox@37020000 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_G5C_MESSAGE>;
#mbox-cells = <1>;
status = "disabled";
};
pcie: pcie@2000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
clock-names = "fic0", "fic1", "fic3";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_FABRIC_F2H_2>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
msi-parent = <&pcie>;
msi-controller;
mchp,axi-m-atr0 = <0x10 0x0>;
status = "disabled";
pcie_intc: legacy-interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
syscontroller: syscontroller {
compatible = "microchip,mpfs-sys-controller";
#address-cells = <1>;
#size-cells = <1>;
mboxes = <&mbox 0>;
};
hwrandom: hwrandom {
compatible = "microchip,mpfs-rng";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
serialnum: serialnum {
compatible = "microchip,mpfs-serial-number";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
fpgadigest: fpgadigest {
compatible = "microchip,mpfs-digest";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
devicecert: cert {
compatible = "microchip,mpfs-device-cert";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
signature: signature {
compatible = "microchip,mpfs-signature";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
};
};

5
board/microchip/mpfs_icicle/Kconfig
View File

@@ -45,5 +45,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply MMC_WRITE
imply MMC_SDHCI
imply MMC_SDHCI_CADENCE
imply MMC_SDHCI_ADMA
imply MMC_HS200_SUPPORT
imply CMD_I2C
imply DM_I2C
imply SYS_I2C_MICROCHIP
endif

17
board/microchip/mpfs_icicle/mpfs_icicle.c
View File

@@ -119,7 +119,22 @@ int board_late_init(void)
if (icicle_mac_addr[idx] == ':')
icicle_mac_addr[idx] = ' ';
}
env_set("icicle_mac_addr", icicle_mac_addr);
env_set("icicle_mac_addr0", icicle_mac_addr);
mac_addr[5] = device_serial_number[0] + 1;
icicle_mac_addr[0] = '[';
sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
icicle_mac_addr[18] = ']';
icicle_mac_addr[19] = '\0';
for (idx = 0; idx < 20; idx++) {
if (icicle_mac_addr[idx] == ':')
icicle_mac_addr[idx] = ' ';
}
env_set("icicle_mac_addr1", icicle_mac_addr);
return 0;
}

1
board/sifive/unmatched/Kconfig
View File

@@ -26,6 +26,7 @@ config SPL_OPENSBI_LOAD_ADDR
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SIFIVE_FU740
select ENV_IS_IN_SPI_FLASH
select SUPPORT_SPL
select RESET_SIFIVE
select BINMAN

3
board/sifive/unmatched/spl.c
View File

@@ -22,6 +22,7 @@
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
#define MODE_SELECT_REG 0x1000
#define MODE_SELECT_SPI 0x6
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
@@ -123,6 +124,8 @@ u32 spl_boot_device(void)
u32 boot_device = mode_select & MODE_SELECT_MASK;
switch (boot_device) {
case MODE_SELECT_SPI:
return BOOT_DEVICE_SPI;
case MODE_SELECT_SD:
return BOOT_DEVICE_MMC1;
default:

1
configs/microchip_mpfs_icicle_defconfig
View File

@@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
CONFIG_TARGET_MICROCHIP_ICICLE=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_SBI_V01=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y

6
configs/sifive_unmatched_defconfig
View File

@@ -8,6 +8,7 @@ CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
CONFIG_SPL_MMC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_AHCI=y
CONFIG_TARGET_SIFIVE_UNMATCHED=y
@@ -23,17 +24,22 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_PWM=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x54
CONFIG_E1000=y
CONFIG_NVME=y

7
doc/board/microchip/mpfs_icicle.rst
View File

@@ -20,6 +20,7 @@ The support for following drivers are already enabled:
2. Microchip Clock Driver.
3. Cadence MACB ethernet driver for networking support.
4. Cadence MMC Driver for eMMC/SD support.
5. Microchip I2C Driver.
Booting from eMMC using HSS
---------------------------
@@ -214,7 +215,8 @@ GPT partition.
Booting
~~~~~~~
You should see the U-Boot prompt on UART0.
You should see the U-Boot prompt on UART1.
(Note: UART0 is reserved for HSS)
Sample boot log from MPFS Icicle Kit
''''''''''''''''''''''''''''''''''''
@@ -451,7 +453,8 @@ copied payload and Linux image.
sudo dd if=<payload_binary> of=/dev/sdX2 bs=512
You should see the U-Boot prompt on UART0.
You should see the U-Boot prompt on UART1.
(Note: UART0 is reserved for HSS)
GUID type
~~~~~~~~~

31
doc/board/sifive/unmatched.rst
View File

@@ -534,3 +534,34 @@ Sample boot log from HiFive Unmatched board
OpenEmbedded nodistro.0 unmatched ttySIF0
unmatched login:
Booting from SPI
----------------
Use Building steps from "Booting from uSD using U-Boot SPL" section.
Partition the SPI in Linux via mtdblock. The partition types here are
"HiFive Unleashed FSBL", "HiFive Unleashed BBL", and "U-Boot environment"
for partitions one through three respectively.
.. code-block:: none
sgdisk --clear -a 1 \
--new=1:40:2087 --change-name=1:spl --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
--new=2:2088:10279 --change-name=2:uboot --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
--new=3:10280:10535 --change-name=3:env --typecode=3:3DE21764-95BD-54BD-A5C3-4ABE786F38A8 \
/dev/mtdblock0
Write U-boot SPL and U-boot to their partitions.
.. code-block:: none
dd if=u-boot-spl.bin of=/dev/mtdblock0 bs=4096 seek=5 conv=sync
dd if=u-boot.itb of=/dev/mtdblock0 bs=4096 seek=261 conv=sync
Power off the board.
Change DIP switches MSEL[3:0] to 0110.
Power up the board.

6
drivers/i2c/Kconfig
View File

@@ -250,6 +250,12 @@ config SYS_I2C_MESON
internal buffer holding up to 8 bytes for transfers and supports
both 7-bit and 10-bit addresses.
config SYS_I2C_MICROCHIP
bool "Microchip I2C driver"
help
Add support for the Microchip I2C driver. This is operating on
standard mode up to 100 kbits/s and fast mode up to 400 kbits/s.
config SYS_I2C_MXC
bool "NXP MXC I2C driver"
help

1
drivers/i2c/Makefile
View File

@@ -28,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o
obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o

482
drivers/i2c/i2c-microchip.c Normal file
View File

@@ -0,0 +1,482 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Microchip I2C controller driver
*
* Copyright (C) 2021 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <i2c.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#define MICROCHIP_I2C_TIMEOUT (1000 * 60)
#define MPFS_I2C_CTRL (0x00)
#define CTRL_CR0 (0x00)
#define CTRL_CR1 (0x01)
#define CTRL_AA BIT(2)
#define CTRL_SI BIT(3)
#define CTRL_STO BIT(4)
#define CTRL_STA BIT(5)
#define CTRL_ENS1 BIT(6)
#define CTRL_CR2 (0x07)
#define MPFS_I2C_STATUS (0x04)
#define STATUS_BUS_ERROR (0x00)
#define STATUS_M_START_SENT (0x08)
#define STATUS_M_REPEATED_START_SENT (0x10)
#define STATUS_M_SLAW_ACK (0x18)
#define STATUS_M_SLAW_NACK (0x20)
#define STATUS_M_TX_DATA_ACK (0x28)
#define STATUS_M_TX_DATA_NACK (0x30)
#define STATUS_M_ARB_LOST (0x38)
#define STATUS_M_SLAR_ACK (0x40)
#define STATUS_M_SLAR_NACK (0x48)
#define STATUS_M_RX_DATA_ACKED (0x50)
#define STATUS_M_RX_DATA_NACKED (0x58)
#define STATUS_S_SLAW_ACKED (0x60)
#define STATUS_S_ARB_LOST_SLAW_ACKED (0x68)
#define STATUS_S_GENERAL_CALL_ACKED (0x70)
#define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED (0x78)
#define STATUS_S_RX_DATA_ACKED (0x80)
#define STATUS_S_RX_DATA_NACKED (0x88)
#define STATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90)
#define STATUS_S_GENERAL_CALL_RX_DATA_NACKED (0x98)
#define STATUS_S_RX_STOP (0xA0)
#define STATUS_S_SLAR_ACKED (0xA8)
#define STATUS_S_ARB_LOST_SLAR_ACKED (0xB0)
#define STATUS_S_TX_DATA_ACK (0xb8)
#define STATUS_S_TX_DATA_NACK (0xC0)
#define STATUS_LAST_DATA_ACK (0xC8)
#define STATUS_M_SMB_MASTER_RESET (0xD0)
#define STATUS_S_SCL_LOW_TIMEOUT (0xD8)
#define STATUS_NO_STATE_INFO (0xF8)
#define MPFS_I2C_DATA (0x08)
#define MPFS_I2C_SLAVE0_ADDR (0x0c)
#define MPFS_I2C_SMBUS (0x10)
#define MPFS_I2C_FREQ (0x14)
#define MPFS_I2C_GLITCHREG (0x18)
#define MPFS_I2C_SLAVE1_ADDR (0x1c)
#define PCLK_DIV_256 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
#define PCLK_DIV_224 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
#define PCLK_DIV_192 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
#define PCLK_DIV_160 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
#define PCLK_DIV_960 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
#define PCLK_DIV_120 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
#define PCLK_DIV_60 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
#define BCLK_DIV_8 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
#define CLK_MASK ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
/*
* mpfs_i2c_bus - I2C bus context
* @base: pointer to register struct
* @msg_len: number of bytes transferred in msg
* @msg_err: error code for completed message
* @i2c_clk: clock reference for i2c input clock
* @clk_rate: current i2c bus clock rate
* @buf: ptr to msg buffer for easier use.
* @addr: i2c address.
* @isr_status: cached copy of local ISR status.
*/
struct mpfs_i2c_bus {
void __iomem *base;
size_t msg_len;
int msg_err;
struct clk i2c_clk;
u32 clk_rate;
u8 *buf;
u8 addr;
u32 isr_status;
};
static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
{
return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
}
static void mpfs_i2c_int_clear(struct mpfs_i2c_bus *bus)
{
u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl &= ~CTRL_SI;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
}
static void mpfs_i2c_core_disable(struct mpfs_i2c_bus *bus)
{
u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl &= ~CTRL_ENS1;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
}
static void mpfs_i2c_core_enable(struct mpfs_i2c_bus *bus)
{
u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl |= CTRL_ENS1;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
}
static void mpfs_i2c_reset(struct mpfs_i2c_bus *bus)
{
mpfs_i2c_core_disable(bus);
mpfs_i2c_core_enable(bus);
}
static inline void mpfs_i2c_stop(struct mpfs_i2c_bus *bus)
{
u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl |= CTRL_STO;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
}
static inline int mpfs_generate_divisor(u32 rate, u8 *code)
{
int ret = 0;
if (rate >= 960)
*code = PCLK_DIV_960;
else if (rate >= 256)
*code = PCLK_DIV_256;
else if (rate >= 224)
*code = PCLK_DIV_224;
else if (rate >= 192)
*code = PCLK_DIV_192;
else if (rate >= 160)
*code = PCLK_DIV_160;
else if (rate >= 120)
*code = PCLK_DIV_120;
else if (rate >= 60)
*code = PCLK_DIV_60;
else if (rate >= 8)
*code = BCLK_DIV_8;
else
ret = -EINVAL;
return ret;
}
static int mpfs_i2c_init(struct mpfs_i2c_bus *bus, struct udevice *dev)
{
u32 clk_rate, divisor;
u8 clkval, ctrl;
int ret;
ret = clk_get_by_index(dev, 0, &bus->i2c_clk);
if (ret)
return -EINVAL;
ret = clk_enable(&bus->i2c_clk);
if (ret)
return ret;
clk_rate = clk_get_rate(&bus->i2c_clk);
if (!clk_rate)
return -EINVAL;
clk_free(&bus->i2c_clk);
divisor = clk_rate / bus->clk_rate;
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl &= ~CLK_MASK;
ret = mpfs_generate_divisor(divisor, &clkval);
if (ret)
return -EINVAL;
ctrl |= clkval;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
ctrl = readl(bus->base + MPFS_I2C_CTRL);
/* Reset I2C core */
mpfs_i2c_reset(bus);
return 0;
}
static void mpfs_i2c_transfer(struct mpfs_i2c_bus *bus, u32 data)
{
if (bus->msg_len > 0)
writel(data, bus->base + MPFS_I2C_DATA);
}
static void mpfs_i2c_empty_rx(struct mpfs_i2c_bus *bus)
{
u8 ctrl;
u8 data_read;
if (bus->msg_len > 0) {
data_read = readl(bus->base + MPFS_I2C_DATA);
*bus->buf++ = data_read;
bus->msg_len--;
}
if (bus->msg_len == 0) {
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl &= ~CTRL_AA;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
}
}
static int mpfs_i2c_fill_tx(struct mpfs_i2c_bus *bus)
{
mpfs_i2c_transfer(bus, *bus->buf++);
bus->msg_len--;
return 0;
}
static int mpfs_i2c_service_handler(struct mpfs_i2c_bus *bus)
{
bool finish = false;
u32 status;
u8 ctrl;
status = bus->isr_status;
switch (status) {
case STATUS_M_START_SENT:
case STATUS_M_REPEATED_START_SENT:
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl &= ~CTRL_STA;
writel(bus->addr, bus->base + MPFS_I2C_DATA);
writel(ctrl, bus->base + MPFS_I2C_CTRL);
break;
case STATUS_M_SLAW_ACK:
case STATUS_M_TX_DATA_ACK:
if (bus->msg_len > 0) {
mpfs_i2c_fill_tx(bus);
} else {
/* On the last byte to be transmitted, send STOP */
mpfs_i2c_stop(bus);
finish = true;
}
break;
case STATUS_M_SLAR_ACK:
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl |= CTRL_AA;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
if (bus->msg_len == 0) {
/* On the last byte to be transmitted, send STOP */
mpfs_i2c_stop(bus);
finish = true;
}
break;
case STATUS_M_RX_DATA_ACKED:
mpfs_i2c_empty_rx(bus);
if (bus->msg_len == 0) {
/* On the last byte to be transmitted, send STOP */
mpfs_i2c_stop(bus);
finish = true;
}
break;
case STATUS_M_TX_DATA_NACK:
case STATUS_M_RX_DATA_NACKED:
case STATUS_M_SLAR_NACK:
case STATUS_M_SLAW_NACK:
bus->msg_err = -ENXIO;
mpfs_i2c_stop(bus);
finish = true;
break;
case STATUS_M_ARB_LOST:
/* Handle Lost Arbitration */
bus->msg_err = -EAGAIN;
finish = true;
break;
default:
break;
}
if (finish) {
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl &= ~CTRL_AA;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
return 0;
}
return 1;
}
static int mpfs_i2c_service(struct mpfs_i2c_bus *bus)
{
int ret = 0;
int si_bit;
si_bit = readl(bus->base + MPFS_I2C_CTRL);
if (si_bit & CTRL_SI) {
bus->isr_status = readl(bus->base + MPFS_I2C_STATUS);
ret = mpfs_i2c_service_handler(bus);
}
/* Clear the si flag */
mpfs_i2c_int_clear(bus);
si_bit = readl(bus->base + MPFS_I2C_CTRL);
return ret;
}
static int mpfs_i2c_check_service_change(struct mpfs_i2c_bus *bus)
{
u8 ctrl;
u32 count = 0;
while (1) {
ctrl = readl(bus->base + MPFS_I2C_CTRL);
if (ctrl & CTRL_SI)
break;
udelay(1);
count += 1;
if (count == MICROCHIP_I2C_TIMEOUT)
return -ETIMEDOUT;
}
return 0;
}
static int mpfs_i2c_poll_device(struct mpfs_i2c_bus *bus)
{
int ret;
while (1) {
ret = mpfs_i2c_check_service_change(bus);
if (ret)
return ret;
ret = mpfs_i2c_service(bus);
if (!ret)
/* all messages have been transferred */
return ret;
}
}
static int mpfs_i2c_xfer_msg(struct mpfs_i2c_bus *bus, struct i2c_msg *msg)
{
u8 ctrl;
int ret;
if (!msg->len || !msg->buf)
return -EINVAL;
bus->addr = i2c_8bit_addr_from_msg(msg);
bus->msg_len = msg->len;
bus->buf = msg->buf;
bus->msg_err = 0;
mpfs_i2c_core_enable(bus);
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl |= CTRL_STA;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
ret = mpfs_i2c_poll_device(bus);
if (ret)
return ret;
return bus->msg_err;
}
static int mpfs_i2c_xfer(struct udevice *dev, struct i2c_msg *msgs, int num_msgs)
{
struct mpfs_i2c_bus *bus = dev_get_priv(dev);
int idx, ret;
if (!msgs || !num_msgs)
return -EINVAL;
for (idx = 0; idx < num_msgs; idx++) {
ret = mpfs_i2c_xfer_msg(bus, msgs++);
if (ret)
return ret;
}
return ret;
}
static int mpfs_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
{
struct mpfs_i2c_bus *bus = dev_get_priv(dev);
int ret;
u8 ctrl, reg = 0;
/*
* Send the chip address and verify that the
* address was <ACK>ed.
*/
bus->addr = addr << 1 | I2C_M_RD;
bus->buf = &reg;
bus->msg_len = 0;
bus->msg_err = 0;
mpfs_i2c_core_enable(bus);
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl |= CTRL_STA;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
ret = mpfs_i2c_poll_device(bus);
if (ret)
return ret;
return bus->msg_err;
}
static int mpfs_i2c_probe(struct udevice *dev)
{
int ret;
u32 val;
struct mpfs_i2c_bus *bus = dev_get_priv(dev);
bus->base = dev_read_addr_ptr(dev);
if (!bus->base)
return -EINVAL;
val = dev_read_u32(dev, "clock-frequency", &bus->clk_rate);
if (val) {
printf("Default to 100kHz\n");
/* default clock rate */
bus->clk_rate = 100000;
}
if (bus->clk_rate > 400000 || bus->clk_rate <= 0) {
printf("Invalid clock-frequency %d\n", bus->clk_rate);
return -EINVAL;
}
ret = mpfs_i2c_init(bus, dev);
return ret;
}
static const struct dm_i2c_ops mpfs_i2c_ops = {
.xfer = mpfs_i2c_xfer,
.probe_chip = mpfs_i2c_probe_chip,
};
static const struct udevice_id mpfs_i2c_ids[] = {
{.compatible = "microchip,mpfs-i2c"},
{}
};
U_BOOT_DRIVER(mpfs_i2c) = {
.name = "mpfs_i2c",
.id = UCLASS_I2C,
.of_match = mpfs_i2c_ids,
.ops = &mpfs_i2c_ops,
.probe = mpfs_i2c_probe,
.priv_auto = sizeof(struct mpfs_i2c_bus),
};

18
drivers/net/macb.c
View File

@@ -1348,7 +1348,7 @@ static const struct macb_usrio_cfg macb_default_usrio = {
.clken = MACB_BIT(CLKEN),
};
static const struct macb_config default_gem_config = {
static struct macb_config default_gem_config = {
.dma_burst_length = 16,
.hw_dma_cap = HW_DMA_CAP_32B,
.clk_init = NULL,
@@ -1383,8 +1383,13 @@ static int macb_eth_probe(struct udevice *dev)
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
macb->config = (struct macb_config *)dev_get_driver_data(dev);
if (!macb->config)
if (!macb->config) {
if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT)) {
if (GEM_BFEXT(DAW64, gem_readl(macb, DCFG6)))
default_gem_config.hw_dma_cap = HW_DMA_CAP_64B;
}
macb->config = &default_gem_config;
}
#ifdef CONFIG_CLK
ret = macb_enable_clk(dev);
@@ -1453,13 +1458,6 @@ static const struct macb_usrio_cfg sama7g5_usrio = {
.clken = BIT(2),
};
static const struct macb_config microchip_config = {
.dma_burst_length = 16,
.hw_dma_cap = HW_DMA_CAP_64B,
.clk_init = NULL,
.usrio = &macb_default_usrio,
};
static const struct macb_config sama5d4_config = {
.dma_burst_length = 4,
.hw_dma_cap = HW_DMA_CAP_32B,
@@ -1502,8 +1500,6 @@ static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "sifive,fu540-c000-gem",
.data = (ulong)&sifive_config },
{ .compatible = "microchip,mpfs-mss-gem",
.data = (ulong)&microchip_config },
{ }
};

13
include/configs/ax25-ae350.h
View File

@@ -119,12 +119,23 @@
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* Support autoboot from RAM (kernel image is loaded via debug port) */
#define KERNEL_IMAGE_ADDR "0x2000000 "
#define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \
"ram "
#define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \
"bootcmd_ram=" \
"booti " \
KERNEL_IMAGE_ADDR \
"- $fdtcontroladdr\0"
/* When we use RAM as ENV */
/* Enable distro boot */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
func(DHCP, dhcp, na) \
func(RAM, ram, na)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \

196
include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h Normal file
View File

@@ -0,0 +1,196 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/* Copyright (c) 2020-2021 Microchip Technology Inc */
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
#define PLIC_INT_INVALID 0
#define PLIC_INT_L2_METADATA_CORR 1
#define PLIC_INT_L2_METADATA_UNCORR 2
#define PLIC_INT_L2_DATA_CORR 3
#define PLIC_INT_L2_DATA_UNCORR 4
#define PLIC_INT_DMA_CH0_DONE 5
#define PLIC_INT_DMA_CH0_ERR 6
#define PLIC_INT_DMA_CH1_DONE 7
#define PLIC_INT_DMA_CH1_ERR 8
#define PLIC_INT_DMA_CH2_DONE 9
#define PLIC_INT_DMA_CH2_ERR 10
#define PLIC_INT_DMA_CH3_DONE 11
#define PLIC_INT_DMA_CH3_ERR 12
#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13
#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14
#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15
#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16
#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17
#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18
#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19
#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20
#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21
#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22
#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23
#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24
#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25
#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26
#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27
#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28
#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29
#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30
#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31
#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32
#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33
#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34
#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35
#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36
#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37
#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38
#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39
#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40
#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41
#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42
#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43
#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44
#define PLIC_INT_GPIO1_BIT18 45
#define PLIC_INT_GPIO1_BIT19 46
#define PLIC_INT_GPIO1_BIT20 47
#define PLIC_INT_GPIO1_BIT21 48
#define PLIC_INT_GPIO1_BIT22 49
#define PLIC_INT_GPIO1_BIT23 50
#define PLIC_INT_GPIO0_NON_DIRECT 51
#define PLIC_INT_GPIO1_NON_DIRECT 52
#define PLIC_INT_GPIO2_NON_DIRECT 53
#define PLIC_INT_SPI0 54
#define PLIC_INT_SPI1 55
#define PLIC_INT_CAN0 56
#define PLIC_INT_CAN1 57
#define PLIC_INT_I2C0_MAIN 58
#define PLIC_INT_I2C0_ALERT 59
#define PLIC_INT_I2C0_SUS 60
#define PLIC_INT_I2C1_MAIN 61
#define PLIC_INT_I2C1_ALERT 62
#define PLIC_INT_I2C1_SUS 63
#define PLIC_INT_MAC0_INT 64
#define PLIC_INT_MAC0_QUEUE1 65
#define PLIC_INT_MAC0_QUEUE2 66
#define PLIC_INT_MAC0_QUEUE3 67
#define PLIC_INT_MAC0_EMAC 68
#define PLIC_INT_MAC0_MMSL 69
#define PLIC_INT_MAC1_INT 70
#define PLIC_INT_MAC1_QUEUE1 71
#define PLIC_INT_MAC1_QUEUE2 72
#define PLIC_INT_MAC1_QUEUE3 73
#define PLIC_INT_MAC1_EMAC 74
#define PLIC_INT_MAC1_MMSL 75
#define PLIC_INT_DDRC_TRAIN 76
#define PLIC_INT_SCB_INTERRUPT 77
#define PLIC_INT_ECC_ERROR 78
#define PLIC_INT_ECC_CORRECT 79
#define PLIC_INT_RTC_WAKEUP 80
#define PLIC_INT_RTC_MATCH 81
#define PLIC_INT_TIMER1 82
#define PLIC_INT_TIMER2 83
#define PLIC_INT_ENVM 84
#define PLIC_INT_QSPI 85
#define PLIC_INT_USB_DMA 86
#define PLIC_INT_USB_MC 87
#define PLIC_INT_MMC_MAIN 88
#define PLIC_INT_MMC_WAKEUP 89
#define PLIC_INT_MMUART0 90
#define PLIC_INT_MMUART1 91
#define PLIC_INT_MMUART2 92
#define PLIC_INT_MMUART3 93
#define PLIC_INT_MMUART4 94
#define PLIC_INT_G5C_DEVRST 95
#define PLIC_INT_G5C_MESSAGE 96
#define PLIC_INT_USOC_VC_INTERRUPT 97
#define PLIC_INT_USOC_SMB_INTERRUPT 98
#define PLIC_INT_E51_0_MAINTENACE 99
#define PLIC_INT_WDOG0_MRVP 100
#define PLIC_INT_WDOG1_MRVP 101
#define PLIC_INT_WDOG2_MRVP 102
#define PLIC_INT_WDOG3_MRVP 103
#define PLIC_INT_WDOG4_MRVP 104
#define PLIC_INT_WDOG0_TOUT 105
#define PLIC_INT_WDOG1_TOUT 106
#define PLIC_INT_WDOG2_TOUT 107
#define PLIC_INT_WDOG3_TOUT 108
#define PLIC_INT_WDOG4_TOUT 109
#define PLIC_INT_G5C_MSS_SPI 110
#define PLIC_INT_VOLT_TEMP_ALARM 111
#define PLIC_INT_ATHENA_COMPLETE 112
#define PLIC_INT_ATHENA_ALARM 113
#define PLIC_INT_ATHENA_BUS_ERROR 114
#define PLIC_INT_USOC_AXIC_US 115
#define PLIC_INT_USOC_AXIC_DS 116
#define PLIC_INT_SPARE 117
#define PLIC_INT_FABRIC_F2H_0 118
#define PLIC_INT_FABRIC_F2H_1 119
#define PLIC_INT_FABRIC_F2H_2 120
#define PLIC_INT_FABRIC_F2H_3 121
#define PLIC_INT_FABRIC_F2H_4 122
#define PLIC_INT_FABRIC_F2H_5 123
#define PLIC_INT_FABRIC_F2H_6 124
#define PLIC_INT_FABRIC_F2H_7 125
#define PLIC_INT_FABRIC_F2H_8 126
#define PLIC_INT_FABRIC_F2H_9 127
#define PLIC_INT_FABRIC_F2H_10 128
#define PLIC_INT_FABRIC_F2H_11 129
#define PLIC_INT_FABRIC_F2H_12 130
#define PLIC_INT_FABRIC_F2H_13 131
#define PLIC_INT_FABRIC_F2H_14 132
#define PLIC_INT_FABRIC_F2H_15 133
#define PLIC_INT_FABRIC_F2H_16 134
#define PLIC_INT_FABRIC_F2H_17 135
#define PLIC_INT_FABRIC_F2H_18 136
#define PLIC_INT_FABRIC_F2H_19 137
#define PLIC_INT_FABRIC_F2H_20 138
#define PLIC_INT_FABRIC_F2H_21 139
#define PLIC_INT_FABRIC_F2H_22 140
#define PLIC_INT_FABRIC_F2H_23 141
#define PLIC_INT_FABRIC_F2H_24 142
#define PLIC_INT_FABRIC_F2H_25 143
#define PLIC_INT_FABRIC_F2H_26 144
#define PLIC_INT_FABRIC_F2H_27 145
#define PLIC_INT_FABRIC_F2H_28 146
#define PLIC_INT_FABRIC_F2H_29 147
#define PLIC_INT_FABRIC_F2H_30 148
#define PLIC_INT_FABRIC_F2H_31 149
#define PLIC_INT_FABRIC_F2H_32 150
#define PLIC_INT_FABRIC_F2H_33 151
#define PLIC_INT_FABRIC_F2H_34 152
#define PLIC_INT_FABRIC_F2H_35 153
#define PLIC_INT_FABRIC_F2H_36 154
#define PLIC_INT_FABRIC_F2H_37 155
#define PLIC_INT_FABRIC_F2H_38 156
#define PLIC_INT_FABRIC_F2H_39 157
#define PLIC_INT_FABRIC_F2H_40 158
#define PLIC_INT_FABRIC_F2H_41 159
#define PLIC_INT_FABRIC_F2H_42 160
#define PLIC_INT_FABRIC_F2H_43 161
#define PLIC_INT_FABRIC_F2H_44 162
#define PLIC_INT_FABRIC_F2H_45 163
#define PLIC_INT_FABRIC_F2H_46 164
#define PLIC_INT_FABRIC_F2H_47 165
#define PLIC_INT_FABRIC_F2H_48 166
#define PLIC_INT_FABRIC_F2H_49 167
#define PLIC_INT_FABRIC_F2H_50 168
#define PLIC_INT_FABRIC_F2H_51 169
#define PLIC_INT_FABRIC_F2H_52 170
#define PLIC_INT_FABRIC_F2H_53 171
#define PLIC_INT_FABRIC_F2H_54 172
#define PLIC_INT_FABRIC_F2H_55 173
#define PLIC_INT_FABRIC_F2H_56 174
#define PLIC_INT_FABRIC_F2H_57 175
#define PLIC_INT_FABRIC_F2H_58 176
#define PLIC_INT_FABRIC_F2H_59 177
#define PLIC_INT_FABRIC_F2H_60 178
#define PLIC_INT_FABRIC_F2H_61 179
#define PLIC_INT_FABRIC_F2H_62 180
#define PLIC_INT_FABRIC_F2H_63 181
#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182
#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183
#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184
#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185
#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186
#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */

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include/dt-bindings/interrupt-controller/riscv-hart.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/* Copyright (c) 2020-2021 Microchip Technology Inc */
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
#define HART_INT_U_SOFT 0
#define HART_INT_S_SOFT 1
#define HART_INT_M_SOFT 3
#define HART_INT_U_TIMER 4
#define HART_INT_S_TIMER 5
#define HART_INT_M_TIMER 7
#define HART_INT_U_EXT 8
#define HART_INT_S_EXT 9
#define HART_INT_M_EXT 11
#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */