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arm: mvebu: a38x: Adjust UTMI PHY parameters

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When running USB compliance tests on our Armada-385 hardware platforms
we have seen some eye mask violations. Marvell's internal documentation
says: Based on silicon test results, it is recommended to change the
impedance calibration threshold setting to 0x6 prior to calibration.

Port changes from Marvell's u-boot fork[1] to address this.

[1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
2020-06-25 12:48:51 +12:00
committed by Stefan Roese
parent ec9deec400
commit 4182232158
1 changed files with 21 additions and 4 deletions
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25
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
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@@ -672,12 +672,29 @@ struct op_params usb2_power_up_params[] = {
{0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
/* Phy0 register 3 - TX Channel control 0 */
{0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
/* check PLLCAL_DONE is set and IMPCAL_DONE is set */
/* Decrease the amplitude of the low speed eye to meet the spec */
{0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
{0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
{0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
/* Change the High speed impedance threshold */
{0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
{0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
{0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
/* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */
{0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
{0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
{0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
/* Check PLLCAL_DONE is set and IMPCAL_DONE is set */
{0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000},
/* check REG_SQCAL_DONE is set */
/* Check REG_SQCAL_DONE is set */
{0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
/* check PLL_READY is set */
{0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}
/* Check PLL_READY is set */
{0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
/* Start calibrate of high seed impedance */
{0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0},
{0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0},
/* De-assert the calibration signal */
{0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0},
};
/*