ppc: Remove MPC8572DS board
This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI. The deadline for this conversion was the v2019.07 release. The use of CONFIG_AHCI requires CONFIG_DM. The deadline for this conversion was v2020.01. Remove this board. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Tom Rini
@@ -68,14 +68,6 @@ config TARGET_MPC8569MDS
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bool "Support MPC8569MDS"
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select ARCH_MPC8569
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config TARGET_MPC8572DS
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bool "Support MPC8572DS"
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select ARCH_MPC8572
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# Use DDR3 controller with DDR2 DIMMs on this board
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select SYS_FSL_DDRC_GEN3
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imply SCSI
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imply PANIC_HANG
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config TARGET_P1010RDB_PA
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bool "Support P1010RDB_PA"
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select ARCH_P1010
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@@ -1442,7 +1434,6 @@ source "board/freescale/mpc8548cds/Kconfig"
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source "board/freescale/mpc8555cds/Kconfig"
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source "board/freescale/mpc8568mds/Kconfig"
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source "board/freescale/mpc8569mds/Kconfig"
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source "board/freescale/mpc8572ds/Kconfig"
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source "board/freescale/p1010rdb/Kconfig"
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source "board/freescale/p1_p2_rdb_pc/Kconfig"
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source "board/freescale/p2041rdb/Kconfig"
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@@ -48,7 +48,6 @@ obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
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obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
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obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
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obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o
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obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
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obj-$(CONFIG_P2020DS) += ics307_clk.o
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obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
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@@ -45,35 +45,6 @@ typedef struct pixis {
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u8 res2[4];
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} __attribute__ ((packed)) pixis_t;
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#elif defined(CONFIG_TARGET_MPC8572DS)
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typedef struct pixis {
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u8 id;
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u8 ver;
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u8 pver;
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u8 csr;
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u8 rst;
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u8 pwr1;
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u8 aux1;
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u8 spd;
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u8 aux2;
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u8 res[7];
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u8 vctl;
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u8 vstat;
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u8 vcfgen0;
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u8 vcfgen1;
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u8 vcore0;
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u8 res1;
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u8 vboot;
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u8 vspeed[3];
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u8 res2[2];
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u8 sclk[3];
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u8 dclk[3];
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u8 res3[2];
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u8 watch;
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u8 led;
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u8 res4[25];
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} __attribute__ ((packed)) pixis_t;
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#elif defined(CONFIG_TARGET_MPC8610HPCD)
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typedef struct pixis {
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u8 id;
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@@ -1,12 +0,0 @@
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if TARGET_MPC8572DS
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config SYS_BOARD
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default "mpc8572ds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC8572DS"
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endif
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@@ -1,7 +0,0 @@
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MPC8572DS BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: board/freescale/mpc8572ds/
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F: include/configs/MPC8572DS.h
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F: configs/MPC8572DS_defconfig
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F: configs/MPC8572DS_36BIT_defconfig
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@@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2007 Freescale Semiconductor, Inc.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc8572ds.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@@ -1,166 +0,0 @@
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Overview
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--------
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MPC8572DS is a high-performance computing, evaluation and development platform
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supporting the mpc8572 PowerTM processor.
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Building U-Boot
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-----------
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make MPC8572DS_config
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make
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Flash Banks
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-----------
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MPC8572DS board has two flash banks. They are both present on boot, but their
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locations can be swapped using the dip-switch SW9[1:2].
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Booting is always from the boot bank at 0xec00_0000.
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Memory Map
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----------
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0xe800_0000 - 0xebff_ffff Alternate bank 64MB
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0xec00_0000 - 0xefff_ffff Boot bank 64MB
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0xebf8_0000 - 0xebff_ffff Alternate U-Boot address 512KB
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0xeff8_0000 - 0xefff_ffff Boot U-Boot address 512KB
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Flashing Images
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---------------
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To place a new U-Boot image in the alternate flash bank and then reset with that
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new image temporarily, use this:
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tftp 1000000 u-boot.bin
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erase ebf80000 ebffffff
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cp.b 1000000 ebf80000 80000
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pixis_reset altbank
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To program the image in the boot flash bank:
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tftp 1000000 u-boot.bin
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protect off all
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erase eff80000 ffffffff
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cp.b 1000000 eff80000 80000
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The pixis_reset command
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-----------------------
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The command - "pixis_reset", is introduced to reset mpc8572ds board
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using the FPGA sequencer. When the board restarts, it has the option
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of using either the current or alternate flash bank as the boot
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image, with or without the watchdog timer enabled, and finally with
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or without frequency changes.
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Usage is;
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pixis_reset
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pixis_reset altbank
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pixis_reset altbank wd
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pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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Examples:
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/* reset to current bank, like "reset" command */
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pixis_reset
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/* reset board but use the to alternate flash bank */
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pixis_reset altbank
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Using the Device Tree Source File
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---------------------------------
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To create the DTB (Device Tree Binary) image file,
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use a command similar to this:
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dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
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Likely, that .dts file will come from here;
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linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
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Booting Linux
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-------------
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage.8572
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tftp c00000 mpc8572ds.dtb
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bootm 1000000 - c00000
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Implementing AMP(Asymmetric MultiProcessing)
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-------------
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1. Build kernel image for core0:
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a. $ make 85xx/mpc8572_ds_defconfig
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b. $ make menuconfig
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- un-select "Processor support"->"Symetric multi-processing support"
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c. $ make uImage
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d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
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2. Build kernel image for core1:
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a. $ make 85xx/mpc8572_ds_defconfig
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b. $ make menuconfig
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- Un-select "Processor support"->"Symetric multi-processing support"
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- Select "Advanced setup" -> " Prompt for advanced kernel
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configuration options"
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- Select "Set physical address where the kernel is loaded" and
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set it to 0x20000000, assuming core1 will start from 512MB.
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- Select "Set custom page offset address"
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- Select "Set custom kernel base address"
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- Select "Set maximum low memory"
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- "Exit" and save the selection.
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c. $ make uImage
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d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
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3. Create dtb for core0:
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$ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
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4. Create dtb for core1:
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$ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
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5. Bring up two cores separately:
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a. Power on the board, under U-Boot prompt:
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=> setenv <serverip>
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=> setenv <ipaddr>
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=> setenv bootargs root=/dev/ram rw console=ttyS0,115200
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b. Bring up core1's kernel first:
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=> setenv bootm_low 0x20000000
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=> setenv bootm_size 0x10000000
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=> tftp 21000000 8572/uImage.core1
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=> tftp 22000000 8572/ramdiskfile
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=> tftp 20c00000 8572/mpc8572ds_core1.dtb
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=> interrupts off
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=> bootm start 21000000 22000000 20c00000
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=> bootm loados
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=> bootm ramdisk
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=> bootm fdt
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=> fdt boardsetup
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=> fdt chosen $initrd_start $initrd_end
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=> bootm prep
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=> cpu 1 release $bootm_low - $fdtaddr -
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c. Bring up core0's kernel(on the same U-Boot console):
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=> setenv bootm_low 0
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=> setenv bootm_size 0x20000000
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=> tftp 1000000 8572/uImage.core0
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=> tftp 2000000 8572/ramdiskfile
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=> tftp c00000 8572/mpc8572ds_core0.dtb
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=> bootm 1000000 2000000 c00000
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Please note only core0 will run U-Boot, core1 starts kernel directly after
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"cpu release" command is issued.
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@@ -1,166 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*
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* For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
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* tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
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* all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
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* For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
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* from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
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*
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* CPO value doesn't matter if workaround for errata 111 and 134 enabled.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 8, 7, 5, 0},
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{2, 400, 8, 9, 5, 0},
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{2, 549, 8, 11, 5, 0},
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{2, 680, 8, 10, 5, 0},
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{2, 850, 8, 12, 5, 1},
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{1, 333, 6, 7, 3, 0},
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{1, 400, 6, 9, 3, 0},
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{1, 549, 6, 11, 3, 0},
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{1, 680, 1, 10, 5, 0},
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{1, 850, 1, 12, 5, 0},
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{}
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};
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static const struct board_specific_parameters udimm1[] = {
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/*
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* memory controller 1
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 8, 7, 5, 0},
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{2, 400, 8, 9, 5, 0},
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{2, 549, 8, 11, 5, 0},
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{2, 680, 8, 11, 5, 0},
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{2, 850, 8, 13, 5, 1},
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{1, 333, 6, 7, 3, 0},
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{1, 400, 6, 9, 3, 0},
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{1, 549, 6, 11, 3, 0},
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{1, 680, 1, 11, 6, 0},
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{1, 850, 1, 13, 6, 0},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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udimm1,
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};
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static const struct board_specific_parameters rdimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 4, 7, 3, 0},
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{2, 400, 4, 9, 3, 0},
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{2, 549, 4, 11, 3, 0},
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{2, 680, 4, 10, 3, 0},
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{2, 850, 4, 12, 3, 1},
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{}
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};
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static const struct board_specific_parameters rdimm1[] = {
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/*
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* memory controller 1
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 4, 7, 3, 0},
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{2, 400, 4, 9, 3, 0},
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{2, 549, 4, 11, 3, 0},
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{2, 680, 4, 11, 3, 0},
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{2, 850, 4, 13, 3, 1},
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{}
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};
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static const struct board_specific_parameters *rdimms[] = {
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rdimm0,
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rdimm1,
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 1) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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if (popts->registered_dimm_en)
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pbsp = rdimms[ctrl_num];
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else
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pbsp = udimms[ctrl_num];
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->twot_en = pbsp->force_2t;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found "
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"for data rate %lu MT/s!\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->twot_en = pbsp->force_2t;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
|
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*/
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||||
popts->half_strength_driver_enable = 0;
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}
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@@ -1,19 +0,0 @@
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||||
// SPDX-License-Identifier: GPL-2.0+
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/*
|
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* Copyright 2008, 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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};
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||||
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int num_law_entries = ARRAY_SIZE(law_table);
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||||
@@ -1,260 +0,0 @@
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||||
// SPDX-License-Identifier: GPL-2.0+
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||||
/*
|
||||
* Copyright 2007-2011 Freescale Semiconductor, Inc.
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||||
*/
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||||
|
||||
#include <common.h>
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||||
#include <command.h>
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||||
#include <env.h>
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||||
#include <image.h>
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||||
#include <init.h>
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||||
#include <log.h>
|
||||
#include <net.h>
|
||||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <miiphy.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <tsec.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#include "../common/sgmii_riser.h"
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
u8 vboot;
|
||||
u8 *pixis_base = (u8 *)PIXIS_BASE;
|
||||
|
||||
printf("Board: MPC8572DS Sys ID: 0x%02x, "
|
||||
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
|
||||
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
|
||||
in_8(pixis_base + PIXIS_PVER));
|
||||
|
||||
vboot = in_8(pixis_base + PIXIS_VBOOT);
|
||||
switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
|
||||
case PIXIS_VBOOT_LBMAP_NOR0:
|
||||
puts ("vBank: 0\n");
|
||||
break;
|
||||
case PIXIS_VBOOT_LBMAP_PJET:
|
||||
puts ("Promjet\n");
|
||||
break;
|
||||
case PIXIS_VBOOT_LBMAP_NAND:
|
||||
puts ("NAND\n");
|
||||
break;
|
||||
case PIXIS_VBOOT_LBMAP_NOR1:
|
||||
puts ("vBank: 1\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* Fixed sdram init -- doesn't use serial presence detect.
|
||||
*/
|
||||
|
||||
phys_size_t fixed_sdram (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
|
||||
uint d_init;
|
||||
|
||||
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
|
||||
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
|
||||
|
||||
ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
|
||||
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
|
||||
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
|
||||
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
|
||||
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
|
||||
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
|
||||
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
|
||||
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
|
||||
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
|
||||
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
|
||||
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
|
||||
ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
|
||||
ddr->err_sbe = CONFIG_SYS_DDR_SBE;
|
||||
#endif
|
||||
asm("sync;isync");
|
||||
|
||||
udelay(500);
|
||||
|
||||
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
|
||||
|
||||
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
d_init = 1;
|
||||
debug("DDR - 1st controller: memory initializing\n");
|
||||
/*
|
||||
* Poll until memory is initialized.
|
||||
* 512 Meg at 400 might hit this 200 times or so.
|
||||
*/
|
||||
while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
|
||||
udelay(1000);
|
||||
}
|
||||
debug("DDR: memory initialized\n\n");
|
||||
asm("sync; isync");
|
||||
udelay(500);
|
||||
#endif
|
||||
|
||||
return 512 * 1024 * 1024;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void pci_init_board(void)
|
||||
{
|
||||
struct pci_controller *hose;
|
||||
|
||||
fsl_pcie_init_board(0);
|
||||
|
||||
hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
|
||||
|
||||
if (hose) {
|
||||
u32 temp32;
|
||||
u8 uli_busno = hose->first_busno + 2;
|
||||
|
||||
/*
|
||||
* Activate ULI1575 legacy chip by performing a fake
|
||||
* memory access. Needed to make ULI RTC work.
|
||||
* Device 1d has the first on-board memory BAR.
|
||||
*/
|
||||
pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
|
||||
PCI_BASE_ADDRESS_1, &temp32);
|
||||
|
||||
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
|
||||
void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
|
||||
temp32, 4, 0);
|
||||
debug(" uli1572 read to %p\n", p);
|
||||
in_be32(p);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
int flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
if (flash_esel == -1) {
|
||||
/* very unlikely unless something is messed up */
|
||||
puts("Error: Could not find TLB for FLASH BASE\n");
|
||||
flash_esel = 2; /* give our best effort to continue */
|
||||
} else {
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
}
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
struct fsl_pq_mdio_info mdio_info;
|
||||
struct tsec_info_struct tsec_info[4];
|
||||
int num = 0;
|
||||
|
||||
#ifdef CONFIG_TSEC1
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
||||
if (is_serdes_configured(SGMII_TSEC1)) {
|
||||
puts("eTSEC1 is in sgmii mode.\n");
|
||||
tsec_info[num].flags |= TSEC_SGMII;
|
||||
}
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC2
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 2);
|
||||
if (is_serdes_configured(SGMII_TSEC2)) {
|
||||
puts("eTSEC2 is in sgmii mode.\n");
|
||||
tsec_info[num].flags |= TSEC_SGMII;
|
||||
}
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC3
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 3);
|
||||
if (is_serdes_configured(SGMII_TSEC3)) {
|
||||
puts("eTSEC3 is in sgmii mode.\n");
|
||||
tsec_info[num].flags |= TSEC_SGMII;
|
||||
}
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC4
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 4);
|
||||
if (is_serdes_configured(SGMII_TSEC4)) {
|
||||
puts("eTSEC4 is in sgmii mode.\n");
|
||||
tsec_info[num].flags |= TSEC_SGMII;
|
||||
}
|
||||
num++;
|
||||
#endif
|
||||
|
||||
if (!num) {
|
||||
printf("No TSECs initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
fsl_sgmii_riser_init(tsec_info, num);
|
||||
#endif
|
||||
|
||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
|
||||
mdio_info.name = DEFAULT_MII_NAME;
|
||||
fsl_pq_mdio_init(bis, &mdio_info);
|
||||
|
||||
tsec_eth_init(bis, tsec_info, num);
|
||||
#endif
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = env_get_bootm_low();
|
||||
size = env_get_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
FT_FSL_PCI_SETUP;
|
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
fsl_sgmii_riser_fdt_fixup(blob);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -1,87 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
/* W**G* - Flash/promjet, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
|
||||
/* *I*G - NAND */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 8, BOOKE_PAGESZ_4K, 1),
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
|
||||
/* *I*G - L2SRAM */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
|
||||
CONFIG_SYS_INIT_L2_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 9, BOOKE_PAGESZ_256K, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
|
||||
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@@ -1,56 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_MPC8572DS=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_REGINFO=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_MP=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_PCI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_ADDR_MAP=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@@ -1,54 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_MPC8572DS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_REGINFO=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_MP=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_PCI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@@ -1,600 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* mpc8572ds board configuration file
|
||||
*
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#include "../board/freescale/common/ics307_clk.h"
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
|
||||
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
|
||||
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
|
||||
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
/*
|
||||
* Config the L2 Cache as L2 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#endif
|
||||
#define CONFIG_SYS_L2_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#endif
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#define CONFIG_DDR_SPD
|
||||
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||
|
||||
/* I2C addresses of SPD EEPROMs */
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
|
||||
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
|
||||
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
|
||||
|
||||
/* These are used when DDR doesn't use SPD. */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00020000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
|
||||
#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
|
||||
#define CONFIG_SYS_DDR_MODE_1 0x00440462
|
||||
#define CONFIG_SYS_DDR_MODE_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
|
||||
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
|
||||
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
|
||||
#define CONFIG_SYS_DDR_CONTROL2 0x24400000
|
||||
|
||||
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
|
||||
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
|
||||
#define CONFIG_SYS_DDR_SBE 0x00010000
|
||||
|
||||
/*
|
||||
* Make sure required options are set
|
||||
*/
|
||||
#ifndef CONFIG_SPD_EEPROM
|
||||
#error ("CONFIG_SPD_EEPROM is required")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
||||
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
|
||||
* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
|
||||
* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
|
||||
*
|
||||
* Localbus cacheable (TBD)
|
||||
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
|
||||
*
|
||||
* Localbus non-cacheable
|
||||
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
|
||||
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
|
||||
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
|
||||
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
|
||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
|
||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
||||
*/
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_FLASH_BR_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
|
||||
|
||||
#define CONFIG_HWCONFIG /* enable hwconfig */
|
||||
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
|
||||
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define PIXIS_BASE_PHYS 0xfffdf0000ull
|
||||
#else
|
||||
#define PIXIS_BASE_PHYS PIXIS_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
||||
|
||||
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
|
||||
#define PIXIS_VER 0x1 /* Board version at offset 1 */
|
||||
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
|
||||
#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
|
||||
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
|
||||
#define PIXIS_PWR 0x5 /* PIXIS Power status register */
|
||||
#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
|
||||
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
|
||||
#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
|
||||
#define PIXIS_VCTL 0x10 /* VELA Control Register */
|
||||
#define PIXIS_VSTAT 0x11 /* VELA Status Register */
|
||||
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
|
||||
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
|
||||
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
|
||||
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
|
||||
#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
|
||||
#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
|
||||
#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
|
||||
#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
|
||||
#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
|
||||
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
|
||||
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
|
||||
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
|
||||
#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
|
||||
#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
|
||||
#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
|
||||
#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
|
||||
#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
|
||||
#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
|
||||
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
|
||||
#define PIXIS_LED 0x25 /* LED Register */
|
||||
|
||||
#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
|
||||
|
||||
/* old pixis referenced names */
|
||||
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
|
||||
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
|
||||
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
|
||||
#define PIXIS_VSPEED2_TSEC1SER 0x8
|
||||
#define PIXIS_VSPEED2_TSEC2SER 0x4
|
||||
#define PIXIS_VSPEED2_TSEC3SER 0x2
|
||||
#define PIXIS_VSPEED2_TSEC4SER 0x1
|
||||
#define PIXIS_VCFGEN1_TSEC1SER 0x20
|
||||
#define PIXIS_VCFGEN1_TSEC2SER 0x20
|
||||
#define PIXIS_VCFGEN1_TSEC3SER 0x20
|
||||
#define PIXIS_VCFGEN1_TSEC4SER 0x20
|
||||
#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
|
||||
| PIXIS_VSPEED2_TSEC2SER \
|
||||
| PIXIS_VSPEED2_TSEC3SER \
|
||||
| PIXIS_VSPEED2_TSEC4SER)
|
||||
#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
|
||||
| PIXIS_VCFGEN1_TSEC2SER \
|
||||
| PIXIS_VCFGEN1_TSEC3SER \
|
||||
| PIXIS_VCFGEN1_TSEC4SER)
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE 0xfff00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
|
||||
CONFIG_SYS_NAND_BASE + 0x40000, \
|
||||
CONFIG_SYS_NAND_BASE + 0x80000,\
|
||||
CONFIG_SYS_NAND_BASE + 0xC0000}
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 4
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 5
|
||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
|
||||
|
||||
/* NAND boot: 4K NAND loader config */
|
||||
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START \
|
||||
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
|
||||
|
||||
/* NAND flash config */
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_NS16550_MIN_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
*/
|
||||
#define CONFIG_ID_EEPROM
|
||||
#ifdef CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 1
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
|
||||
#define CONFIG_SYS_PCIE3_NAME "ULI"
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
|
||||
#define CONFIG_SYS_PCIE2_NAME "Slot 1"
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 1, Slot 1, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_NAME "Slot 2"
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
/*PCIE video card used*/
|
||||
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
|
||||
|
||||
/* video */
|
||||
|
||||
#if defined(CONFIG_VIDEO)
|
||||
#define CONFIG_BIOSEMU
|
||||
#define CONFIG_ATI_RADEON_FB
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
|
||||
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
|
||||
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
#ifdef CONFIG_SCSI_AHCI
|
||||
#define CONFIG_SATA_ULI5288
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
|
||||
#endif /* SCSI */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
#define CONFIG_TSEC3 1
|
||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
||||
#define CONFIG_TSEC4 1
|
||||
#define CONFIG_TSEC4_NAME "eTSEC4"
|
||||
|
||||
#define CONFIG_PIXIS_SGMII_CMD
|
||||
#define CONFIG_FSL_SGMII_RISER 1
|
||||
#define SGMII_RISER_PHY_OFFSET 0x1c
|
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
|
||||
#endif
|
||||
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC3_PHY_ADDR 2
|
||||
#define TSEC4_PHY_ADDR 3
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC3_PHYIDX 0
|
||||
#define TSEC4_PHYIDX 0
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_PCI_EHCI_DEVICE 0
|
||||
#endif
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPADDR 192.168.1.254
|
||||
|
||||
#define CONFIG_HOSTNAME "unknown"
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=8572ds/ramdisk.uboot\0" \
|
||||
"fdtaddr=1e00000\0" \
|
||||
"fdtfile=8572ds/mpc8572ds.dtb\0" \
|
||||
"bdev=sda3\0"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Reference in New Issue
Block a user