dm: ppc: p1010: add i2c DM support
This supports i2c DM for SoC P1010 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Biwen Li
Priyanka Jain
@@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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*/
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#include <common.h>
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@@ -136,6 +137,125 @@ int config_board_mux(int ctrl_type)
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u8 tmp;
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#ifdef CONFIG_DM_I2C
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struct udevice *dev;
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int ret;
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#if defined(CONFIG_TARGET_P1010RDB_PA)
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
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I2C_PCA9557_ADDR1, 1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n",
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__func__, I2C_PCA9557_BUS_NUM);
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return ret;
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}
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switch (ctrl_type) {
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case MUX_TYPE_IFC:
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tmp = 0xf0;
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dm_i2c_write(dev, 3, &tmp, 1);
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tmp = 0x01;
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dm_i2c_write(dev, 1, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_IFC;
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clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
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break;
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case MUX_TYPE_SDHC:
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tmp = 0xf0;
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dm_i2c_write(dev, 3, &tmp, 1);
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tmp = 0x05;
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dm_i2c_write(dev, 1, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_SDHC;
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clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
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PMUXCR1_SDHC_ENABLE);
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break;
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case MUX_TYPE_SPIFLASH:
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out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
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break;
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case MUX_TYPE_TDM:
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out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
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out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
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break;
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case MUX_TYPE_CAN:
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out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
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break;
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default:
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break;
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}
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#elif defined(CONFIG_TARGET_P1010RDB_PB)
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ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
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I2C_PCA9557_ADDR2, 1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n",
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__func__, I2C_PCA9557_BUS_NUM);
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return ret;
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}
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switch (ctrl_type) {
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case MUX_TYPE_IFC:
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dm_i2c_read(dev, 0, &tmp, 1);
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clrbits_8(&tmp, 0x04);
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dm_i2c_write(dev, 1, &tmp, 1);
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dm_i2c_read(dev, 3, &tmp, 1);
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clrbits_8(&tmp, 0x04);
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dm_i2c_write(dev, 3, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_IFC;
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clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
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break;
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case MUX_TYPE_SDHC:
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dm_i2c_read(dev, 0, &tmp, 1);
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setbits_8(&tmp, 0x04);
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dm_i2c_write(dev, 1, &tmp, 1);
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dm_i2c_read(dev, 3, &tmp, 1);
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clrbits_8(&tmp, 0x04);
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dm_i2c_write(dev, 3, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_SDHC;
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clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
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PMUXCR1_SDHC_ENABLE);
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break;
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case MUX_TYPE_SPIFLASH:
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dm_i2c_read(dev, 0, &tmp, 1);
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clrbits_8(&tmp, 0x80);
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dm_i2c_write(dev, 1, &tmp, 1);
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dm_i2c_read(dev, 3, &tmp, 1);
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clrbits_8(&tmp, 0x80);
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dm_i2c_write(dev, 3, &tmp, 1);
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break;
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case MUX_TYPE_TDM:
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dm_i2c_read(dev, 0, &tmp, 1);
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setbits_8(&tmp, 0x82);
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dm_i2c_write(dev, 1, &tmp, 1);
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dm_i2c_read(dev, 3, &tmp, 1);
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clrbits_8(&tmp, 0x82);
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dm_i2c_write(dev, 3, &tmp, 1);
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break;
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case MUX_TYPE_CAN:
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dm_i2c_read(dev, 0, &tmp, 1);
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clrbits_8(&tmp, 0x02);
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dm_i2c_write(dev, 1, &tmp, 1);
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dm_i2c_read(dev, 3, &tmp, 1);
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clrbits_8(&tmp, 0x02);
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dm_i2c_write(dev, 3, &tmp, 1);
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break;
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case MUX_TYPE_CS0_NOR:
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dm_i2c_read(dev, 0, &tmp, 1);
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clrbits_8(&tmp, 0x08);
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dm_i2c_write(dev, 1, &tmp, 1);
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dm_i2c_read(dev, 3, &tmp, 1);
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clrbits_8(&tmp, 0x08);
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dm_i2c_write(dev, 3, &tmp, 1);
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break;
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case MUX_TYPE_CS0_NAND:
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dm_i2c_read(dev, 0, &tmp, 1);
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setbits_8(&tmp, 0x08);
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dm_i2c_write(dev, 1, &tmp, 1);
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dm_i2c_read(dev, 3, &tmp, 1);
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clrbits_8(&tmp, 0x08);
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dm_i2c_write(dev, 3, &tmp, 1);
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break;
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default:
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break;
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}
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#endif
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#else
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#if defined(CONFIG_TARGET_P1010RDB_PA)
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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@@ -242,6 +362,7 @@ int config_board_mux(int ctrl_type)
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break;
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}
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i2c_set_bus_num(orig_bus);
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#endif
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#endif
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return 0;
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}
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@@ -250,9 +371,23 @@ int config_board_mux(int ctrl_type)
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int i2c_pca9557_read(int type)
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{
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u8 val;
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int bus_num = I2C_PCA9557_BUS_NUM;
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i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
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#ifdef CONFIG_DM_I2C
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struct udevice *dev;
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int ret;
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ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n",
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__func__, bus_num);
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return ret;
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}
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dm_i2c_read(dev, 0, &val, 1);
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#else
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i2c_set_bus_num(bus_num);
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
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#endif
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switch (type) {
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case I2C_READ_BANK:
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@@ -280,11 +415,26 @@ int checkboard(void)
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printf("Board: %sRDB-PA, ", cpu->name);
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#elif defined(CONFIG_TARGET_P1010RDB_PB)
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printf("Board: %sRDB-PB, ", cpu->name);
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#ifdef CONFIG_DM_I2C
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struct udevice *dev;
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int ret;
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ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
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1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n", __func__,
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I2C_PCA9557_BUS_NUM);
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return ret;
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}
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val = 0x0; /* no polarity inversion */
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dm_i2c_write(dev, 2, &val, 1);
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#else
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i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
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i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
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val = 0x0; /* no polarity inversion */
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i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
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#endif
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#endif
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#ifdef CONFIG_SDCARD
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/* switch to IFC to read info from CPLD */
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@@ -308,7 +458,11 @@ int checkboard(void)
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case 0xe:
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puts("SDHC\n");
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val = 0x60; /* set pca9557 pin input/output */
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#ifdef CONFIG_DM_I2C
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dm_i2c_write(dev, 3, &val, 1);
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#else
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
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#endif
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break;
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case 0x5:
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config_board_mux(MUX_TYPE_IFC);
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@@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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*/
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/*
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@@ -522,17 +523,22 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* I2C */
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#ifndef CONFIG_DM_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#else
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define I2C_PCA9557_ADDR1 0x18
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#define I2C_PCA9557_ADDR2 0x19
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#define I2C_PCA9557_BUS_NUM 0
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#define CONFIG_SYS_I2C_FSL
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/* I2C EEPROM */
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#if defined(CONFIG_TARGET_P1010RDB_PB)
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