eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

clk: sunxi: Add drivers for A31 and H6 PRCM CCUs

Browse Source 
Add a driver so the clocks/resets for these peripherals (especially I2C,
RSB, and UART) can be enabled using the normal uclass methods.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Samuel Holland
2021-09-12 09:47:25 -05:00
committed by Andre Przywara
parent c61897bf02
commit 23c83366f3
4 changed files with 136 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/clk/sunxi/Kconfig
View File

@@ -30,6 +30,13 @@ config CLK_SUN6I_A31
This enables common clock driver support for platforms based
on Allwinner A31/A31s SoC.
config CLK_SUN6I_A31_R
bool "Clock driver for Allwinner A31 generation PRCM"
default SUNXI_GEN_SUN6I
help
This enables common clock driver support for the PRCM
in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
config CLK_SUN8I_A23
bool "Clock driver for Allwinner A23/A33"
default MACH_SUN8I_A23 || MACH_SUN8I_A33
@@ -79,6 +86,13 @@ config CLK_SUN50I_H6
This enables common clock driver support for platforms based
on Allwinner H6 SoC.
config CLK_SUN50I_H6_R
bool "Clock driver for Allwinner H6 generation PRCM"
default SUN50I_GEN_H6
help
This enables common clock driver support for the PRCM
in Allwinner H6/H616 SoCs.
config CLK_SUN50I_H616
bool "Clock driver for Allwinner H616"
default MACH_SUN50I_H616

2
drivers/clk/sunxi/Makefile
View File

@@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
@@ -18,5 +19,6 @@ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

59
drivers/clk/sunxi/clk_a31_r.c Normal file
View File

@@ -0,0 +1,59 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) Samuel Holland <samuel@sholland.org>
*/
#include <clk-uclass.h>
#include <dm.h>
#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
#include <linux/bitops.h>
static struct ccu_clk_gate a31_r_gates[] = {
[CLK_APB0_PIO] = GATE(0x028, BIT(0)),
[CLK_APB0_IR] = GATE(0x028, BIT(1)),
[CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
[CLK_APB0_RSB] = GATE(0x028, BIT(3)),
[CLK_APB0_UART] = GATE(0x028, BIT(4)),
[CLK_APB0_I2C] = GATE(0x028, BIT(6)),
[CLK_APB0_TWD] = GATE(0x028, BIT(7)),
};
static struct ccu_reset a31_r_resets[] = {
[RST_APB0_IR] = RESET(0x0b0, BIT(1)),
[RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
[RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
[RST_APB0_UART] = RESET(0x0b0, BIT(4)),
[RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
};
static const struct ccu_desc a31_r_ccu_desc = {
.gates = a31_r_gates,
.resets = a31_r_resets,
};
static int a31_r_clk_bind(struct udevice *dev)
{
return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
}
static const struct udevice_id a31_r_clk_ids[] = {
{ .compatible = "allwinner,sun8i-a83t-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
{ .compatible = "allwinner,sun8i-h3-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
{ .compatible = "allwinner,sun50i-a64-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun6i_a31_r) = {
.name = "sun6i_a31_r_ccu",
.id = UCLASS_CLK,
.of_match = a31_r_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a31_r_clk_bind,
};

61
drivers/clk/sunxi/clk_h6_r.c Normal file
View File

@@ -0,0 +1,61 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) Samuel Holland <samuel@sholland.org>
*/
#include <clk-uclass.h>
#include <dm.h>
#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
#include <linux/bitops.h>
static struct ccu_clk_gate h6_r_gates[] = {
[CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
[CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
[CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
[CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
[CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
[CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
[CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
[CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
};
static struct ccu_reset h6_r_resets[] = {
[RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)),
[RST_R_APB1_TWD] = RESET(0x12c, BIT(16)),
[RST_R_APB1_PWM] = RESET(0x13c, BIT(16)),
[RST_R_APB2_UART] = RESET(0x18c, BIT(16)),
[RST_R_APB2_I2C] = RESET(0x19c, BIT(16)),
[RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)),
[RST_R_APB1_IR] = RESET(0x1cc, BIT(16)),
[RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
};
static const struct ccu_desc h6_r_ccu_desc = {
.gates = h6_r_gates,
.resets = h6_r_resets,
};
static int h6_r_clk_bind(struct udevice *dev)
{
return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
}
static const struct udevice_id h6_r_clk_ids[] = {
{ .compatible = "allwinner,sun50i-h6-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
{ .compatible = "allwinner,sun50i-h616-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun6i_h6_r) = {
.name = "sun6i_h6_r_ccu",
.id = UCLASS_CLK,
.of_match = h6_r_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = h6_r_clk_bind,
};