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rockchip: px30: sync serial flash controller bindings with mainline

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The devicetree submitted and approved for the mainline linux kernel is
slightly different than the one present here. This syncs both
devicetrees (for the Rockchip SFC node at least) present on the PX30
and the Odroid Go Advance. Changes include renaming the flash node,
reordering the values in the SFC node for the rk3326-odroid-go2,
changing the name of the cs pinctrl node to cs0, and updating the
u-boot specific tree to utilize the new flash node value.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Chris Morgan
2021-08-20 20:46:58 -05:00
committed by Kever Yang
parent 3ad88ecc6b
commit 193ab22797
3 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/px30.dtsi
View File

@@ -967,7 +967,7 @@
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
pinctrl-names = "default";
pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
@@ -1953,7 +1953,7 @@
<1 RK_PA1 3 &pcfg_pull_none>;
};
sfc_cs: sfc-cs {
sfc_cs0: sfc-cs0 {
rockchip,pins =
<1 RK_PA4 3 &pcfg_pull_none>;
};

2
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
View File

@@ -80,7 +80,7 @@
u-boot,dm-pre-reloc;
};
&spi_flash {
&{/sfc@ff3a0000/flash@0} {
u-boot,dm-pre-reloc;
};

8
arch/arm/dts/rk3326-odroid-go2.dts
View File

@@ -618,18 +618,18 @@
};
&sfc {
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
status = "okay";
spi_flash: xt25f128b@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
spi-tx-bus-width = <1>;
};
};