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arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node

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The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
This commit is contained in:
Suman Anna
2020-08-17 18:15:10 -05:00
committed by Lokesh Vutla
parent 7873e9df8f
commit 10c4de02f0
2 changed files with 45 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/dts/k3-j7200-common-proc-board.dts
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@@ -13,6 +13,11 @@
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
aliases {
remoteproc0 = &mcu_r5fss0_core0;
remoteproc1 = &mcu_r5fss0_core1;
};
};
&wkup_pmx0 {

40
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
View File

@@ -269,4 +269,44 @@
ti,cpts-periodic-outputs = <2>;
};
};
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j7200-r5fss";
lockstep-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j7200-r5f";
reg = <0x41000000 0x00010000>,
<0x41010000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <250>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 250 1>;
firmware-name = "j7200-mcu-r5f0_0-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j7200-r5f";
reg = <0x41400000 0x00008000>,
<0x41410000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <251>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 251 1>;
firmware-name = "j7200-mcu-r5f0_1-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
};
};