eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

board: phytec: phycore_imx8mp: Set VDD_ARM to 0,95V

Browse Source 
Increase VDD_ARM to prevent timing issues as VDD_SOC is
used in OD mode. Also increase GIC clock.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Teresa Remmet
2021-07-07 12:58:01 +00:00
committed by Stefano Babic
parent 60f64bec41
commit 0f166b85ac
2 changed files with 11 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
board/phytec/phycore_imx8mp/spl.c
View File

@@ -62,7 +62,8 @@ int power_init_board(void)
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
/* increase VDD_SOC to typical value 0.95V */
/* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */
@@ -71,6 +72,14 @@ int power_init_board(void)
return 0;
}
void spl_board_init(void)
{
/* Set GIC clock to 500Mhz for OD VDD_SOC. */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
}
int board_fit_config_name_match(const char *name)
{
return 0;

1
configs/phycore-imx8mp_defconfig
View File

@@ -25,6 +25,7 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y