net: eepro100: Reorder functions in the driver
Move the functions around in the driver to prepare it for DM conversion. Drop forward declarations which are not necessary anymore. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
Marek Vasut
@@ -5,13 +5,13 @@
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <cpu_func.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <miiphy.h>
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#include <linux/delay.h>
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/* Ethernet chip registers. */
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@@ -201,16 +201,6 @@ static const char i82558_config_cmd[] = {
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0x31, 0x05,
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};
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static void init_rx_ring(struct eth_device *dev);
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static void purge_tx_ring(struct eth_device *dev);
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static void read_hw_addr(struct eth_device *dev, bd_t *bis);
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static int eepro100_init(struct eth_device *dev, bd_t *bis);
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static int eepro100_send(struct eth_device *dev, void *packet, int length);
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static int eepro100_recv(struct eth_device *dev);
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static void eepro100_halt(struct eth_device *dev);
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#if defined(CONFIG_E500)
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#define bus_to_phys(a) (a)
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#define phys_to_bus(a) (a)
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@@ -353,6 +343,39 @@ static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
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#endif
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static void init_rx_ring(struct eth_device *dev)
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{
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int i;
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for (i = 0; i < NUM_RX_DESC; i++) {
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rx_ring[i].status = 0;
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rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
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cpu_to_le16 (RFD_CONTROL_S) : 0;
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rx_ring[i].link =
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cpu_to_le32(phys_to_bus((u32)&rx_ring[(i + 1) %
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NUM_RX_DESC]));
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rx_ring[i].rx_buf_addr = 0xffffffff;
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rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
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}
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flush_dcache_range((unsigned long)rx_ring,
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(unsigned long)rx_ring +
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(sizeof(*rx_ring) * NUM_RX_DESC));
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rx_next = 0;
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}
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static void purge_tx_ring(struct eth_device *dev)
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{
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tx_next = 0;
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tx_threshold = 0x01208000;
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memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
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flush_dcache_range((unsigned long)tx_ring,
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(unsigned long)tx_ring +
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(sizeof(*tx_ring) * NUM_TX_DESC));
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}
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/* Wait for the chip get the command. */
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static int wait_for_eepro100(struct eth_device *dev)
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{
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@@ -366,94 +389,6 @@ static int wait_for_eepro100(struct eth_device *dev)
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return 1;
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}
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static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
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{}
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};
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int eepro100_initialize(bd_t *bis)
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{
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pci_dev_t devno;
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int card_number = 0;
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struct eth_device *dev;
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u32 iobase, status;
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int idx = 0;
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while (1) {
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/* Find PCI device */
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devno = pci_find_devices(supported, idx++);
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if (devno < 0)
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break;
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pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
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iobase &= ~0xf;
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debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
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iobase);
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pci_write_config_dword(devno, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Check if I/O accesses and Bus Mastering are enabled. */
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pci_read_config_dword(devno, PCI_COMMAND, &status);
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if (!(status & PCI_COMMAND_MEMORY)) {
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printf("Error: Can not enable MEM access.\n");
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continue;
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}
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if (!(status & PCI_COMMAND_MASTER)) {
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printf("Error: Can not enable Bus Mastering.\n");
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continue;
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}
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dev = (struct eth_device *)malloc(sizeof(*dev));
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if (!dev) {
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printf("eepro100: Can not allocate memory\n");
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break;
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}
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memset(dev, 0, sizeof(*dev));
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sprintf(dev->name, "i82559#%d", card_number);
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dev->priv = (void *)devno; /* this have to come before bus_to_phys() */
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dev->iobase = bus_to_phys(iobase);
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dev->init = eepro100_init;
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dev->halt = eepro100_halt;
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dev->send = eepro100_send;
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dev->recv = eepro100_recv;
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eth_register(dev);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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/* register mii command access routines */
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
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mdiodev->read = eepro100_miiphy_read;
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mdiodev->write = eepro100_miiphy_write;
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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#endif
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card_number++;
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/* Set the latency timer for value. */
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pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
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udelay(10 * 1000);
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read_hw_addr(dev, bis);
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}
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return card_number;
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}
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static int eepro100_txcmd_send(struct eth_device *dev,
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struct eepro100_txfd *desc)
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{
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@@ -494,6 +429,71 @@ static int eepro100_txcmd_send(struct eth_device *dev,
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return 0;
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}
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/* SROM Read. */
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static int read_eeprom(struct eth_device *dev, int location, int addr_len)
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{
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unsigned short retval = 0;
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int read_cmd = location | EE_READ_CMD;
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int i;
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OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
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OUTW(dev, EE_ENB, SCB_EEPROM);
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/* Shift the read command bits out. */
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for (i = 12; i >= 0; i--) {
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short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
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OUTW(dev, EE_ENB | dataval, SCB_EEPROM);
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udelay(1);
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OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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}
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OUTW(dev, EE_ENB, SCB_EEPROM);
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for (i = 15; i >= 0; i--) {
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OUTW(dev, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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retval = (retval << 1) |
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((INW(dev, SCB_EEPROM) & EE_DATA_READ) ? 1 : 0);
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OUTW(dev, EE_ENB, SCB_EEPROM);
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udelay(1);
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}
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/* Terminate the EEPROM access. */
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OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
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return retval;
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}
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static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
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{}
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};
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static void read_hw_addr(struct eth_device *dev, bd_t *bis)
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{
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u16 sum = 0;
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int i, j;
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int addr_len = read_eeprom(dev, 0, 6) == 0xffff ? 8 : 6;
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for (j = 0, i = 0; i < 0x40; i++) {
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u16 value = read_eeprom(dev, i, addr_len);
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sum += value;
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if (i < 3) {
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dev->enetaddr[j++] = value;
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dev->enetaddr[j++] = value >> 8;
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}
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}
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if (sum != 0xBABA) {
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memset(dev->enetaddr, 0, ETH_ALEN);
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debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
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dev->name, sum);
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}
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}
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static int eepro100_init(struct eth_device *dev, bd_t *bis)
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{
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struct eepro100_txfd *ias_cmd, *cfg_cmd;
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@@ -711,93 +711,83 @@ done:
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return;
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}
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/* SROM Read. */
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static int read_eeprom(struct eth_device *dev, int location, int addr_len)
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int eepro100_initialize(bd_t *bis)
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{
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unsigned short retval = 0;
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int read_cmd = location | EE_READ_CMD;
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int i;
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pci_dev_t devno;
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int card_number = 0;
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struct eth_device *dev;
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u32 iobase, status;
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int idx = 0;
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OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
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OUTW(dev, EE_ENB, SCB_EEPROM);
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while (1) {
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/* Find PCI device */
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devno = pci_find_devices(supported, idx++);
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if (devno < 0)
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break;
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/* Shift the read command bits out. */
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for (i = 12; i >= 0; i--) {
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short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
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pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
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iobase &= ~0xf;
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OUTW(dev, EE_ENB | dataval, SCB_EEPROM);
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udelay(1);
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OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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}
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OUTW(dev, EE_ENB, SCB_EEPROM);
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debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
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iobase);
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for (i = 15; i >= 0; i--) {
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OUTW(dev, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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retval = (retval << 1) |
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((INW(dev, SCB_EEPROM) & EE_DATA_READ) ? 1 : 0);
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OUTW(dev, EE_ENB, SCB_EEPROM);
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udelay(1);
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}
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pci_write_config_dword(devno, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Terminate the EEPROM access. */
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OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
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return retval;
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}
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static void init_rx_ring(struct eth_device *dev)
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{
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int i;
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for (i = 0; i < NUM_RX_DESC; i++) {
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rx_ring[i].status = 0;
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rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
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cpu_to_le16 (RFD_CONTROL_S) : 0;
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rx_ring[i].link =
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cpu_to_le32(phys_to_bus((u32)&rx_ring[(i + 1) %
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NUM_RX_DESC]));
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rx_ring[i].rx_buf_addr = 0xffffffff;
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rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
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}
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flush_dcache_range((unsigned long)rx_ring,
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(unsigned long)rx_ring +
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(sizeof(*rx_ring) * NUM_RX_DESC));
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rx_next = 0;
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}
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static void purge_tx_ring(struct eth_device *dev)
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{
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tx_next = 0;
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tx_threshold = 0x01208000;
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memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
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flush_dcache_range((unsigned long)tx_ring,
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(unsigned long)tx_ring +
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(sizeof(*tx_ring) * NUM_TX_DESC));
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}
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static void read_hw_addr(struct eth_device *dev, bd_t *bis)
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{
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u16 sum = 0;
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int i, j;
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int addr_len = read_eeprom(dev, 0, 6) == 0xffff ? 8 : 6;
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for (j = 0, i = 0; i < 0x40; i++) {
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u16 value = read_eeprom(dev, i, addr_len);
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sum += value;
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if (i < 3) {
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dev->enetaddr[j++] = value;
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dev->enetaddr[j++] = value >> 8;
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/* Check if I/O accesses and Bus Mastering are enabled. */
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pci_read_config_dword(devno, PCI_COMMAND, &status);
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if (!(status & PCI_COMMAND_MEMORY)) {
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printf("Error: Can not enable MEM access.\n");
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continue;
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}
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if (!(status & PCI_COMMAND_MASTER)) {
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printf("Error: Can not enable Bus Mastering.\n");
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continue;
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}
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dev = (struct eth_device *)malloc(sizeof(*dev));
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if (!dev) {
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printf("eepro100: Can not allocate memory\n");
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break;
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}
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memset(dev, 0, sizeof(*dev));
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sprintf(dev->name, "i82559#%d", card_number);
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dev->priv = (void *)devno; /* this have to come before bus_to_phys() */
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dev->iobase = bus_to_phys(iobase);
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dev->init = eepro100_init;
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dev->halt = eepro100_halt;
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dev->send = eepro100_send;
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dev->recv = eepro100_recv;
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eth_register(dev);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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/* register mii command access routines */
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
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mdiodev->read = eepro100_miiphy_read;
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mdiodev->write = eepro100_miiphy_write;
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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#endif
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card_number++;
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/* Set the latency timer for value. */
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pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
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udelay(10 * 1000);
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read_hw_addr(dev, bis);
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}
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if (sum != 0xBABA) {
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memset(dev->enetaddr, 0, ETH_ALEN);
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debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
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dev->name, sum);
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}
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return card_number;
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}
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