Add kernel generated files and fix SPI Makefile for VPS builds

- Force-add kernel include/generated/ and include/config/ headers needed
  for out-of-tree module compilation (autoconf.h, asm-offsets.h, etc.)
- Force-add kernel .config, Module.symvers, and build tool binaries
  (scripts/basic/fixdep, scripts/mod/modpost) for kbuild module support
- Fix SPI tools Makefile: use PATH-relative arm-linux-gnueabihf-gcc
  instead of hardcoded /opt/gcc-arm-eabihf/bin/ path

These files enable the z80drv, ttymzdrv kernel modules and SPI tools
to build on the VPS Jenkins without running make defconfig first.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 16:29:32  June 24, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "16:29:32  September 10, 2021"
+
+# Revisions
+
+PROJECT_REVISION = "tzpuFusionX_PCW8256"

CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256.qsf

@@ -0,0 +1,243 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 16:29:32  June 24, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		tzpuFusionX.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY MAX7000AE
+set_global_assignment -name DEVICE "EPM7512AETC144-10"
+set_global_assignment -name TOP_LEVEL_ENTITY tzpuFusionX_PCW8256
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32  JUNE 24, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
+
+# Z80 Data Bus
+# ============
+set_location_assignment PIN_81 -to Z80_DATA[0]
+set_location_assignment PIN_78 -to Z80_DATA[1]
+set_location_assignment PIN_87 -to Z80_DATA[2]
+set_location_assignment PIN_100 -to Z80_DATA[3]
+set_location_assignment PIN_102 -to Z80_DATA[4]
+set_location_assignment PIN_93 -to Z80_DATA[5]
+set_location_assignment PIN_94 -to Z80_DATA[6]
+set_location_assignment PIN_84 -to Z80_DATA[7]
+
+# Z80 Control signals.
+# ====================
+set_location_assignment PIN_69 -to Z80_INTn
+set_location_assignment PIN_70 -to Z80_NMIn
+set_location_assignment PIN_71 -to Z80_HALTn
+set_location_assignment PIN_68 -to Z80_MREQn
+set_location_assignment PIN_65 -to Z80_IORQn
+set_location_assignment PIN_67 -to Z80_RDn
+set_location_assignment PIN_66 -to Z80_WRn
+set_location_assignment PIN_63 -to Z80_BUSAKn
+set_location_assignment PIN_62 -to Z80_WAITn
+set_location_assignment PIN_61 -to Z80_BUSRQn
+set_location_assignment PIN_79 -to Z80_RFSHn
+set_location_assignment PIN_60 -to Z80_M1n
+set_location_assignment PIN_56 -to Z80_RESETn
+set_location_assignment PIN_101 -to Z80_CLK
+
+# Z80 Address Bus
+# ===============
+set_location_assignment PIN_80 -to Z80_ADDR[0]
+set_location_assignment PIN_90 -to Z80_ADDR[1]
+set_location_assignment PIN_83 -to Z80_ADDR[2]
+set_location_assignment PIN_86 -to Z80_ADDR[3]
+set_location_assignment PIN_88 -to Z80_ADDR[4]
+set_location_assignment PIN_91 -to Z80_ADDR[5]
+set_location_assignment PIN_92 -to Z80_ADDR[6]
+set_location_assignment PIN_96 -to Z80_ADDR[7]
+set_location_assignment PIN_97 -to Z80_ADDR[8]
+set_location_assignment PIN_98 -to Z80_ADDR[9]
+set_location_assignment PIN_99 -to Z80_ADDR[10]
+set_location_assignment PIN_110 -to Z80_ADDR[11]
+set_location_assignment PIN_108 -to Z80_ADDR[12]
+set_location_assignment PIN_107 -to Z80_ADDR[13]
+set_location_assignment PIN_106 -to Z80_ADDR[14]
+set_location_assignment PIN_103 -to Z80_ADDR[15]
+
+# SOM SPI
+# =======
+set_location_assignment PIN_32 -to VSOM_SPI_CSn
+set_location_assignment PIN_31 -to VSOM_SPI_CLK
+set_location_assignment PIN_30 -to VSOM_SPI_MOSI
+set_location_assignment PIN_29 -to VSOM_SPI_MISO
+
+# SOM Parallel Bus
+# ================
+set_location_assignment PIN_41 -to VSOM_DATA_OUT[0]
+set_location_assignment PIN_40 -to VSOM_DATA_OUT[1]
+set_location_assignment PIN_39 -to VSOM_DATA_OUT[2]
+set_location_assignment PIN_38 -to VSOM_DATA_OUT[3]
+set_location_assignment PIN_37 -to VSOM_DATA_OUT[4]
+set_location_assignment PIN_36 -to VSOM_DATA_OUT[5]
+set_location_assignment PIN_35 -to VSOM_DATA_OUT[6]
+set_location_assignment PIN_34 -to VSOM_DATA_OUT[7]
+set_location_assignment PIN_132 -to VSOM_HBYTE
+
+# SOM Reserved signals.
+# =====================
+set_location_assignment PIN_21 -to VSOM_RSV[1]
+
+# SOM Control Signals
+# ===================
+set_location_assignment PIN_28 -to VSOM_READY
+set_location_assignment PIN_19 -to VSOM_LTSTATE
+set_location_assignment PIN_27 -to VSOM_BUSRQ
+set_location_assignment PIN_26 -to VSOM_BUSACK
+set_location_assignment PIN_18 -to VSOM_INT
+set_location_assignment PIN_22 -to VSOM_NMI
+set_location_assignment PIN_25 -to VSOM_WAIT
+set_location_assignment PIN_23 -to VSOM_RESET
+set_location_assignment PIN_16 -to PM_RESET
+
+# VGA_Palette Control
+# ===================
+set_location_assignment PIN_133 -to VGA_R[7]
+set_location_assignment PIN_137 -to VGA_R[8]
+set_location_assignment PIN_140 -to VGA_R[9]
+set_location_assignment PIN_134 -to VGA_G[7]
+set_location_assignment PIN_138 -to VGA_G[8]
+set_location_assignment PIN_141 -to VGA_G[9]
+set_location_assignment PIN_136 -to VGA_B[8]
+set_location_assignment PIN_139 -to VGA_B[9]
+
+
+# VGA Control Signals
+# ===================
+set_location_assignment PIN_142 -to VGA_PXL_CLK
+set_location_assignment PIN_14 -to VGA_DISPEN
+set_location_assignment PIN_12 -to VGA_VSYNCn
+set_location_assignment PIN_11 -to VGA_HSYNCn
+set_location_assignment PIN_82 -to VGA_COLR
+set_location_assignment PIN_109 -to VGA_CSYNCn
+set_location_assignment PIN_143 -to VGA_BLANKn
+
+# CRT Control Signals
+# ===================
+set_location_assignment PIN_15 -to MONO_PXL_CLK
+set_location_assignment PIN_114 -to MONO_BLANKn
+set_location_assignment PIN_113 -to MONO_CSYNCn
+set_location_assignment PIN_116 -to MONO_RSV
+
+# CRT Lower Chrominance Control
+# =============================
+set_location_assignment PIN_1 -to MONO_R[0]
+set_location_assignment PIN_6 -to MONO_R[1]
+set_location_assignment PIN_10 -to MONO_R[2]
+set_location_assignment PIN_2 -to MONO_G[0]
+set_location_assignment PIN_7 -to MONO_G[1]
+set_location_assignment PIN_9 -to MONO_G[2]
+set_location_assignment PIN_5 -to MONO_B[1]
+set_location_assignment PIN_8 -to MONO_B[2]
+
+# MUX Control Signals
+# ===================
+set_location_assignment PIN_72 -to VIDEO_SRC
+set_location_assignment PIN_74 -to MONO_VIDEO_SRC
+set_location_assignment PIN_77 -to AUDIO_SRC_L
+set_location_assignment PIN_75 -to AUDIO_SRC_R
+
+# Mainboard Reset Signals
+# =======================
+#set_location_assignment PIN_127 -to CPU_RESETn
+set_location_assignment PIN_122 -to MB_RESETn
+set_location_assignment PIN_111 -to MB_IPLn
+
+# USB Power Control
+# =================
+set_location_assignment PIN_55 -to VBUS_EN
+
+# Clocks
+# ======
+#set_location_assignment PIN_125 -to CPU_CLK
+set_location_assignment PIN_128 -to CLK_50M
+
+# Unused ports
+# ============
+#set_location_assignment PIN_42  -to 
+#set_location_assignment PIN_43  -to 
+#set_location_assignment PIN_44  -to 
+#set_location_assignment PIN_45  -to 
+#set_location_assignment PIN_112 -to 
+#set_location_assignment PIN_131 -to 
+#set_location_assignment PIN_117 -to 
+#set_location_assignment PIN_118 -to 
+#set_location_assignment PIN_119 -to 
+#set_location_assignment PIN_120 -to 
+#set_location_assignment PIN_121 -to 
+#set_location_assignment PIN_25  -to 
+#set_location_assignment PIN_53  -to 
+#set_location_assignment PIN_128 -to 
+#set_location_assignment PIN_47  -to 
+#set_location_assignment PIN_54  -to 
+#set_location_assignment PIN_127 -to 
+#set_location_assignment PIN_125 -to 
+#set_location_assignment PIN_48  -to 
+#set_location_assignment PIN_46  -to 
+#set_location_assignment PIN_49  -to 
+
+
+set_global_assignment -name VHDL_FILE ../tzpuFusionX_Toplevel.vhd
+set_global_assignment -name VHDL_FILE ../tzpuFusionX_pkg.vhd
+set_global_assignment -name VHDL_FILE ../tzpuFusionX.vhd
+set_global_assignment -name SDC_FILE tzpuFusionX_PCW8256_constraints.sdc
+
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
+set_global_assignment -name AUTO_RESOURCE_SHARING OFF
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF
+
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF
+set_global_assignment -name AUTO_LCELL_INSERTION ON
+
+set_global_assignment -name CDF_FILE output_files/tzpuFusionX_PCW8256.cdf

CPLD/v1.0/PCW8256/build/tzpuFusionX_PCW8256_constraints.sdc

@@ -0,0 +1,324 @@
+## Generated SDC file "tzpuFusionX.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
+
+## DATE    "Fri Jun 26 22:10:05 2020"
+
+##
+## DEVICE  "EPM7160STC100-10"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+# Standard mainboard clock. If using tzpuFusionX on a different host then set to the host frequency.
+create_clock -name {Z80_CLK} -period 250.000 -waveform { 0.000 125.000 } [get_ports { Z80_CLK }]
+
+# For 50MHz crystal.
+create_clock -name {CLK_50M} -period 20.000 -waveform { 0.000 10.000 }   [ get_ports { CLK_50M }]
+
+# For SPI CSn
+#create_clock -name {VSOM_SPI_CSn} -period 200.000 -waveform { 160.000 40.000 }   [ get_ports { VSOM_SPI_CSn }]
+
+# For SPI CLK
+create_clock -name {VSOM_SPI_CLK} -period 14.000 -waveform { 0.000 7.000 }   [ get_ports { VSOM_SPI_CLK }]
+
+# For basic board with oscillator.
+#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 }   [ get_ports { CTLCLK }]
+#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ]
+##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {CTL_MBSEL}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {CTL_BUSRQn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {CTL_WAITn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {SYS_BUSRQn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {SYS_WAITn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_ADDR[*]}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_HI_ADDR[*]}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {VZ80_ADDR[*]}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_BUSACKn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_DATA[*]}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_HALTn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_IORQn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_M1n}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_MREQn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_RESETn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_RFSHn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_WRn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {Z80_RDn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {R_IN}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {G_IN}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {B_IN}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {COLR_IN}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {CSYNC_IN}]
+##set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {CVIDEO_IN}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {HSYNC_IN}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {VSYNC_IN}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  1.000 [get_ports {VZ80_DATA[*]}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_MREQn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_IORQn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_WRn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_RDn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_M1n}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_BUSACKn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_INTn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_NMIn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_WAITn}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VWAITn_A21_V_CSYNC}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}]
+#set_input_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {CTL_BUSACKn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {CTL_HALTn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {CTL_M1n}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {CTL_RFSHn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {RAM_CSn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {RAM_CS2n}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {RAM_OEn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {RAM_WEn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {SVCREQn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {SYS_BUSACKn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_BUSRQn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_DATA[*]}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_ADDR[*]}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_HI_ADDR[*]}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_RA_ADDR[*]}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_WAITn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_MREQn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_CLK}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_ADDR[*]}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_DATA[*]}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_CLK}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_MREQn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_IORQn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_RDn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_WRn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_M1n}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VIDEO_RDn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VIDEO_WRn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_A18_INTn_V_R}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_BUSRQn_V_G}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_A16_WAITn_V_B}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_A17_NMIn_V_COLR}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VWAITn_A21_V_CSYNC}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_HALTn}]
+#set_output_delay -add_delay  -clock [get_clocks {SYSCLK}]  5.000 [get_ports {Z80_RFSHn}]
+
+# For K64F
+#set_output_delay -add_delay  -clock [get_clocks {CTLCLK}]  5.000 [get_ports {Z80_CLK}]
+
+# For basic board with oscillator.
+#set_output_delay -add_delay  -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}]  5.000 [get_ports {Z80_CLK}]
+
+#**************************************************************
+# Set Max Delay
+#**************************************************************
+#set_max_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_HALTn} 30.000
+#set_max_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_IORQn} 30.000
+#set_max_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_M1n}   30.000
+#set_max_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_RDn}   30.000
+#set_max_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_WRn}   30.000
+#set_max_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_RFSHn} 30.000
+#set_max_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}]        -to {Z80_HALTn} 30.000
+#set_max_delay -from [get_ports {VZ80_IORQn}]                    -to {Z80_IORQn} 30.000
+#set_max_delay -from [get_ports {VZ80_MREQn}]                    -to {Z80_IORQn} 30.000
+#set_max_delay -from [get_ports {VZ80_M1n}]                      -to {Z80_M1n}   30.000
+#set_max_delay -from [get_ports {VZ80_RDn}]                      -to {Z80_RDn}   30.000
+#set_max_delay -from [get_ports {VZ80_WRn}]                      -to {Z80_WRn}   30.000
+#set_max_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_HALTn} 40.000
+#set_max_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_RFSHn} 40.000
+#set_max_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_IORQn} 40.000
+#set_max_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_M1n}   30.000
+#set_max_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_RDn}   30.000
+#set_max_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_WRn}   30.000
+#set_max_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}]        -to {Z80_RFSHn} 30.000
+#set_max_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_HALTn} 30.000
+#set_max_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_IORQn} 30.000
+#set_max_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_M1n}   30.000
+#set_max_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_RDn}   30.000
+#set_max_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_WRn}   30.000
+#set_max_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_RFSHn} 30.000
+#set_max_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_HALTn}]   45.000
+#set_max_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_IORQn}]   30.000
+#set_max_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_M1n}]     30.000
+#set_max_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_RDn}]     30.000
+#set_max_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_RFSHn}]   45.000
+#set_max_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_WRn}]     30.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}]   45.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}]   50.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}]     40.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}]     40.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}]     40.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}]   45.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_HALTn}]   60.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_IORQn}]   45.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_M1n}]     40.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_RDn}]     40.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_WRn}]     40.000
+#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_RFSHn}]   60.000
+
+#**************************************************************
+# Set Min Delay
+#**************************************************************
+#set_min_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_HALTn} 1.000
+#set_min_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_IORQn} 1.000
+#set_min_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_M1n}   1.000
+#set_min_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_RDn}   1.000
+#set_min_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_WRn}   1.000
+#set_min_delay -from [get_ports {CTL_BUSRQn}]                    -to {Z80_RFSHn} 1.000
+#set_min_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}]        -to {Z80_HALTn} 1.000
+#set_min_delay -from [get_ports {VZ80_IORQn}]                    -to {Z80_IORQn} 1.000
+#set_min_delay -from [get_ports {VZ80_MREQn}]                    -to {Z80_IORQn} 1.000
+#set_min_delay -from [get_ports {VZ80_M1n}]                      -to {Z80_M1n}   1.000
+#set_min_delay -from [get_ports {VZ80_RDn}]                      -to {Z80_RDn}   1.000
+#set_min_delay -from [get_ports {VZ80_WRn}]                      -to {Z80_WRn}   1.000
+#set_min_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_HALTn} 1.000
+#set_min_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_RFSHn} 1.000
+#set_min_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_IORQn} 1.000
+#set_min_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_M1n}   1.000
+#set_min_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_RDn}   1.000
+#set_min_delay -from [get_ports {VZ80_BUSACKn}]                  -to {Z80_WRn}   1.000
+#set_min_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}]        -to {Z80_RFSHn} 1.000
+#set_min_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_HALTn} 1.000
+#set_min_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_IORQn} 1.000
+#set_min_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_M1n}   1.000
+#set_min_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_RDn}   1.000
+#set_min_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_WRn}   1.000
+#set_min_delay -from [get_ports {Z80_BUSACKn}]                   -to {Z80_RFSHn} 1.000
+#set_min_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_HALTn}] 1.000
+#set_min_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_IORQn}] 1.000
+#set_min_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_M1n}]   1.000
+#set_min_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_RDn}]   1.000
+#set_min_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_RFSHn}] 1.000
+#set_min_delay -from {Z80_BUSACKn}                               -to [get_ports {Z80_WRn}]   1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}]   1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}]   1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}]   1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_HALTn}] 1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_IORQn}] 1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_M1n}]   1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_RDn}]   1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_WRn}]   1.000
+#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}  -to [get_ports {Z80_RFSHn}] 1.000
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+# For K64F
+#set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}]
+#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
+
+# For basic board with oscillator.
+#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}]
+#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}]
+#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}]
+#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
+
+# For both configurations.
+#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE}    -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+#set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]}  -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+#set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]}    -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+#set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]}   -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+#set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B}   -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+#set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE}   -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2
+#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -hold -end 1
+
+#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2
+#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1
+
+#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2
+#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

build.sh

@@ -91,6 +91,7 @@ usage() {
     echo "  --drivers       Build kernel modules and user-space apps only"
     echo "  --spi           Build SPI tools only"
     echo "  --cpld          Build CPLD bitstreams only (requires Quartus Docker)"
+    echo "  --image         Build Linux SD card image (requires ARM cross-compiler)"
     echo "  --clean         Clean all build artifacts"
     echo "  --help          Show this help"
     echo ""
@@ -352,6 +353,56 @@ build_cpld() {
     done
 }
 
+#-------------------------------------------------------------------------------------------------------
+# Build Linux SD card image using Build_FusionX.sh.
+#-------------------------------------------------------------------------------------------------------
+
+build_image() {
+    log_info "Building Linux SD card image..."
+
+    local BUILD_SCRIPT="${SOFTDIR}/linux/Build_FusionX.sh"
+    local IMAGE_OUTPUT="${SOFTDIR}/linux/project/image/output/images"
+
+    if [ ! -f "${BUILD_SCRIPT}" ]; then
+        log_skip "Build_FusionX.sh not found at ${BUILD_SCRIPT}"
+        return
+    fi
+
+    if ! command -v ${CROSS_PREFIX}gcc &>/dev/null; then
+        log_skip "ARM cross-compiler (${CROSS_PREFIX}gcc) not found - cannot build Linux image"
+        return
+    fi
+
+    if [ ! -d "${SOFTDIR}/linux/kernel" ] || [ ! -d "${SOFTDIR}/linux/boot" ]; then
+        log_skip "Linux kernel/boot source tree not found"
+        return
+    fi
+
+    chmod +x "${BUILD_SCRIPT}"
+    log_info "  Running Build_FusionX.sh -f nand -p ssd202 -o 2D06 ..."
+    if "${BUILD_SCRIPT}" -f nand -p ssd202 -o 2D06 2>&1; then
+        # Check for output images.
+        local has_output=false
+        if [ -f "${IMAGE_OUTPUT}/sdrootfs.tar.gz" ]; then
+            log_ok "Image: sdrootfs.tar.gz"
+            has_output=true
+        fi
+        if [ -f "${IMAGE_OUTPUT}/SigmastarUpgradeSD.bin" ]; then
+            log_ok "Image: SigmastarUpgradeSD.bin"
+            has_output=true
+        fi
+        if [ -f "${IMAGE_OUTPUT}/SigmastarUpgrade.bin" ]; then
+            log_ok "Image: SigmastarUpgrade.bin"
+            has_output=true
+        fi
+        if ! ${has_output}; then
+            log_fail "Linux image build produced no output files"
+        fi
+    else
+        log_fail "Linux image build (Build_FusionX.sh)"
+    fi
+}
+
 #-------------------------------------------------------------------------------------------------------
 # Clean all build artifacts.
 #-------------------------------------------------------------------------------------------------------
@@ -386,6 +437,7 @@ BUILD_CPM=false
 BUILD_DRIVERS=false
 BUILD_SPI=false
 BUILD_CPLD=false
+BUILD_IMAGE=false
 BUILD_ALL=false
 DO_CLEAN=false
 
@@ -402,6 +454,7 @@ while [ $# -gt 0 ]; do
         --drivers)  BUILD_DRIVERS=true ;;
         --spi)      BUILD_SPI=true ;;
         --cpld)     BUILD_CPLD=true ;;
+        --image)    BUILD_IMAGE=true ;;
         --clean)    DO_CLEAN=true ;;
         --help|-h)  usage ;;
         *)          echo "Unknown option: $1"; usage ;;
@@ -425,6 +478,7 @@ if ${BUILD_ALL} || ${BUILD_CPM};     then build_cpm;      fi
 if ${BUILD_ALL} || ${BUILD_DRIVERS}; then build_drivers;  fi
 if ${BUILD_ALL} || ${BUILD_SPI};     then build_spi;      fi
 if ${BUILD_ALL} || ${BUILD_CPLD};    then build_cpld;     fi
+if ${BUILD_ALL} || ${BUILD_IMAGE};   then build_image;    fi
 
 echo ""
 echo "========================================"

software/FusionX/src/spitools/Makefile

@@ -42,8 +42,8 @@ ARCH := arm
 
 #Compilers
 ifeq ($(ARCH),arm)
-CPP := /opt/gcc-arm-eabihf/bin/arm-linux-gnueabihf-g++
-CC := /opt/gcc-arm-eabihf/bin/arm-linux-gnueabihf-gcc
+CPP := arm-linux-gnueabihf-g++
+CC := arm-linux-gnueabihf-gcc
 else
 CPP := g++
 CC := gcc

software/FusionX/src/ttymz/Makefile

@@ -10,7 +10,7 @@ FUSIONX        := $(PWD)/../..
 CROSS          := arm-linux-gnueabihf-
 CTRLINC        = -IZeta/API -IZ80/API -DTARGET_HOST_$(MODEL)=1
 
-ccflags-y      = -O2 -I${KERNEL}/drivers/sstar/include -I${KERNEL}/drivers/sstar/include/infinity2m -I${KERNEL}/drivers/sstar/gpio/infinity2m -D__KERNEL_DRIVER__ -DTARGET_HOST_$(MODEL)=1
+ccflags-y      = -O2 -I${KERNEL}/drivers/sstar/include -I${KERNEL}/drivers/sstar/include/infinity2m -I${KERNEL}/drivers/sstar/gpio/infinity2m -D__KERNEL_DRIVER__ -DTARGET_HOST_$(MODEL)=1 -Wno-error
 ifeq ($(DEBUG),y)
 ccflags-y      += -DTTYMZ_DEBUG
 endif

software/FusionX/src/ttymz/sharpmz.c

@@ -2455,17 +2455,34 @@ static t_ansiKeyMap ansiKeySeq[] = {
 #endif     
 
     // Set the module control structures to default values according to build target.
-    static t_displayBuffer display        = displayDefault;
-    static t_keyboard      keyboard       = keyboardDefault;
-    static t_audio         audio          = audioDefault;
-    static t_AnsiTerm      ansiterm       = ansitermDefault;
-    static t_control       ctrl           = ctrlDefault;
+    // NB: Cannot use const locals as initializers for static variables in C (not compile-time constants).
+    // Defaults are applied at runtime in sharpmz_init_defaults().
+    static t_displayBuffer display;
+    static t_keyboard      keyboard;
+    static t_audio         audio;
+    static t_AnsiTerm      ansiterm;
+    static t_control       ctrl;
+    static int             defaultsInitialised = 0;
 
 
 // --------------------------------------------------------------------------------------------------------------
 // Methods
 // --------------------------------------------------------------------------------------------------------------
 
+// Initialise the static control structures with default values.
+// Called once from the module init path before any hardware access.
+void sharpmz_init_defaults(void)
+{
+    if (!defaultsInitialised) {
+        display  = displayDefault;
+        keyboard = keyboardDefault;
+        audio    = audioDefault;
+        ansiterm = ansitermDefault;
+        ctrl     = ctrlDefault;
+        defaultsInitialised = 1;
+    }
+}
+
 // Method to configure the motherboard hardware after a reset.
 //
 uint8_t mzInitMBHardware(void)

software/FusionX/src/ttymz/sharpmz.h

@@ -556,6 +556,7 @@ typedef struct {
 
 // Prototypes.
 //
+void                                 sharpmz_init_defaults(void);
 uint8_t                              mzInitMBHardware(void);
 uint8_t                              mzInit(void);
 void                                 mzBeep(uint32_t, uint32_t);

software/FusionX/src/ttymz/ttymz.c

@@ -823,6 +823,9 @@ static int __init ttymz_init(void)
     int  i;
     char buf[80];
 
+    // Initialise the sharpmz module control structures with default values.
+    sharpmz_init_defaults();
+
     // Allocate the tty driver handles, one per potential device.
     ttymzCtrl.ttymzDriver = alloc_tty_driver(SHARPMZ_TTY_MINORS);
     if(!ttymzCtrl.ttymzDriver)

software/linux/Build_FusionX.sh

@@ -8,10 +8,11 @@
 ##                  This script builds the complete OS and software set required for FusionX.
 ##                  It builds the Linux kernel, rootfs filesystem, U-boot loader and apps.
 ##
-## Credits:         
+## Credits:
 ## Copyright:       (c) SigmaStar, tailoring by Philip Smart for FusionX
 ##
 ## History:         October 2022   - Initial tailoring for FusionX
+##                  March 2026     - Fixed hardcoded paths to be relative to project root.
 ##
 ## Synopsis:        Build_FusionX.sh -f nand -p ssd202 -o 2D06 -m 256
 ##
@@ -47,20 +48,14 @@ done
 
 DATE=$(date +%m%d)
 BACKUPDIR=$(date +%m%d%H%M)
-#images will output in ${RELEASEDIR}/images/
-RELEASEDIR=`pwd`
-FUSIONXDIR=`pwd`\..\FusionX
-WEBSRVDIR=`pwd`\..\WebServer
-Z80EMUDIR=`pwd`\..\Z80emu
-#release source code
-#find ./boot/ | grep -v boot/.git | cpio -pdm ${RELEASEDIR}/
-#find ./project/ | grep -v project/.git | cpio -pdm ${RELEASEDIR}/
-#find ./kernel/ | grep -v kernel/.git | cpio -pdm ${RELEASEDIR}/
-#find ./sdk/ | grep sdk/verify | grep -v sdk/verify/application/smarttalk | cpio -pdm ${RELEASEDIR}/
 
-#save code version
-#repo manifest -o snapshot.xml -r
-#cp snapshot.xml ${RELEASEDIR}/sdk_version.xml
+# Resolve the script's directory to establish relative paths.
+SCRIPTDIR="$(cd "$(dirname "$0")" && pwd)"
+RELEASEDIR="${SCRIPTDIR}"
+SOFTWAREDIR="$(cd "${SCRIPTDIR}/.." && pwd)"
+FUSIONXDIR="${SOFTWAREDIR}/FusionX"
+WEBSRVDIR="${SOFTWAREDIR}/WebServer"
+Z80EMUDIR="${SOFTWAREDIR}/Z80emu"
 
 export ARCH=arm
 
@@ -69,14 +64,14 @@ echo chose ${flashtype}
 if [ ! "${project}" = "2D06" -a ! "${project}" = "2D07" ]; then
 	project=2D07
 	#exit 1
-fi	
+fi
 
 # Make the output directories if not present.
 mkdir -p ${RELEASEDIR}/project/image/output/
 for f in miservice appconfigs customer vendor rootfs images
 do
     mkdir -p ${RELEASEDIR}/project/image/output/$f
-done 
+done
 
 export PROJECT=${project}
 
@@ -127,7 +122,7 @@ if [ "${flashtype}" = "nor" ]; then
 		echo "Make Kernel 2"
 		make infinity2m_ssc011a_s01a_minigui_defconfig
 	fi
-	
+
 else
 	if [ "${fastboot}" = "fastboot" ]; then
 		echo "Make Kernel 3"
@@ -137,7 +132,7 @@ else
 		#make infinity2m_spinand_ssc011a_s01a_minigui_defconfig
 		make ${KERNEL_DEFCONFIG}
 	fi
-	
+
 fi
 if [ "${clean}" = "1" ]; then
 	make clean
@@ -160,9 +155,9 @@ if [ "${flashtype}" = "nor" ]; then
 	fi
 else
 	if [ "${fastboot}" = "fastboot" ]; then
-		if [ "${chip}" = "ssd201" ]; then 
+		if [ "${chip}" = "ssd201" ]; then
 			./setup_config.sh ./configs/nvr/i2m/8.2.1/spinand.ram-glibc-squashfs.011a.64
-		elif [ "${chip}" = "ssd202" ]; then	
+		elif [ "${chip}" = "ssd202" ]; then
 			./setup_config.sh ./configs/nvr/i2m/8.2.1/spinand.ram-glibc-squashfs.011a.128
 		fi
 	else
@@ -191,11 +186,11 @@ else
 	else
 		./release.sh -k ${RELEASEDIR}/kernel -b 011A -p nvr -f spinand -c i2m -l glibc -v 8.2.1
 	fi
-	
+
 fi
 
 cd ${RELEASEDIR}/project
-make clean;make image-nocheck
+make clean;make image-nocheck || echo "WARNING: make image-nocheck had errors (non-fatal, SD rootfs build continues)"
 
 # Save the rootfs before copying latest release.
 if [ -f ${RELEASEDIR}/project/image/rootfs/rootfs ]; then
@@ -284,9 +279,9 @@ if [ -d ${Z80EMUDIR} ]; then
     mkdir -p ${RELEASEDIR}/project/image/output/sdrootfs/apps/Z80/
     cp -r Z80/* ${RELEASEDIR}/project/image/output/sdrootfs/apps/Z80/
 fi
-if [ -d /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/custom ]; then
+if [ -d ${RELEASEDIR}/project/custom ]; then
     echo -n "Custom "
-    cd /srv/dvlp/Projects/tzpu/FusionX/software/linux/project/
+    cd ${RELEASEDIR}/project/
     mkdir -p ${RELEASEDIR}/project/image/output/sdrootfs/apps/custom/
     cp -r custom/* ${RELEASEDIR}/project/image/output/sdrootfs/apps/custom/
 fi
@@ -294,13 +289,17 @@ fi
 # Copy any new files.
 for f in DSK MZF CPM BAS CAS Basic
 do
-    mkdir -p ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/disk/
-    cp -r /srv/dvlp/Projects/tzpu/FusionX/software/${f}/ ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/disk/${f}/
+    if [ -d ${SOFTWAREDIR}/${f} ]; then
+        mkdir -p ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/disk/
+        cp -r ${SOFTWAREDIR}/${f}/ ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/disk/${f}/
+    fi
 done
 
-# Copy an new rom images.
-mkdir -p ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/roms/
-cp -r /srv/dvlp/Projects/tzpu/FusionX/software/roms/* ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/roms/
+# Copy any new rom images.
+if [ -d ${SOFTWAREDIR}/roms ]; then
+    mkdir -p ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/roms/
+    cp -r ${SOFTWAREDIR}/roms/* ${RELEASEDIR}/project/image/output/sdrootfs/apps/FusionX/roms/
+fi
 
 # Make any manual setup changes.
 #echo "/dev/zram0     none swap sw 0 -1"         >> ${RELEASEDIR}/project/image/output/sdrootfs/etc/fstab
@@ -327,9 +326,9 @@ tar -cf ${RELEASEDIR}/project/image/output/images/sdrootfs.tar.gz *
 echo "Building Upgrade image in project/image/output/images/ - "
 cd ${RELEASEDIR}/project/
 echo -n "SigmastarUpgradeSD.bin "
-yes | ./make_sd_upgrade_sigmastar.sh
+yes | ./make_sd_upgrade_sigmastar.sh || echo "(incomplete - flash images not fully generated)"
 echo -n "SigmastarUpgrade.bin "
-yes | ./make_usb_upgrade_sigmastar.sh
+yes | ./make_usb_upgrade_sigmastar.sh || echo "(incomplete - flash images not fully generated)"
 echo ""
 
 echo "Copy image to SD card or USB drive, install and reboot FusionX to upgrade."
@@ -342,14 +341,7 @@ echo "      /dev/sdc3       6293504 62333951 56040448 26.7G 83 Linux"
 echo "  mkfs.vfat /dev/<sd partition 1>"
 echo "  mkfs.ext2 /dev/<sd partition 3>"
 echo "  mkdir -p /mnt/upgrade; mount /dev/<sd partition 1> /mnt/upgrade"
-echo "  mkdir -p /mnt/rootfd;  mount /dev/<sd partition 3> /mnt/rootfs"
+echo "  mkdir -p /mnt/rootfs;  mount /dev/<sd partition 3> /mnt/rootfs"
 echo "  cp ${RELEASEDIR}/project/image/output/images/SigmastarUpgradeSD.bin /mnt/upgrade/FusionX.bin"
-echo "  cd /mnt/rootfs; tar -xvf /dvlp/Projects/tzpu/FusionX/software/linux/project/image/output/images/sdrootfs.tar.gz; sync; sync"
+echo "  cd /mnt/rootfs; tar -xvf ${RELEASEDIR}/project/image/output/images/sdrootfs.tar.gz; sync; sync"
 echo "  cd /; umount /mnt/upgrade; umount /mnt/rootfs"
-
-#tar -cvzf boot_${DATE}.tar.gz boot
-#tar -cvzf kernel_${DATE}.tar.gz kernel
-#tar -cvzf project_${DATE}.tar.gz project
-#tar -cvzf sdk_${DATE}.tar.gz sdk
-
-

software/linux/kernel/include/config/auto.conf

@@ -0,0 +1,712 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.9.84 Kernel Configuration
+#
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SCSI_DMA=y
+CONFIG_ATAGS=y
+CONFIG_MSTAR_DRIVERS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_SLUB_CPU_PARTIAL=y
+CONFIG_RFS_ACCEL=y
+CONFIG_CRC32=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_VFP=y
+CONFIG_AEABI=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_INOTIFY_USER=y
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_GLOB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_SSB_POSSIBLE=y
+CONFIG_MP_USB_MSTAR=y
+CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a-rgb565-rmii-doublenet"
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_UHID=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_SWPHY=y
+CONFIG_FSNOTIFY=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_BQL=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
+CONFIG_DEVTMPFS=y
+CONFIG_MS_GPIO=y
+CONFIG_WLAN=y
+CONFIG_NAMESPACES=y
+CONFIG_MP_IRQ_TRACE=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_MSDOS_FS=m
+CONFIG_SS_SATA_HOST=y
+CONFIG_SSTAR_SHORT_NAME=""
+CONFIG_CFG80211=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_USB=y
+CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_MSTAR_MMAHEAP=y
+CONFIG_ARM_ASM_UNIFIED=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_DQL=y
+CONFIG_COREDUMP=y
+CONFIG_BCMA_POSSIBLE=y
+CONFIG_FORCE_MAX_ZONEORDER=10
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_NAND_QUAL_READ=y
+CONFIG_PRINTK=y
+CONFIG_SSTAR_NETPHY=y
+CONFIG_TIMERFD=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_SHMEM=y
+CONFIG_MTD=y
+CONFIG_MIGRATION=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_SKIP_SQUASHFS_BAD_BLOCK=y
+CONFIG_MS_SPI_INFINITY=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DNOTIFY=y
+CONFIG_SS_HOST_UVC=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_MS_CPU_FREQ=y
+CONFIG_ATA=y
+CONFIG_MTD_TESTS=m
+CONFIG_CRYPTO_DES=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_VDSO=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_CRYPTODEV=m
+CONFIG_ARM_GIC=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_SERIO=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_ANALOG_PD_IDAC_ATOP=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKD=m
+CONFIG_SSTAR_CHIP_NAME="infinity2m"
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_ARM=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_JFFS2_FS=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_KERNEL_XZ=y
+CONFIG_MS_FLASH_ISP=y
+CONFIG_USB_STORAGE=m
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_RATIONAL=y
+CONFIG_I2C_MUX=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_BLOCK=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_BUG=y
+CONFIG_CLKSRC_OF=y
+CONFIG_SPI=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+CONFIG_OF_IRQ=y
+CONFIG_LIBFDT=y
+CONFIG_VT=y
+CONFIG_DTC=y
+CONFIG_REGMAP_SPI=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_SBITMAP=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_WEXT_CORE=y
+CONFIG_NLS=y
+CONFIG_MS_CRYPTO=m
+CONFIG_SPI_SPIDEV=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_SYN_COOKIES=y
+CONFIG_IRQ_WORK=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_USB_COMMON=y
+CONFIG_FIXED_PHY=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_OF_NET=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_DISCONNECT_DELAY_S=1
+CONFIG_SG_POOL=y
+CONFIG_MS_MSYS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_NETDEVICES=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_EVENTFD=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_HZ_100=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_BPF=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_SS_FAST_MMC=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_MS_KERNEL_TYPE=""
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SS_SATA_AHCI_PLATFORM_HOST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_EXT3_FS=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_FAT_FS=m
+CONFIG_MAY_USE_DEVLINK=y
+CONFIG_NVMEM=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_MS_EMMC_UNIFY_DRIVER=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MS_I2C=y
+CONFIG_CPU_FREQ=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=16
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_NAND_QUAL_WRITE=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_PWM_SYSFS=y
+CONFIG_SWIOTLB=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_ELFCORE=y
+CONFIG_CPU_SW_DOMAIN_PAN=y
+CONFIG_BINFMT_ELF=y
+CONFIG_SCSI_PROC_FS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_CPU_CP15=y
+CONFIG_HZ_FIXED=0
+CONFIG_MS_ZEN=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_NMI_LOG_BUF_SHIFT=13
+CONFIG_USE_OF=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_SPI_MASTER=y
+CONFIG_MS_SDMMC=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_CRC16=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TMPFS=y
+CONFIG_ANON_INODES=y
+CONFIG_FUTEX=y
+CONFIG_REGMAP_I2C=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_VMSPLIT_3G=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_USB_HID=y
+CONFIG_UBIFS_FS=y
+CONFIG_ANDROID=y
+CONFIG_SYSVIPC=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_MODULES=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_EEPROM_LEGACY=m
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_UNIX=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_HAVE_CLK=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SRCU=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_NFS_FS=m
+CONFIG_MEMBARRIER=y
+CONFIG_XPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_PM_OPP=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+CONFIG_NFS_COMMON=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_WLAN_VENDOR_ATH=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_VFAT_FS=m
+CONFIG_PID_NS=y
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CPU_RMAP=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_MULTIUSER=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_FS_MBCACHE=y
+CONFIG_RTC_CLASS=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_ANALOG_PD_IDAC_LPLL=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_TOUCHSCREEN_PROPERTIES=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_SLUB=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EMAC_PHY_RESTART_AN=y
+CONFIG_MTD_UBI=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_I2C=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_MS_EMMC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_DEBUG_FS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_CC_STACKPROTECTOR_REGULAR=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_MS_MOVE_DMA=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_SUNRPC=m
+CONFIG_GPIO_SYSFS=y
+CONFIG_FW_LOADER=y
+CONFIG_KALLSYMS=y
+CONFIG_COMMON_CLK=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_PWM=y
+CONFIG_MS_RTC=y
+CONFIG_MII=y
+CONFIG_SIGNALFD=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_EXT4_FS=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_MS_FLASH_ISP_MXP_PARTS=y
+CONFIG_SS_BUILTIN_DTB=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_XZ_DEC=y
+CONFIG_SATA_PMP=y
+CONFIG_WATCHDOG=y
+CONFIG_HAS_IOMEM=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_SCHED_HRTICK=y
+CONFIG_EPOLL=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_DEFERRED_INIICALLS=y
+CONFIG_TOUCHSCREEN_FTS_DIRECTORY="focaltech_touch"
+CONFIG_HAVE_NET_DSA=y
+CONFIG_NET=y
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_VFPv3=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_PACKET=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_INET=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_MSTAR_MIU=y
+CONFIG_RTC_LIB=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_CRYPTO_AES=y
+CONFIG_GPIOLIB=y
+CONFIG_SWP_EMULATE=y
+CONFIG_UIO=y
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SS_VOLTAGE_CTRL=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_HAVE_NMI=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_PRINTK_NMI=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_NO_HZ=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_TOUCHSCREEN_FTS=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_CPU_V7=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_SATA_HOST_0=m
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_SMP=y
+CONFIG_TTY=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_GENERIC_IO=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_GENERIC_BUG=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HW_CONSOLE=y
+CONFIG_DEVMEM=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_ARM_PMU=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_HAVE_UID16=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_NEON=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_MTD_RAM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_LOCALVERSION=""
+CONFIG_CRYPTO=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CMDLINE=""
+CONFIG_ANALOG_PD_SATA_ATOP=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_DEFAULT_CUBIC=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_SCSI_MOD=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_SERIAL_CORE=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_UID16=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_VIDEO_DEV=y
+CONFIG_INPUT_LEDS=y
+CONFIG_HAS_DMA=y
+CONFIG_SCSI=y
+CONFIG_HID=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_JBD2=y
+CONFIG_PHYLIB=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_FB_CMDLINE=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_ARCH_SSTAR=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_IPC_NS=y
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_OF_GPIO=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_SSC007A_S01A=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_GRACE_PERIOD=m
+CONFIG_HAVE_SMP=y
+CONFIG_MS_SPINAND=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_EEPROM_AT24=m
+CONFIG_MTD_NAND=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_KERNFS=y
+CONFIG_MMC_BLOCK=y
+CONFIG_EXPERT=y
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_WIRELESS=y
+CONFIG_WEXT_PROC=y
+CONFIG_SQUASHFS=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_FRAME_VECTOR=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_FRAME_WARN=4096
+CONFIG_HID_GENERIC=y
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_CGROUPS=y
+CONFIG_MMC=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_HAVE_GCC_PLUGINS=y
+CONFIG_STACKTRACE=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_RTCPWC_INNER=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_ARCH_INFINITY2M=y
+CONFIG_HZ=100
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_MS_SERIAL=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_NLATTR=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_NR_CPUS=4
+CONFIG_HAVE_EXIT_THREAD=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_SYSFS=y
+CONFIG_USB_DEFAULT_PERSIST=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_ARM_THUMB=y
+CONFIG_CC_STACKPROTECTOR=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_FB=y
+CONFIG_CPU_32v7=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_CMA_SIZE_MBYTES=2
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_SMP_ON_UP=y
+CONFIG_RPS=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_IP_MULTICAST=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_CPU_32v6K=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_TICK_ONESHOT=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_MS_EMAC=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_OF_MDIO=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_NTFS_FS=m
+CONFIG_BASE_SMALL=1
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_COMPACTION=y
+CONFIG_NFS_V2=m
+CONFIG_ANALOG_PD_HDMI_ATOP=y
+CONFIG_PROC_FS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_VIDEOBUF2_VMALLOC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_FLATMEM=y
+CONFIG_SYSCTL=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_MS_BDMA=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_CIFS=m
+CONFIG_NET_NS=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_ATA_SFF=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_CMA_AREAS=1
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_MS_PADMUX=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_OF_FLATTREE=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_IRQCHIP=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_ELF_CORE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_CMA_DEBUG=y
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_SOC_BUS=y
+CONFIG_STAGING=y
+CONFIG_DMA_CMA=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_VT_CONSOLE=y
+CONFIG_LEDS_GPIO=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_PREEMPT=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_RTC_SYSTOHC=y
+CONFIG_OF_ADDRESS=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_CROSS_COMPILE=""
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_ATA_BMDMA=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_REGMAP=y
+CONFIG_NLS_UTF8=m
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_FB_NOTIFY=y
+CONFIG_NEW_LEDS=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_CMA=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_BITREVERSE=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_FILE_LOCKING=y
+CONFIG_AIO=y
+CONFIG_OF=y
+CONFIG_PERF_EVENTS=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_LEDS_CLASS=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_CMA_ALIGNMENT=4
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_UTS_NS=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MOUSE_PS2=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_INPUT=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_MMU=y
+CONFIG_DISABLE_CLK_DEBUGFS_SUPPORT=y
+CONFIG_KUSER_HELPERS=y