155 lines
6.7 KiB
VHDL
155 lines
6.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.zpu_soc_pkg.all;
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entity tranZPUter is
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port (
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-- Clock
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CLOCK_12M : in std_logic;
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-- LED
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LED : out std_logic_vector(7 downto 0);
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-- Debounced keys
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-- KEY : in std_logic_vector(1 downto 0);
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-- DIP switches
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-- SW : in std_logic_vector(3 downto 0);
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USER_BTN : in std_logic;
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-- TDI : in std_logic;
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-- TCK : in std_logic;
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-- TCS : in std_logic;
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-- TDO : out std_logic;
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-- I2C_SDAT : inout std_logic;
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-- I2C_SCLK : out std_logic;
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-- GPIO_0 : inout std_logic_vector(33 downto 0);
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-- GPIO_1 : inout std_logic_vector(33 downto 0);
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-- SD Card 1
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SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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UART_RX_0 : in std_logic;
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UART_TX_0 : out std_logic;
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UART_RX_1 : in std_logic;
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UART_TX_1 : out std_logic;
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-- SDRAM signals
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SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
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SDRAM_CKE : out std_logic; -- clock enable.
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SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
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SDRAM_ADDR : out std_logic_vector(11 downto 0); -- 13 bit multiplexed address bus
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SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
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SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
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SDRAM_CS : out std_logic; -- a single chip select
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SDRAM_WE : out std_logic; -- write enable
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SDRAM_RAS : out std_logic; -- row address select
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SDRAM_CAS : out std_logic; -- columns address select
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-- TCPU signals.
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CYC_D : out std_logic_vector(15 downto 0); -- Data bus
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CYC_CTL_SET_n : out std_logic; -- Set the transceiver control signals.
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CYC_CLK_n : in std_logic; -- Z80 Main Clock
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CYC_NMI_n : in std_logic; -- Z80 NMI converted to 3.3v
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CYC_INT_n : in std_logic; -- Z80 INT converted to 3.,3v
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CYC_WAIT_I_n : in std_logic; -- Z80 Wait converted to 3.3v.
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CYC_BUSACK_I_n : in std_logic; -- Z80 Bus Ack converted to 3.3v.
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CYC_BUSACK_n : out std_logic; -- CYC sending BUS ACK
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CYC_BUSRQ_n : out std_logic; -- CYC requesting Z80 bus.
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CYC_BUSRQ_I_n : in std_logic -- System requesting Z80 bus.
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);
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END entity;
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architecture rtl of tranZPUter is
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signal reset : std_logic;
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signal sysclk : std_logic;
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signal memclk : std_logic;
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signal pll_locked : std_logic;
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--signal ps2m_clk_in : std_logic;
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--signal ps2m_clk_out : std_logic;
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--signal ps2m_dat_in : std_logic;
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--signal ps2m_dat_out : std_logic;
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--signal ps2k_clk_in : std_logic;
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--signal ps2k_clk_out : std_logic;
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--signal ps2k_dat_in : std_logic;
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--signal ps2k_dat_out : std_logic;
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--alias PS2_MDAT : std_logic is GPIO_1(19);
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--alias PS2_MCLK : std_logic is GPIO_1(18);
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begin
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--I2C_SDAT <= 'Z';
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--GPIO_0(33 downto 2) <= (others => 'Z');
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--GPIO_1 <= (others => 'Z');
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--LED <= "101010" & reset & UART_RX_0;
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LED <= "10001000";
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mypll : entity work.Clock_12to100
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port map
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(
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inclk0 => CLOCK_12M,
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c0 => sysclk,
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c1 => memclk,
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locked => pll_locked
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);
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--reset<=(not SW(0) xor KEY(0)) and pll_locked;
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reset<=(not USER_BTN) and pll_locked;
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myVirtualToplevel : entity work.zpu_soc
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generic map
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(
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SYSCLK_FREQUENCY => SYSCLK_CYC1000_FREQ
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)
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port map
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(
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SYSCLK => sysclk,
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MEMCLK => memclk,
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RESET_IN => reset,
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-- RS232
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UART_RX_0 => UART_RX_0,
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UART_TX_0 => UART_TX_0,
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UART_RX_1 => UART_RX_1,
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UART_TX_1 => UART_TX_1,
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-- SD Card (SPI) signals
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SDCARD_MISO => SDCARD_MISO,
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SDCARD_MOSI => SDCARD_MOSI,
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SDCARD_CLK => SDCARD_CLK,
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SDCARD_CS => SDCARD_CS,
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-- SDRAM signals
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SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz
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SDRAM_CKE => SDRAM_CKE, -- clock enable.
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SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus
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SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus
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SDRAM_DQM => SDRAM_DQM, -- two byte masks
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SDRAM_BA => SDRAM_BA, -- two banks
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SDRAM_CS_n => SDRAM_CS, -- a single chip select
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SDRAM_WE_n => SDRAM_WE, -- write enable
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SDRAM_RAS_n => SDRAM_RAS, -- row address select
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SDRAM_CAS_n => SDRAM_CAS, -- columns address select
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SDRAM_READY => open, -- sd ready.
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-- TCPU Bus
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TCPU_DATA => CYC_D, -- Data bus
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TCPU_CTL_SET_n => CYC_CTL_SET_n, -- Set the transceiver control signals.
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TCPU_CLK_n => CYC_CLK_n, -- Z80 Main Clock
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TCPU_NMI_n => CYC_NMI_n, -- Z80 NMI converted to 3.3v
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TCPU_INT_n => CYC_INT_n, -- Z80 INT converted to 3.,3v
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TCPU_WAIT_I_n => CYC_WAIT_I_n, -- Z80 Wait converted to 3.3v.
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TCPU_BUSACK_I_n => CYC_BUSACK_I_n, -- Z80 Bus Ack converted to 3.3v.
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TCPU_BUSACK_n => CYC_BUSACK_n, -- CYC sending BUS ACK
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TCPU_BUSRQ_n => CYC_BUSRQ_n, -- CYC requesting Z80 bus.
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TCPU_BUSRQ_I_n => CYC_BUSRQ_I_n -- System requesting Z80 bus.
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);
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end architecture;
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