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Tranzputer updates and split of coreMZ in preparation for the SharpMZ Emulator being embedded

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This commit is contained in:
Philip Smart
2021-05-08 22:40:52 +01:00
parent 8ebdd783ef
commit 8401246d5c
22 changed files with 106729 additions and 104668 deletions
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8
FPGA/SW700/v1.3/build/coreMZ.qpf
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@@ -18,14 +18,18 @@
#
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 10:43:30 January 29, 2021
# Date created = 19:10:10 May 08, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.1"
DATE = "10:43:30 January 29, 2021"
DATE = "19:10:10 May 08, 2021"
# Revisions
PROJECT_REVISION = "coreMZ_SoftCPU"
PROJECT_REVISION = "coreMZ"
PROJECT_REVISION = "coreMZ_emuMZ"
PROJECT_REVISION = "coreMZ_E115"
PROJECT_REVISION = "coreMZ_E115_SoftCPU"
PROJECT_REVISION = "coreMZ_E115_emuMZ"

9
FPGA/SW700/v1.3/build/coreMZ.qsf
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@@ -260,23 +260,18 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_C
# Files in project.
# =================
set_global_assignment -name SEARCH_PATH ../AZ80
# Sharp MZ Core Logic
set_global_assignment -name QIP_FILE ../coreMZ.qip
# Altera Serial Flash Loader IP
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# Latest T80 CPU
# ==============
set_global_assignment -name QIP_FILE ../softT80.qip
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name QIP_FILE ../softZPU.qip
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

38
FPGA/SW700/v1.3/build/coreMZ_E115.qsf
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@@ -45,6 +45,8 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:26:39 JANUARY 29, 20
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
@@ -61,6 +63,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
@@ -76,7 +79,9 @@ set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
@@ -252,30 +257,21 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
# Files in project.
# =================
#set_global_assignment -name QIP_FILE Clock_50to100.qip
# Latest T80 CPU
# ==============
# Latest ZPU EVO CPU
# ==================
#set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
#set_global_assignment -name VHDL_FILE ../T80/T80a.vhd
set_global_assignment -name SEARCH_PATH ../AZ80
set_global_assignment -name VHDL_FILE ../coreMZ.vhd
set_global_assignment -name VHDL_FILE ../coreMZ_pkg.vhd
# Sharp MZ Core Logic
set_global_assignment -name QIP_FILE ../coreMZ.qip
# Altera Serial Flash Loader IP
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
set_global_assignment -name QIP_FILE ../PLL/Video_Clock_IV.qip
set_global_assignment -name SDC_FILE ../coreMZ_constraints.sdc
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# T80 CPU definitions.
# Latest T80 CPU
# ==============
set_global_assignment -name QIP_FILE ../softT80.qip
# ZPU Evo CPU definitions
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name QIP_FILE ../softZPU.qip
@@ -283,12 +279,4 @@ set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

283
FPGA/SW700/v1.3/build/coreMZ_E115_SoftCPU.qsf Normal file
View File

@@ -0,0 +1,283 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# coreMZ_E115_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name DEVICE EP4CE115F23I7
#set_global_assignment -name DEVICE EP4CE75F23I7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY coreMZ
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:26:39 JANUARY 29, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
# Clocks.
# =======
set_location_assignment PIN_T21 -to CLOCK_50
set_location_assignment PIN_T22 -to CLOCK_50_2
set_location_assignment PIN_T2 -to CTLCLK
set_location_assignment PIN_T1 -to SYSCLK
set_location_assignment PIN_U1 -to VZ80_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CTL_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SYS_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_CLK
# Video Interface/Soft CPU Address Bus
# ====================================
set_location_assignment PIN_AB10 -to VZ80_ADDR[15]
set_location_assignment PIN_AA10 -to VZ80_ADDR[14]
set_location_assignment PIN_AB9 -to VZ80_ADDR[13]
set_location_assignment PIN_AA9 -to VZ80_ADDR[12]
set_location_assignment PIN_AB8 -to VZ80_ADDR[11]
set_location_assignment PIN_AA8 -to VZ80_ADDR[10]
set_location_assignment PIN_AB7 -to VZ80_ADDR[9]
set_location_assignment PIN_AA7 -to VZ80_ADDR[8]
set_location_assignment PIN_AB6 -to VZ80_ADDR[7]
set_location_assignment PIN_AA6 -to VZ80_ADDR[6]
set_location_assignment PIN_AB5 -to VZ80_ADDR[5]
set_location_assignment PIN_AA5 -to VZ80_ADDR[4]
set_location_assignment PIN_AA4 -to VZ80_ADDR[3]
set_location_assignment PIN_AA1 -to VZ80_ADDR[2]
set_location_assignment PIN_Y2 -to VZ80_ADDR[1]
set_location_assignment PIN_Y1 -to VZ80_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[0]
# Video/Soft CPU Data Bus
# =======================
set_location_assignment PIN_AB16 -to VZ80_DATA[7]
set_location_assignment PIN_AA16 -to VZ80_DATA[6]
set_location_assignment PIN_AB15 -to VZ80_DATA[5]
set_location_assignment PIN_AA15 -to VZ80_DATA[4]
set_location_assignment PIN_AB14 -to VZ80_DATA[3]
set_location_assignment PIN_AA14 -to VZ80_DATA[2]
set_location_assignment PIN_AB13 -to VZ80_DATA[1]
set_location_assignment PIN_AA13 -to VZ80_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[0]
# Video/Soft CPU control signals.
# ===============================
set_location_assignment PIN_W1 -to VIDEO_RDn
set_location_assignment PIN_V1 -to VIDEO_WRn
set_location_assignment PIN_V2 -to VZ80_IORQn
set_location_assignment PIN_C1 -to VZ80_MREQn
set_location_assignment PIN_R2 -to VZ80_M1n
set_location_assignment PIN_F1 -to VZ80_RDn
set_location_assignment PIN_H1 -to VZ80_WRn
set_location_assignment PIN_J1 -to VZ80_BUSACKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_MREQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_M1n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSACKn
# Composite video multiplexed with Soft CPU input signals.
# ========================================================
set_location_assignment PIN_R1 -to VWAITn_A21_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_A20_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_A19_HALTn_V_VSYNCn
set_location_assignment PIN_N1 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_N2 -to VZ80_A16_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_A18_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_A17_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_A21_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A20_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A19_HALTn_V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSRn_V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A16_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A18_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A17_NMIn_V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
set_location_assignment PIN_A20 -to COLR_OUT
set_location_assignment PIN_A14 -to CSYNC_OUTn
set_location_assignment PIN_A13 -to CSYNC_OUT
set_location_assignment PIN_A9 -to VSYNC_OUTn
set_location_assignment PIN_A10 -to HSYNC_OUTn
set_location_assignment PIN_H22 -to VGA_R[0]
set_location_assignment PIN_J22 -to VGA_R[1]
set_location_assignment PIN_K22 -to VGA_R[2]
set_location_assignment PIN_L22 -to VGA_R[3]
set_location_assignment PIN_M22 -to VGA_R_COMPOSITE
set_location_assignment PIN_A15 -to VGA_G[0]
set_location_assignment PIN_A16 -to VGA_G[1]
set_location_assignment PIN_A17 -to VGA_G[2]
set_location_assignment PIN_A18 -to VGA_G[3]
set_location_assignment PIN_A19 -to VGA_G_COMPOSITE
set_location_assignment PIN_B22 -to VGA_B[0]
set_location_assignment PIN_C22 -to VGA_B[1]
set_location_assignment PIN_D22 -to VGA_B[2]
set_location_assignment PIN_E22 -to VGA_B[3]
set_location_assignment PIN_F22 -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to COLR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
# Files in project.
# =================
set_global_assignment -name SEARCH_PATH ../AZ80
# Sharp MZ Core Logic
set_global_assignment -name QIP_FILE ../coreMZ_SoftCPU.qip
# Altera Serial Flash Loader IP
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# Latest T80 CPU
# ==============
set_global_assignment -name QIP_FILE ../softT80.qip
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name QIP_FILE ../softZPU.qip
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

282
FPGA/SW700/v1.3/build/coreMZ_E115_emuMZ.qsf Normal file
View File

@@ -0,0 +1,282 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# coreMZ_E115_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name DEVICE EP4CE115F23I7
#set_global_assignment -name DEVICE EP4CE75F23I7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY coreMZ
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:26:39 JANUARY 29, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
# Clocks.
# =======
set_location_assignment PIN_T21 -to CLOCK_50
set_location_assignment PIN_T22 -to CLOCK_50_2
set_location_assignment PIN_T2 -to CTLCLK
set_location_assignment PIN_T1 -to SYSCLK
set_location_assignment PIN_U1 -to VZ80_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CTL_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SYS_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_CLK
# Video Interface/Soft CPU Address Bus
# ====================================
set_location_assignment PIN_AB10 -to VZ80_ADDR[15]
set_location_assignment PIN_AA10 -to VZ80_ADDR[14]
set_location_assignment PIN_AB9 -to VZ80_ADDR[13]
set_location_assignment PIN_AA9 -to VZ80_ADDR[12]
set_location_assignment PIN_AB8 -to VZ80_ADDR[11]
set_location_assignment PIN_AA8 -to VZ80_ADDR[10]
set_location_assignment PIN_AB7 -to VZ80_ADDR[9]
set_location_assignment PIN_AA7 -to VZ80_ADDR[8]
set_location_assignment PIN_AB6 -to VZ80_ADDR[7]
set_location_assignment PIN_AA6 -to VZ80_ADDR[6]
set_location_assignment PIN_AB5 -to VZ80_ADDR[5]
set_location_assignment PIN_AA5 -to VZ80_ADDR[4]
set_location_assignment PIN_AA4 -to VZ80_ADDR[3]
set_location_assignment PIN_AA1 -to VZ80_ADDR[2]
set_location_assignment PIN_Y2 -to VZ80_ADDR[1]
set_location_assignment PIN_Y1 -to VZ80_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[0]
# Video/Soft CPU Data Bus
# =======================
set_location_assignment PIN_AB16 -to VZ80_DATA[7]
set_location_assignment PIN_AA16 -to VZ80_DATA[6]
set_location_assignment PIN_AB15 -to VZ80_DATA[5]
set_location_assignment PIN_AA15 -to VZ80_DATA[4]
set_location_assignment PIN_AB14 -to VZ80_DATA[3]
set_location_assignment PIN_AA14 -to VZ80_DATA[2]
set_location_assignment PIN_AB13 -to VZ80_DATA[1]
set_location_assignment PIN_AA13 -to VZ80_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[0]
# Video/Soft CPU control signals.
# ===============================
set_location_assignment PIN_W1 -to VIDEO_RDn
set_location_assignment PIN_V1 -to VIDEO_WRn
set_location_assignment PIN_V2 -to VZ80_IORQn
set_location_assignment PIN_C1 -to VZ80_MREQn
set_location_assignment PIN_R2 -to VZ80_M1n
set_location_assignment PIN_F1 -to VZ80_RDn
set_location_assignment PIN_H1 -to VZ80_WRn
set_location_assignment PIN_J1 -to VZ80_BUSACKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_MREQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_M1n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSACKn
# Composite video multiplexed with Soft CPU input signals.
# ========================================================
set_location_assignment PIN_R1 -to VWAITn_A21_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_A20_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_A19_HALTn_V_VSYNCn
set_location_assignment PIN_N1 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_N2 -to VZ80_A16_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_A18_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_A17_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_A21_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A20_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A19_HALTn_V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSRn_V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A16_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A18_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A17_NMIn_V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
set_location_assignment PIN_A20 -to COLR_OUT
set_location_assignment PIN_A14 -to CSYNC_OUTn
set_location_assignment PIN_A13 -to CSYNC_OUT
set_location_assignment PIN_A9 -to VSYNC_OUTn
set_location_assignment PIN_A10 -to HSYNC_OUTn
set_location_assignment PIN_H22 -to VGA_R[0]
set_location_assignment PIN_J22 -to VGA_R[1]
set_location_assignment PIN_K22 -to VGA_R[2]
set_location_assignment PIN_L22 -to VGA_R[3]
set_location_assignment PIN_M22 -to VGA_R_COMPOSITE
set_location_assignment PIN_A15 -to VGA_G[0]
set_location_assignment PIN_A16 -to VGA_G[1]
set_location_assignment PIN_A17 -to VGA_G[2]
set_location_assignment PIN_A18 -to VGA_G[3]
set_location_assignment PIN_A19 -to VGA_G_COMPOSITE
set_location_assignment PIN_B22 -to VGA_B[0]
set_location_assignment PIN_C22 -to VGA_B[1]
set_location_assignment PIN_D22 -to VGA_B[2]
set_location_assignment PIN_E22 -to VGA_B[3]
set_location_assignment PIN_F22 -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to COLR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
# Files in project.
# =================
set_global_assignment -name SEARCH_PATH ../AZ80
# Sharp MZ Core Logic
set_global_assignment -name QIP_FILE ../coreMZ_emuMZ.qip
# Altera Serial Flash Loader IP
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# Latest T80 CPU
# ==============
set_global_assignment -name QIP_FILE ../softT80.qip
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name QIP_FILE ../softZPU.qip
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

283
FPGA/SW700/v1.3/build/coreMZ_SoftCPU.qsf Normal file
View File

@@ -0,0 +1,283 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# coreMZ_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
#set_global_assignment -name DEVICE EP4CE115F23I7
set_global_assignment -name DEVICE EP4CE75F23I7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY coreMZ
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
# Clocks.
# =======
set_location_assignment PIN_T21 -to CLOCK_50
set_location_assignment PIN_T22 -to CLOCK_50_2
set_location_assignment PIN_T2 -to CTLCLK
set_location_assignment PIN_T1 -to SYSCLK
set_location_assignment PIN_U1 -to VZ80_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CTL_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SYS_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_CLK
# Video Interface/Soft CPU Address Bus
# ====================================
set_location_assignment PIN_AB10 -to VZ80_ADDR[15]
set_location_assignment PIN_AA10 -to VZ80_ADDR[14]
set_location_assignment PIN_AB9 -to VZ80_ADDR[13]
set_location_assignment PIN_AA9 -to VZ80_ADDR[12]
set_location_assignment PIN_AB8 -to VZ80_ADDR[11]
set_location_assignment PIN_AA8 -to VZ80_ADDR[10]
set_location_assignment PIN_AB7 -to VZ80_ADDR[9]
set_location_assignment PIN_AA7 -to VZ80_ADDR[8]
set_location_assignment PIN_AB6 -to VZ80_ADDR[7]
set_location_assignment PIN_AA6 -to VZ80_ADDR[6]
set_location_assignment PIN_AB5 -to VZ80_ADDR[5]
set_location_assignment PIN_AA5 -to VZ80_ADDR[4]
set_location_assignment PIN_AA4 -to VZ80_ADDR[3]
set_location_assignment PIN_AA1 -to VZ80_ADDR[2]
set_location_assignment PIN_Y2 -to VZ80_ADDR[1]
set_location_assignment PIN_Y1 -to VZ80_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[0]
# Video/Soft CPU Data Bus
# =======================
set_location_assignment PIN_AB16 -to VZ80_DATA[7]
set_location_assignment PIN_AA16 -to VZ80_DATA[6]
set_location_assignment PIN_AB15 -to VZ80_DATA[5]
set_location_assignment PIN_AA15 -to VZ80_DATA[4]
set_location_assignment PIN_AB14 -to VZ80_DATA[3]
set_location_assignment PIN_AA14 -to VZ80_DATA[2]
set_location_assignment PIN_AB13 -to VZ80_DATA[1]
set_location_assignment PIN_AA13 -to VZ80_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[0]
# Video/Soft CPU control signals.
# ===============================
set_location_assignment PIN_W1 -to VIDEO_RDn
set_location_assignment PIN_V1 -to VIDEO_WRn
set_location_assignment PIN_V2 -to VZ80_IORQn
set_location_assignment PIN_C1 -to VZ80_MREQn
set_location_assignment PIN_R2 -to VZ80_M1n
set_location_assignment PIN_F1 -to VZ80_RDn
set_location_assignment PIN_H1 -to VZ80_WRn
set_location_assignment PIN_J1 -to VZ80_BUSACKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_MREQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_M1n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSACKn
# Composite video multiplexed with Soft CPU input signals.
# ========================================================
set_location_assignment PIN_R1 -to VWAITn_A21_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_A20_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_A19_HALTn_V_VSYNCn
set_location_assignment PIN_N1 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_N2 -to VZ80_A16_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_A18_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_A17_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_A21_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A20_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A19_HALTn_V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSRn_V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A16_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A18_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A17_NMIn_V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
set_location_assignment PIN_A20 -to COLR_OUT
set_location_assignment PIN_A14 -to CSYNC_OUTn
set_location_assignment PIN_A13 -to CSYNC_OUT
set_location_assignment PIN_A9 -to VSYNC_OUTn
set_location_assignment PIN_A10 -to HSYNC_OUTn
set_location_assignment PIN_H22 -to VGA_R[0]
set_location_assignment PIN_J22 -to VGA_R[1]
set_location_assignment PIN_K22 -to VGA_R[2]
set_location_assignment PIN_L22 -to VGA_R[3]
set_location_assignment PIN_M22 -to VGA_R_COMPOSITE
set_location_assignment PIN_A15 -to VGA_G[0]
set_location_assignment PIN_A16 -to VGA_G[1]
set_location_assignment PIN_A17 -to VGA_G[2]
set_location_assignment PIN_A18 -to VGA_G[3]
set_location_assignment PIN_A19 -to VGA_G_COMPOSITE
set_location_assignment PIN_B22 -to VGA_B[0]
set_location_assignment PIN_C22 -to VGA_B[1]
set_location_assignment PIN_D22 -to VGA_B[2]
set_location_assignment PIN_E22 -to VGA_B[3]
set_location_assignment PIN_F22 -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to COLR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
# Files in project.
# =================
set_global_assignment -name SEARCH_PATH ../AZ80
# Sharp MZ Core Logic
set_global_assignment -name QIP_FILE ../coreMZ_SoftCPU.qip
# Altera Serial Flash Loader IP
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# Latest T80 CPU
# ==============
set_global_assignment -name QIP_FILE ../softT80.qip
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name QIP_FILE ../softZPU.qip
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

282
FPGA/SW700/v1.3/build/coreMZ_emuMZ.qsf Normal file
View File

@@ -0,0 +1,282 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# coreMZ_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
#set_global_assignment -name DEVICE EP4CE115F23I7
set_global_assignment -name DEVICE EP4CE75F23I7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY coreMZ
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
# Clocks.
# =======
set_location_assignment PIN_T21 -to CLOCK_50
set_location_assignment PIN_T22 -to CLOCK_50_2
set_location_assignment PIN_T2 -to CTLCLK
set_location_assignment PIN_T1 -to SYSCLK
set_location_assignment PIN_U1 -to VZ80_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CTL_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SYS_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_CLK
# Video Interface/Soft CPU Address Bus
# ====================================
set_location_assignment PIN_AB10 -to VZ80_ADDR[15]
set_location_assignment PIN_AA10 -to VZ80_ADDR[14]
set_location_assignment PIN_AB9 -to VZ80_ADDR[13]
set_location_assignment PIN_AA9 -to VZ80_ADDR[12]
set_location_assignment PIN_AB8 -to VZ80_ADDR[11]
set_location_assignment PIN_AA8 -to VZ80_ADDR[10]
set_location_assignment PIN_AB7 -to VZ80_ADDR[9]
set_location_assignment PIN_AA7 -to VZ80_ADDR[8]
set_location_assignment PIN_AB6 -to VZ80_ADDR[7]
set_location_assignment PIN_AA6 -to VZ80_ADDR[6]
set_location_assignment PIN_AB5 -to VZ80_ADDR[5]
set_location_assignment PIN_AA5 -to VZ80_ADDR[4]
set_location_assignment PIN_AA4 -to VZ80_ADDR[3]
set_location_assignment PIN_AA1 -to VZ80_ADDR[2]
set_location_assignment PIN_Y2 -to VZ80_ADDR[1]
set_location_assignment PIN_Y1 -to VZ80_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_ADDR[0]
# Video/Soft CPU Data Bus
# =======================
set_location_assignment PIN_AB16 -to VZ80_DATA[7]
set_location_assignment PIN_AA16 -to VZ80_DATA[6]
set_location_assignment PIN_AB15 -to VZ80_DATA[5]
set_location_assignment PIN_AA15 -to VZ80_DATA[4]
set_location_assignment PIN_AB14 -to VZ80_DATA[3]
set_location_assignment PIN_AA14 -to VZ80_DATA[2]
set_location_assignment PIN_AB13 -to VZ80_DATA[1]
set_location_assignment PIN_AA13 -to VZ80_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_DATA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VZ80_DATA[0]
# Video/Soft CPU control signals.
# ===============================
set_location_assignment PIN_W1 -to VIDEO_RDn
set_location_assignment PIN_V1 -to VIDEO_WRn
set_location_assignment PIN_V2 -to VZ80_IORQn
set_location_assignment PIN_C1 -to VZ80_MREQn
set_location_assignment PIN_R2 -to VZ80_M1n
set_location_assignment PIN_F1 -to VZ80_RDn
set_location_assignment PIN_H1 -to VZ80_WRn
set_location_assignment PIN_J1 -to VZ80_BUSACKn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VIDEO_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_MREQn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_M1n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSACKn
# Composite video multiplexed with Soft CPU input signals.
# ========================================================
set_location_assignment PIN_R1 -to VWAITn_A21_V_CSYNC
set_location_assignment PIN_P1 -to VZ80_A20_RFSHn_V_HSYNCn
set_location_assignment PIN_P2 -to VZ80_A19_HALTn_V_VSYNCn
set_location_assignment PIN_N1 -to VZ80_BUSRQn_V_G
set_location_assignment PIN_N2 -to VZ80_A16_WAITn_V_B
set_location_assignment PIN_M1 -to VZ80_A18_INTn_V_R
set_location_assignment PIN_M2 -to VZ80_A17_NMIn_V_COLR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn_A21_V_CSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A20_RFSHn_V_HSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A19_HALTn_V_VSYNCn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_BUSRn_V_G
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A16_WAITn_V_B
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A18_INTn_V_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_A17_NMIn_V_COLR
# VGA/RGB/Composite video signals output.
# =======================================
set_location_assignment PIN_A20 -to COLR_OUT
set_location_assignment PIN_A14 -to CSYNC_OUTn
set_location_assignment PIN_A13 -to CSYNC_OUT
set_location_assignment PIN_A9 -to VSYNC_OUTn
set_location_assignment PIN_A10 -to HSYNC_OUTn
set_location_assignment PIN_H22 -to VGA_R[0]
set_location_assignment PIN_J22 -to VGA_R[1]
set_location_assignment PIN_K22 -to VGA_R[2]
set_location_assignment PIN_L22 -to VGA_R[3]
set_location_assignment PIN_M22 -to VGA_R_COMPOSITE
set_location_assignment PIN_A15 -to VGA_G[0]
set_location_assignment PIN_A16 -to VGA_G[1]
set_location_assignment PIN_A17 -to VGA_G[2]
set_location_assignment PIN_A18 -to VGA_G[3]
set_location_assignment PIN_A19 -to VGA_G_COMPOSITE
set_location_assignment PIN_B22 -to VGA_B[0]
set_location_assignment PIN_C22 -to VGA_B[1]
set_location_assignment PIN_D22 -to VGA_B[2]
set_location_assignment PIN_E22 -to VGA_B[3]
set_location_assignment PIN_F22 -to VGA_B_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to COLR_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CSYNC_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HSYNC_OUTn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G_COMPOSITE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to COLR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CSYNC_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HSYNC_OUTn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G_COMPOSITE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B_COMPOSITE
# Files in project.
# =================
set_global_assignment -name SEARCH_PATH ../AZ80
# Sharp MZ Core Logic
set_global_assignment -name QIP_FILE ../coreMZ_emuMZ.qip
# Altera Serial Flash Loader IP
set_global_assignment -name QIP_FILE ../SFL/SFL_IV.qip
#
set_global_assignment -name QIP_FILE ../VideoController.qip
# Latest T80 CPU
# ==============
set_global_assignment -name QIP_FILE ../softT80.qip
# Latest ZPU EVO CPU
# ==================
set_global_assignment -name QIP_FILE ../softZPU.qip
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY SKIP_REGENERATING_IP_IF_HDL_MODIFIED
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

1
FPGA/SW700/v1.3/coreMZ.qip
View File

@@ -1,3 +1,4 @@
set_parameter -name ADD_RTL 1 -to coreMZ
set_global_assignment -name IP_TOOL_NAME "Sharp MZ Core MZ Logic"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"

479
FPGA/SW700/v1.3/coreMZ.vhd
View File

@@ -10,7 +10,7 @@
-- to the pure FPGA tranZPUter v2.1 baord.
--
-- Credits:
-- Copyright: (c) 2018-20 Philip Smart <philip.smart@net2net.org>
-- Copyright: (c) 2018-21 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Oct 2020 - Split off from the Sharp MZ80A Video Module, the Video Module for the
@@ -25,6 +25,11 @@
-- Dec 2020 - ZPU Evo added into the framework.
-- Jan 2021 - Z80 (T80, AZ80, NextZ80) and ZPU Evolution processors added into the
-- framework.
-- May 2021 - Split into modules:
-- CoreMZ - Video Module only.
-- CoreMZ SoftCPU - Video Module and Soft CPUs (T80/ZPU).
-- CoreMZ emuMZ - Video Module and a port of the SharpMZ Series FPGA
-- emulator.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
@@ -98,8 +103,8 @@ END entity;
architecture rtl of coreMZ is
signal CPUCLK_75MHZ : std_logic;
signal PLL_LOCKED : std_logic;
--signal CPUCLK_75MHZ : std_logic;
signal PLL_LOCKED : std_logic := '0';
signal RESETn : std_logic := '0';
signal RESET_COUNTER : unsigned(3 downto 0) := (others => '1');
signal CTRLREG_RESET : std_logic := '1'; -- Flag to indicate when a hard reset occurs so that registers can be preloaded based on conditions.
@@ -108,53 +113,13 @@ architecture rtl of coreMZ is
signal CPU_INFO_DATA : std_logic_vector(7 downto 0); -- CPU configuration information register.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPLD configuration register.
signal MODE_CPU_SOFT : std_logic; -- Control signal to enable the Soft CPU and support logic.
signal MODE_SOFTCPU_RESET : std_logic; -- Software controlled reset signal to reset a soft cpu.
signal MODE_SOFTCPU_CLKEN : std_logic; -- Enable the soft cpu clock (1).
signal MODE_CPLD_MB_VIDEOn : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the mainboard video logic is enabled, disabling or blending with the FPGA graphics.
signal MODE_SOFTCPU_Z80 : std_logic; -- Flag to indicate the Z80 module is available and active.
signal MODE_SOFTCPU_ZPUEVO : std_logic; -- Flag to indicate the ZPU Evo module is available and active.
signal CS_IO_6XXn : std_logic; -- Chip select for CPLD configuration registers.
signal CS_CPU_CFGn : std_logic; -- Select to set the CPU configuration register.
signal CS_CPU_INFOn : std_logic; -- Select to read the CPU information register.
signal CS_CPLD_CFGn : std_logic; -- Chip Select to write to the CPLD configuration register at 0x6E.
signal VZ80_HI_ADDR : std_logic_vector(23 downto 16); -- Upper address bits (to 16M) are multiplexed and only available during external access of the FPGA resources.
signal VZ80_BUSACKni : std_logic; -- Internal combination of BUSACK signals.
signal COLOUR_CARRIER_FREQ : std_logic; -- Modulator colour carrier frequency output by video module.
-- T80 - General identifier for Z80 based Soft CPU's, the T80 being the primary but also AZ80 and NextZ80 are available via config flag.
--
signal T80_MREQn : std_logic;
signal T80_IORQn : std_logic;
signal T80_WRn : std_logic;
signal T80_RDn : std_logic;
signal T80_M1n : std_logic;
signal T80_RFSHn : std_logic;
signal T80_ADDR : std_logic_vector(15 downto 0);
signal T80_DATA_OUT : std_logic_vector(7 downto 0);
signal T80_BUSACKn : std_logic;
signal T80_HALTn : std_logic;
-- ZPU
signal ZPU80_MREQn : std_logic;
signal ZPU80_IORQn : std_logic;
signal ZPU80_WRn : std_logic;
signal ZPU80_RDn : std_logic;
signal ZPU80_M1n : std_logic;
signal ZPU80_RFSHn : std_logic;
signal ZPU80_ADDR : std_logic_vector(15 downto 0);
signal ZPU80_VIDEO_ADDR : std_logic_vector(7 downto 0);
signal ZPU80_DATA_OUT : std_logic_vector(7 downto 0);
signal ZPU80_HALTn : std_logic;
signal ZPU_DATA_OUT : std_logic_vector(31 downto 0); -- External RAM block data to write to RAM.
signal ZPU_WRITE_EN : std_logic; -- Write to external RAM.
signal ZPU_MEM_BUSACK : std_logic; -- Memory bus acknowledge signal.
signal ZPU_VIDEO_ADDR : std_logic_vector(23 downto 0); -- Dedicated video address, bypasses the CPLD.
signal ZPU_VIDEO_DATA_IN : std_logic_vector(31 downto 0); -- Video controller to ZPU data in.
signal ZPU_VIDEO_DATA_OUT : std_logic_vector(31 downto 0); -- ZPU to Video controller data out.
signal ZPU_VIDEO_WRn : std_logic; -- Dedicated video channel write signal, bypasses the CPLD.
signal ZPU_VIDEO_RDn : std_logic; -- Dedicated video channel read signal, bypasses the CPLD.
signal ZPU_VIDEO_WR_BYTE : std_logic; -- Dedicated video channel 8bit byte write identifier signal, bypasses the CPLD.
signal ZPU_VIDEO_WR_HWORD : std_logic; -- Dedicated video channel 16bit half word write identifier signal, bypasses the CPLD.
-- Internal core signals, muxed or demuxed physical connections.
--
@@ -182,14 +147,14 @@ begin
-- Instantiate a PLL to generate the clocks required by soft processors.
--
COREMZPLL1 : entity work.Video_Clock_IV
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => CPUCLK_75MHZ,
locked => PLL_LOCKED
);
--COREMZPLL1 : entity work.Video_Clock_IV
--port map
--(
-- inclk0 => CLOCK_50,
-- areset => '0',
-- c0 => CPUCLK_75MHZ,
-- locked => PLL_LOCKED
--);
------------------------------------------------------------------------------------
-- Serial Flash Loader for updating the EPCS64 via Altera Quartus.
@@ -215,6 +180,7 @@ begin
FPGARESET: process(CLOCK_50, PLL_LOCKED)
begin
if PLL_LOCKED = '0' then
PLL_LOCKED <= '1';
RESET_COUNTER <= (others => '1');
RESETn <= '0';
@@ -272,7 +238,7 @@ begin
VGA_B_COMPOSITE => VGA_B_COMPOSITE, -- RGB Blue override for composite output.
HSYNC_OUTn => HSYNC_OUTn, -- Horizontal sync.
VSYNC_OUTn => VSYNC_OUTn, -- Vertical sync.
COLR_OUT => COLOUR_CARRIER_FREQ, -- Composite colour and RF base frequency.
COLR_OUT => COLR_OUT, -- Composite colour and RF base frequency.
CSYNC_OUTn => CSYNC_OUTn, -- Composite sync (negative).
CSYNC_OUT => CSYNC_OUT, -- Composite sync (positive).
@@ -290,194 +256,6 @@ begin
MB_VIDEO_ENABLEn => MODE_CPLD_MB_VIDEOn -- Mainboard video enabled (=0) or FPGA advanced video (=1).
);
------------------------------------------------------------------------------------
-- T80 CPU
------------------------------------------------------------------------------------
CPU0: if IMPL_SOFTCPU_Z80 = true generate
signal T80_INTn : std_logic;
signal T80_NMIn : std_logic;
signal T80_BUSRQn : std_logic;
signal T80_WAITn : std_logic;
signal T80_DATA_IN : std_logic_vector(7 downto 0);
begin
T80CPU : entity work.softT80
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
SYS_CLK => CLOCK_50, -- System logic clock ~50MHz
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => MODE_SOFTCPU_RESET, -- Software controlled reset.
SW_CLKEN => MODE_SOFTCPU_CLKEN, -- Software controlled clock enable.
SW_CPUEN => MODE_SOFTCPU_Z80, -- Software controlled CPU enable.
-- Core Sharp MZ signals.
T80_WAITn => T80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
T80_INTn => T80_INTn, -- INTn signal for maskable interrupts.
T80_NMIn => T80_NMIn, -- NMIn non maskable interrupt input.
T80_BUSRQn => T80_BUSRQn, -- BUSRQn signal to request CPU go into tristate and relinquish bus.
T80_M1n => T80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
T80_MREQn => T80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
T80_IORQn => T80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
T80_RDn => T80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
T80_WRn => T80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
T80_RFSHn => T80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
T80_HALTn => T80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
T80_BUSACKn => T80_BUSACKn, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
T80_ADDR => T80_ADDR, -- 16 bit address lines.
T80_DATA_IN => T80_DATA_IN, -- 8 bit data bus in.
T80_DATA_OUT => T80_DATA_OUT -- 8 bit data bus out.
);
-- Soft CPU data input. Read directly from the Video Controller if selected, at all other times read from the CPLD which in turn reads from the tranZPUter or mainboard.
T80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT(7 downto 0) when CORE_VIDEO_RDn = '0'
else
VZ80_DATA when MODE_SOFTCPU_Z80 = '1' and T80_RDn = '0'
else (others => '0');
-- Direct routed signals to the T80 when not using mainboard video.
T80_INTn <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
T80_NMIn <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
T80_BUSRQn <= VZ80_BUSRQn when MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_WAITn <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
else generate
T80_WRn <= '1';
T80_RDn <= '1';
T80_M1n <= '1';
T80_HALTn <= '1';
T80_MREQn <= '1';
T80_IORQn <= '1';
T80_BUSACKn <= '1';
T80_ADDR <= (others => 'X');
T80_DATA_OUT <= (others => 'X');
end generate;
------------------------------------------------------------------------------------
-- ZPU Evolution CPU
------------------------------------------------------------------------------------
CPU1: if IMPL_SOFTCPU_ZPUEVO = true generate
signal ZPU80_INTn : std_logic;
signal ZPU80_NMIn : std_logic;
signal ZPU80_WAITn : std_logic;
signal ZPU80_DATA_IN : std_logic_vector(7 downto 0);
signal ZPU_MEM_BUSRQ : std_logic; -- Memory bus request signal.
begin
ZPUCPU : entity work.softZPU
generic map (
SYSCLK_FREQUENCY => 75000000 -- Speed of clock used for the ZPU.
)
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
ZPU_CLK => CPUCLK_75MHZ, -- ZPU clock.
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => MODE_SOFTCPU_RESET, -- Software controlled reset.
SW_CLKEN => MODE_SOFTCPU_CLKEN, -- Software controlled clock enable.
SW_CPUEN => MODE_SOFTCPU_ZPUEVO, -- Software controlled CPU enable.
-- Direct access to the video controller, bypassing the CPLD Memory management.
VIDEO_ADDR => ZPU_VIDEO_ADDR, -- Direct video controller addressing, bypass CPLD memory manager and operate at 32bits.
VIDEO_DATA_IN => ZPU_VIDEO_DATA_IN, -- Video controller to ZPU data in.
VIDEO_DATA_OUT => ZPU_VIDEO_DATA_OUT, -- ZPU to Video controller data out.
VIDEO_WRn => ZPU_VIDEO_WRn, -- Direct video write from ZPU, bypass CPLD memory manager.
VIDEO_RDn => ZPU_VIDEO_RDn, -- Direct video read from ZPU, bypass CPLD memory manager.
VIDEO_WR_BYTE => ZPU_VIDEO_WR_BYTE, -- Direct video write byte signal, when set a byte should be written.
VIDEO_WR_HWORD => ZPU_VIDEO_WR_HWORD, -- Direct video write byte signal, when set a 16bit half word should be written.
-- External Direct addressing Bus. Ability to read and write to the internal ZPU memory for uploading new programs/debugging.
-- When BUSRQ is asserted, the external system can drive the signals to query memory.
-- A23 -A16
-- 00000000 - Normal Sharp MZ behaviour
-- 00001XXX - Video Controller
-- 00010000 ->
-- 00011000 - ZPU 128K Block. Boot and stack memory.
-- Access to internal BRAM access signals, become active when bus granted.
INT_MEM_DATA_IN => X"000000" & VZ80_DATA(7 downto 0), -- Internal RAM block data to write to RAM.
INT_MEM_DATA_OUT => ZPU_DATA_OUT, -- Internal RAM block data read from RAM.
INT_MEM_ADDR => VZ80_HI_ADDR & VZ80_ADDR, -- 24bit address bus to address RAM.
INT_MEM_WRITE_EN => not VZ80_WRn, -- Write to internal RAM.
INT_MEM_WRITE_BYTE_EN => '1', -- Write is 1 byte wide.
INT_MEM_WRITE_HWORD_EN => '0', -- Write is 1 half word wide.
-- Bus request/ack mechanism.
MEM_BUSRQ => ZPU_MEM_BUSRQ, -- Bus request signal. Set to 1 when external control is needed of the memory bus.
MEM_BUSACK => ZPU_MEM_BUSACK, -- Bus acknowledge signal, set to 1 when control of the bus is granted.
-- Core Sharp MZ signals.
ZPU80_WAITn => ZPU80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
ZPU80_INTn => ZPU80_INTn, -- INTn signal for maskable interrupts.
ZPU80_NMIn => ZPU80_NMIn, -- NMIn non maskable interrupt input.
ZPU80_BUSRQn => '1', -- BUSRQn signal to request CPU go into tristate and relinquish bus. Not used in this design
ZPU80_M1n => ZPU80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
ZPU80_MREQn => ZPU80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
ZPU80_IORQn => ZPU80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
ZPU80_RDn => ZPU80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
ZPU80_WRn => ZPU80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
ZPU80_RFSHn => ZPU80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
ZPU80_HALTn => ZPU80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
ZPU80_BUSACKn => open, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
ZPU80_ADDR => ZPU80_ADDR, -- 16 bit address lines.
ZPU80_DATA_IN => ZPU80_DATA_IN, -- 8 bit data bus in.
ZPU80_DATA_OUT => ZPU80_DATA_OUT, -- 8 bit data bus out.
-- Debug.
DEBUG_TXD_IN => COLOUR_CARRIER_FREQ, -- Serial debug loop, used as output when debug not enabled.
DEBUG_TXD_OUT => COLR_OUT -- Debug serial output when debug enabled. / DEBUG_TXD_IN when debug disabled.
);
-- Direct routed signals to the ZPU when not using mainboard video.
ZPU_VIDEO_DATA_IN <= CORE_DATA_OUT;
ZPU80_INTn <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_NMIn <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_WAITn <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and ZPU80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and ZPU80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT(7 downto 0) when CORE_VIDEO_RDn = '0'
else
VZ80_DATA when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_RDn = '0'
else (others => '0');
ZPU_MEM_BUSRQ <= '1' when VZ80_BUSRQn = '0' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1') -- Incoming BUSRQ from the K64F requests the ZPU Bus as well.
else '0';
else generate
ZPU80_M1n <= '1';
ZPU80_MREQn <= '1';
ZPU80_IORQn <= '1';
ZPU80_RDn <= '1';
ZPU80_WRn <= '1';
ZPU80_RFSHn <= '1';
ZPU80_HALTn <= '1';
ZPU80_ADDR <= (others => '0');
ZPU80_DATA_OUT <= (others => '0');
ZPU_WRITE_EN <= '0';
ZPU_MEM_BUSACK <= '0';
ZPU_VIDEO_WRn <= '1';
ZPU_VIDEO_RDn <= '1';
end generate;
------------------------------------------------------------------------------------
-- Core Logic
@@ -487,14 +265,11 @@ begin
--
--
CTRLREGISTERS: process( RESETn, CLOCK_50, VZ80_CLK, CS_CPU_CFGn, CS_CPLD_CFGn, VZ80_WRn, VZ80_RDn )
variable SOFT_RESET_COUNTER : unsigned(3 downto 0); -- Down counter to set reset pulse width.
begin
-- Ensure default values at reset.
if RESETn='0' then
CTRLREG_RESET <= '1';
CPU_CFG_DATA(7 downto 6) <= "01"; -- Dont reset soft CPU selection flag on a reset.
MODE_SOFTCPU_RESET <= '0';
SOFT_RESET_COUNTER := (others => '0');
VZ80_CLK_LAST <= (others => '0');
elsif rising_edge(CLOCK_50) then
@@ -555,54 +330,19 @@ begin
--
if(CS_CPU_CFGn = '0' and VZ80_WRn = '0') then
-- Store the new value into the register, used for read operations.
CPU_CFG_DATA <= VZ80_DATA;
-- Check to ensure only one CPU selected, if more than one default to hard CPU. Also check to ensure only instantiated CPU's selected, otherwise default to hard CPU.
--
if (unsigned(VZ80_DATA(5 downto 0)) and (unsigned(VZ80_DATA(5 downto 0))-1)) /= 0 or (VZ80_DATA(5 downto 2) and "1111") /= "0000" or (IMPL_SOFTCPU_Z80 = false and VZ80_DATA(0) = '1') or (IMPL_SOFTCPU_ZPUEVO = false and VZ80_DATA(1) = '1') then
CPU_CFG_DATA(5 downto 0) <= (others => '0');
end if;
-- Soft CPU's are not implemented.
CPU_CFG_DATA <= (others => '0');
elsif(CS_CPLD_CFGn = '0' and VZ80_WRn = '0') then
-- Store the new value into the register, used for read operations.
CPLD_CFG_DATA <= VZ80_DATA;
end if;
-- Soft reset mechanism. If the reset flag was set on the previous cycle, toggle reset active and start a down counter. On zero, toggle reset to inactive.
if CPU_CFG_DATA(7) = '1' then
MODE_SOFTCPU_RESET <= '1';
SOFT_RESET_COUNTER := (others => '1');
CPU_CFG_DATA(7) <= '0';
end if;
if SOFT_RESET_COUNTER /= 0 then
SOFT_RESET_COUNTER := SOFT_RESET_COUNTER - 1;
else
MODE_SOFTCPU_RESET <= '0';
end if;
end if;
end if;
end process;
-- Mode flags to indicate a CPU is available and selected.
MODEZ80: if IMPL_SOFTCPU_Z80 = true generate
MODE_SOFTCPU_Z80 <= '1' when CPU_CFG_DATA(0) = '1'
else '0';
else generate
MODE_SOFTCPU_Z80 <= '0';
end generate;
MODEEVO: if IMPL_SOFTCPU_ZPUEVO = true generate
MODE_SOFTCPU_ZPUEVO <= '1' when CPU_CFG_DATA(1) = '1'
else '0';
else generate
MODE_SOFTCPU_ZPUEVO <= '0';
end generate;
--
MODE_SOFTCPU_CLKEN <= CPU_CFG_DATA(6);
-- CPU information register.
-- CPU information register. Not implemented in this module.
-- [5:0] - R/O - CPU Availability.
-- 000000 = Hard CPU
-- 000001 = T80 CPU
@@ -613,13 +353,7 @@ begin
-- 100000 = Future CPU AAA
-- [7:6] - R/O - Soft CPU capable, 01 = capable, /01 = not capable (value to cater for non-FPGA reads which return 11 or 00).
--
CPU_INFO_DATA <= "01000001" when IMPL_SOFTCPU_Z80 = true and IMPL_SOFTCPU_ZPUEVO = false
else
"01000010" when IMPL_SOFTCPU_Z80 = false and IMPL_SOFTCPU_ZPUEVO = true
else
"01000011" when IMPL_SOFTCPU_Z80 = true and IMPL_SOFTCPU_ZPUEVO = true
else
"00000000";
CPU_INFO_DATA <= "00000000";
-- CPLD configuration register range.
CS_IO_6XXn <= '0' when CORE_IORQn = '0' and CORE_ADDR(7 downto 4) = "0110"
@@ -635,95 +369,40 @@ begin
CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and CORE_ADDR(3 downto 0) = "1110" -- IO 6E - CPLD configuration register.
else '1';
-- Set the mainboard video state, 0 = enabled, 1 = disabled. Signal set to enabled if the soft cpu is enabled.
MODE_CPLD_MB_VIDEOn <= '1' when CPLD_CFG_DATA(3) = '1' or CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Flag to indicate Soft CPU is running,
MODE_CPU_SOFT <= '1' when CPU_CFG_DATA(5 downto 0) /= "000000"
-- Set the mainboard video state, 0 = enabled, 1 = disabled.
MODE_CPLD_MB_VIDEOn <= '1' when CPLD_CFG_DATA(3) = '1'
else '0';
-- Mux the main Z80 control signals for internal use, either use the hard Z80 on the tranZPUter or the soft CPU in the FPGA.
--
CORE_MREQn <= VZ80_MREQn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_MREQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_MREQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_IORQn <= VZ80_IORQn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_IORQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_IORQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_RDn <= VZ80_RDn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_RDn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_WRn <= VZ80_WRn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_WRn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_M1n <= VZ80_M1n when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_M1n when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_M1n when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_RFSHn <= T80_RFSHn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RFSHn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_HALTn <= T80_HALTn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_HALTn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_VIDEO_WRn <= '0' when VZ80_BUSACKni = '0' and VZ80_WRn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
ZPU_VIDEO_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
CORE_MREQn <= VZ80_MREQn;
CORE_IORQn <= VZ80_IORQn;
CORE_RDn <= VZ80_RDn;
CORE_WRn <= VZ80_WRn;
CORE_M1n <= VZ80_M1n;
CORE_RFSHn <= '1';
CORE_HALTn <= '1';
CORE_VIDEO_WRn <= '0' when VZ80_WRn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
VIDEO_WRn;
CORE_VIDEO_RDn <= '0' when VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
ZPU_VIDEO_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
CORE_VIDEO_RDn <= '0' when VZ80_RDn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
VIDEO_RDn;
-- 32/16/8 bit write select. When the ZPU is writing, the signals are active and controlled by the ZPU, otherwise default to 1 byte writes.
CORE_VIDEO_WR_BYTE <= '1' when ZPU_VIDEO_WRn = '1'
else
ZPU_VIDEO_WR_BYTE;
CORE_VIDEO_WR_HWORD <= '0' when ZPU_VIDEO_WRn = '1'
else
ZPU_VIDEO_WR_HWORD;
CORE_VIDEO_WR_BYTE <= '1';
CORE_VIDEO_WR_HWORD <= '0';
-- Internal reset dependent on external reset or a change of the SOFT CPU.
CORE_RESETn <= '0' when RESETn = '0'
else '1';
-- Address lines driven according to the CPU being used. Hard CPU = address via CPLD, Soft CPU = address direct.
CORE_ADDR <= X"00" & T80_ADDR when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
CORE_ADDR <= VZ80_HI_ADDR & VZ80_ADDR when VZ80_BUSACKni = '0'
else
ZPU_VIDEO_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and (ZPU_VIDEO_WRn = '0' or ZPU_VIDEO_RDn = '0')
else
X"00" & ZPU80_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and ZPU_VIDEO_WRn = '1' and ZPU_VIDEO_RDn = '1'
else
VZ80_HI_ADDR & VZ80_ADDR when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else (others => '0');
"00000000" & VZ80_ADDR;
-- Data into the core, generally the Video Controller, comes from the CPLD (hard CPU or mainboard) if the soft CPU is disabled else from the soft CPU.
CORE_DATA_IN <= X"000000" & T80_DATA_OUT when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_VIDEO_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and (ZPU_VIDEO_WRn = '0' or ZPU_VIDEO_RDn = '0')
else
X"000000" & ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and ZPU_VIDEO_WRn = '1' and ZPU_VIDEO_RDn = '1'
else
X"000000" & VZ80_DATA when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else (others => '0');
CORE_DATA_IN <= X"000000" & VZ80_DATA;
-- tranZPUter, hard CPU or mainboard data input. Read directly from the Video Controller if selected, else the data being output from the soft CPU if enabled otherwise
-- tri-state as data is coming from the CPLD.
@@ -732,79 +411,29 @@ begin
CPU_INFO_DATA when CS_CPU_INFOn = '0' and VZ80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT (7 downto 0) when CORE_VIDEO_RDn = '0' -- If the video resources are being read, either by the hard cpu or the K64f, output requested data.
else
T80_DATA_OUT when MODE_SOFTCPU_Z80 = '1' and T80_WRn = '0' and VZ80_BUSACKni = '1' -- T80 has control over writing data when enabled and bus not requested.
else
ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_WRn = '0' and VZ80_BUSACKni = '1' -- ZPU Evo Z80 Bus controller has control over writing data when enabled and bus not requested.
else
ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_MREQn = '0' and ZPU80_IORQn = '0' and VZ80_BUSACKni = '1' -- ZPU has control when writing special control word to CPLD to enable memory mode.
-- When bus requested, K64F has control, reading data from the ZPU BRAM if selected.
else
ZPU_DATA_OUT(7 downto 0) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "11"
else
ZPU_DATA_OUT(15 downto 8) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "10"
else
ZPU_DATA_OUT(23 downto 16) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "01"
else
ZPU_DATA_OUT(31 downto 24) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "00"
else (others => 'Z');
-- Direct routed signals to the ZPU when not using mainboard video.
VZ80_HI_ADDR(16) <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(17) <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(18) <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(19) <= VZ80_A19_HALTn_V_VSYNCn when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(20) <= VZ80_A20_RFSHn_V_HSYNCn when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(21) <= VWAITn_A21_V_CSYNC when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(16) <= VZ80_A16_WAITn_V_B;
VZ80_HI_ADDR(17) <= VZ80_A17_NMIn_V_COLR;
VZ80_HI_ADDR(18) <= VZ80_A18_INTn_V_R;
VZ80_HI_ADDR(19) <= VZ80_A19_HALTn_V_VSYNCn;
VZ80_HI_ADDR(20) <= VZ80_A20_RFSHn_V_HSYNCn;
VZ80_HI_ADDR(21) <= VWAITn_A21_V_CSYNC;
VZ80_HI_ADDR(22) <= '0';
VZ80_HI_ADDR(23) <= '0';
-- Tri-state controls. If the hard Z80 is being used then tri-state output signals.
VZ80_MREQn <= T80_MREQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1' -- When the T80 is selected and not under K64F control, drive the MREQ line output by the T80.
else
ZPU80_MREQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' -- When the ZPU Evo is selected and not under K64F control, drive the MREQ line output by the T80.
else 'Z';
VZ80_IORQn <= T80_IORQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_IORQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_RDn <= T80_RDn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_WRn <= T80_WRn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_M1n <= T80_M1n when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_M1n when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_A20_RFSHn_V_HSYNCn<=T80_RFSHn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RFSHn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_A19_HALTn_V_VSYNCn<=T80_HALTn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_HALTn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_ADDR <= T80_ADDR when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else (others => 'Z');
VZ80_BUSACKni <= '0' when MODE_CPU_SOFT = '0' and VZ80_BUSRQn = '0' and MODE_CPLD_MB_VIDEOn = '1' -- When soft CPU's are disabled, generate a BUSACK when FPGA video is enabled and BUSRQ is asserted.
else
'0' when MODE_SOFTCPU_Z80 = '1' and T80_BUSACKn = '0'
else
'0' when MODE_SOFTCPU_ZPUEVO = '1' and ZPU_MEM_BUSACK = '1' -- The ZPU has priority, when it acknowledges then the Z80 BUS is already idle.
else '1';
VZ80_BUSRQn <= VZ80_BUSRQn_V_G when MODE_CPU_SOFT = '1' or MODE_CPLD_MB_VIDEOn = '1' -- Just a wire, demux of the VZ80_BUSRQn_V_G signal.
VZ80_MREQn <= 'Z';
VZ80_IORQn <= 'Z';
VZ80_RDn <= 'Z';
VZ80_WRn <= 'Z';
VZ80_M1n <= 'Z';
VZ80_A20_RFSHn_V_HSYNCn<= 'Z';
VZ80_A19_HALTn_V_VSYNCn<= 'Z';
VZ80_ADDR <= (others => 'Z');
VZ80_BUSACKni <= VZ80_BUSRQn;
VZ80_BUSRQn <= VZ80_BUSRQn_V_G when MODE_CPLD_MB_VIDEOn = '1'
else '1';
VZ80_BUSACKn <= VZ80_BUSACKni;

7
FPGA/SW700/v1.3/coreMZ_SoftCPU.qip Normal file
View File

@@ -0,0 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "Sharp MZ700 + Soft CPU Core Logic"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) coreMZ_pkg.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) coreMZ_SoftCPU.vhd]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) coreMZ_SoftCPU_constraints.sdc]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) PLL/Video_Clock_IV.qip]

816
FPGA/SW700/v1.3/coreMZ_SoftCPU.vhd Normal file
View File

@@ -0,0 +1,816 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: coreMZ_SoftCPU.vhd
-- Created: June 2020
-- Author(s): Philip Smart
-- Description: Sharp MZ Series FPGA core.
--
-- This module provides a Sharp MZ series computer with Video and Soft CPU enhancements.
-- Initially written for the Sharp MZ-700 on the SW700 v1.3 board and will be migrated
-- to the pure FPGA tranZPUter v2.1 baord.
--
-- Credits:
-- Copyright: (c) 2018-21 Philip Smart <philip.smart@net2net.org>
--
-- History: June 2020 - Initial creation.
-- Oct 2020 - Split off from the Sharp MZ80A Video Module, the Video Module for the
-- Sharp MZ700 has the same roots but different control functionality. The
-- MZ700 version resides within the tranZPUter memory and not the mainboard
-- allowing for generally easier control. The MZ80A and MZ700 graphics logic
-- should be pretty much identical.
-- Nov 2020 - Split off from v1.2 VideoController700 module. With the advent of v1.3
-- with it's much larger FPGA, it is now possible to add Soft CPU's in
-- addition to the Video Controller logic. This required a restructuring
-- of the VHDL to seperate the Video from the Soft CPUs.
-- Dec 2020 - ZPU Evo added into the framework.
-- Jan 2021 - Z80 (T80, AZ80, NextZ80) and ZPU Evolution processors added into the
-- framework.
-- May 2021 - Split into modules:
-- CoreMZ - Video Module only.
-- CoreMZ SoftCPU - Video Module and Soft CPUs (T80/ZPU).
-- CoreMZ emuMZ - Video Module and a port of the SharpMZ Series FPGA
-- emulator.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.coreMZ_pkg.all;
use altera.altera_syn_attributes.all;
entity coreMZ is
port (
-- Primary and video clocks.
CLOCK_50 : in std_logic; -- 50MHz base clock for video timing and gate clocking.
CTLCLK : in std_logic; -- tranZPUter external clock (for overclocking).
SYSCLK : in std_logic; -- Mainboard system clock.
VZ80_CLK : in std_logic; -- Z80 clock combining SYSCLK and CTLCLK.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Address Bus
VZ80_ADDR : inout std_logic_vector(15 downto 0); -- Z80 Address bus.
-- Data Bus
VZ80_DATA : inout std_logic_vector(7 downto 0); -- Z80 Data bus.
-- Control signals.
VZ80_MREQn : inout std_logic; -- Z80 MREQ Out from Soft CPU.
VZ80_IORQn : inout std_logic; -- Z80 IORQ In from Hard Z80/Out from Soft CPU.
VZ80_RDn : inout std_logic; -- Z80 RDn In from Hard Z80/Out from Soft CPU.
VZ80_WRn : inout std_logic; -- Z80 WRn In from Hard Z80/Out from Soft CPU.
VZ80_M1n : inout std_logic; -- Z80 M1 Out from Soft CPU.
VZ80_BUSACKn : out std_logic; -- Z80 BUSACK Out from Soft CPU.
VIDEO_RDn : in std_logic; -- Decoded Video Controller Read from CPLD memory manager.
VIDEO_WRn : in std_logic; -- Decoded Video Controller Write from CPLD memory manager.
-- VGA & Composite output signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
VGA_G : out std_logic_vector(3 downto 0); -- 16 level Green output.
VGA_B : out std_logic_vector(3 downto 0); -- 16 level Blue output.
VGA_R_COMPOSITE : inout std_logic; -- RGB Red override for composite output.
VGA_G_COMPOSITE : inout std_logic; -- RGB Green override for composite output.
VGA_B_COMPOSITE : inout std_logic; -- RGB Blue override for composite output.
HSYNC_OUTn : out std_logic; -- Horizontal sync.
VSYNC_OUTn : out std_logic; -- Vertical sync.
COLR_OUT : out std_logic; -- Composite and RF base frequency.
CSYNC_OUTn : out std_logic; -- Composite sync (negative).
CSYNC_OUT : out std_logic; -- Composite sync (positive).
-- RGB & Composite input signals.
VWAITn_A21_V_CSYNC : inout std_logic; -- Upper address bit for access to FPGA resources / Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
VZ80_A20_RFSHn_V_HSYNCn : inout std_logic; -- Upper address bit for access to FPGA resources / Soft CPU RFSH out / Horizontal sync (negative) from mainboard.
VZ80_A19_HALTn_V_VSYNCn : inout std_logic; -- Upper address bit for access to FPGA resources / Soft CPU HALT out / Video memory selected / Vertical sync (negative) from mainboard.
VZ80_A17_NMIn_V_COLR : in std_logic; -- Upper address bit for access to FPGA resources / Soft CPU NMIn in / Composite and RF base frequency from mainboard.
VZ80_BUSRQn_V_G : in std_logic; -- Soft CPU BUSRQn in / Digital Green (on/off) from mainboard.
VZ80_A16_WAITn_V_B : in std_logic; -- Upper address bit for access to FPGA resources / Soft CPU WAITn in / Digital Blue (on/off) from mainboard.
VZ80_A18_INTn_V_R : in std_logic -- Upper address bit for access to FPGA resources / Soft CPU INTn in / Digital Red (on/off) from mainboard.
);
END entity;
architecture rtl of coreMZ is
signal CPUCLK_75MHZ : std_logic;
signal PLL_LOCKED : std_logic;
signal RESETn : std_logic := '0';
signal RESET_COUNTER : unsigned(3 downto 0) := (others => '1');
signal CTRLREG_RESET : std_logic := '1'; -- Flag to indicate when a hard reset occurs so that registers can be preloaded based on conditions.
signal MODE_CPLD_VIDEO_WAIT : std_logic; -- FPGA video display period wait flag, 1 = enabled, 0 = disabled.
signal CPU_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPU Configuration register.
signal CPU_INFO_DATA : std_logic_vector(7 downto 0); -- CPU configuration information register.
signal CPLD_CFG_DATA : std_logic_vector(7 downto 0):=(others => '0'); -- CPLD configuration register.
signal MODE_CPU_SOFT : std_logic; -- Control signal to enable the Soft CPU and support logic.
signal MODE_SOFTCPU_RESET : std_logic; -- Software controlled reset signal to reset a soft cpu.
signal MODE_SOFTCPU_CLKEN : std_logic; -- Enable the soft cpu clock (1).
signal MODE_CPLD_MB_VIDEOn : std_logic := '0'; -- Machine configuration (memory map, I/O etc) set in the CPLD. When this flag is set, the mainboard video logic is enabled, disabling or blending with the FPGA graphics.
signal MODE_SOFTCPU_Z80 : std_logic; -- Flag to indicate the Z80 module is available and active.
signal MODE_SOFTCPU_ZPUEVO : std_logic; -- Flag to indicate the ZPU Evo module is available and active.
signal CS_IO_6XXn : std_logic; -- Chip select for CPLD configuration registers.
signal CS_CPU_CFGn : std_logic; -- Select to set the CPU configuration register.
signal CS_CPU_INFOn : std_logic; -- Select to read the CPU information register.
signal CS_CPLD_CFGn : std_logic; -- Chip Select to write to the CPLD configuration register at 0x6E.
signal VZ80_HI_ADDR : std_logic_vector(23 downto 16); -- Upper address bits (to 16M) are multiplexed and only available during external access of the FPGA resources.
signal VZ80_BUSACKni : std_logic; -- Internal combination of BUSACK signals.
signal COLOUR_CARRIER_FREQ : std_logic; -- Modulator colour carrier frequency output by video module.
-- T80 - General identifier for Z80 based Soft CPU's, the T80 being the primary but also AZ80 and NextZ80 are available via config flag.
--
signal T80_MREQn : std_logic;
signal T80_IORQn : std_logic;
signal T80_WRn : std_logic;
signal T80_RDn : std_logic;
signal T80_M1n : std_logic;
signal T80_RFSHn : std_logic;
signal T80_ADDR : std_logic_vector(15 downto 0);
signal T80_DATA_OUT : std_logic_vector(7 downto 0);
signal T80_BUSACKn : std_logic;
signal T80_HALTn : std_logic;
-- ZPU
signal ZPU80_MREQn : std_logic;
signal ZPU80_IORQn : std_logic;
signal ZPU80_WRn : std_logic;
signal ZPU80_RDn : std_logic;
signal ZPU80_M1n : std_logic;
signal ZPU80_RFSHn : std_logic;
signal ZPU80_ADDR : std_logic_vector(15 downto 0);
signal ZPU80_VIDEO_ADDR : std_logic_vector(7 downto 0);
signal ZPU80_DATA_OUT : std_logic_vector(7 downto 0);
signal ZPU80_HALTn : std_logic;
signal ZPU_DATA_OUT : std_logic_vector(31 downto 0); -- External RAM block data to write to RAM.
signal ZPU_WRITE_EN : std_logic; -- Write to external RAM.
signal ZPU_MEM_BUSACK : std_logic; -- Memory bus acknowledge signal.
signal ZPU_VIDEO_ADDR : std_logic_vector(23 downto 0); -- Dedicated video address, bypasses the CPLD.
signal ZPU_VIDEO_DATA_IN : std_logic_vector(31 downto 0); -- Video controller to ZPU data in.
signal ZPU_VIDEO_DATA_OUT : std_logic_vector(31 downto 0); -- ZPU to Video controller data out.
signal ZPU_VIDEO_WRn : std_logic; -- Dedicated video channel write signal, bypasses the CPLD.
signal ZPU_VIDEO_RDn : std_logic; -- Dedicated video channel read signal, bypasses the CPLD.
signal ZPU_VIDEO_WR_BYTE : std_logic; -- Dedicated video channel 8bit byte write identifier signal, bypasses the CPLD.
signal ZPU_VIDEO_WR_HWORD : std_logic; -- Dedicated video channel 16bit half word write identifier signal, bypasses the CPLD.
-- Internal core signals, muxed or demuxed physical connections.
--
signal CORE_MREQn : std_logic; --
signal CORE_IORQn : std_logic; --
signal CORE_RDn : std_logic; --
signal CORE_WRn : std_logic; --
signal CORE_M1n : std_logic; --
signal CORE_RFSHn : std_logic; --
signal CORE_HALTn : std_logic; --
signal CORE_RESETn : std_logic;
signal CORE_VIDEO_WRn : std_logic; -- FPGA video write. Normally from the CPLD memory manager but overriden by soft CPU's such as the ZPU.
signal CORE_VIDEO_RDn : std_logic; -- FPGA video read. Normally from the CPLD memory manager but overriden by soft CPU's such as the ZPU.
signal CORE_VIDEO_WR_BYTE : std_logic; -- FPGA video byte write. A single byte is written when this flag is active.
signal CORE_VIDEO_WR_HWORD : std_logic; -- FPGA video 16bit half word write. A 16bit word, 2 bytes are written when this flag is active, half word aligned.
signal CORE_ADDR : std_logic_vector(23 downto 0); --
signal CORE_DATA_OUT : std_logic_vector(31 downto 0); --
signal CORE_DATA_IN : std_logic_vector(31 downto 0); --
signal VZ80_CLK_LAST : std_logic_vector(2 downto 0);
signal VZ80_BUSRQn : std_logic;
begin
------------------------------------------------------------------------------------
-- PLL System generation.
------------------------------------------------------------------------------------
-- Instantiate a PLL to generate the clocks required by soft processors.
--
COREMZPLL1 : entity work.Video_Clock_IV
port map
(
inclk0 => CLOCK_50,
areset => '0',
c0 => CPUCLK_75MHZ,
locked => PLL_LOCKED
);
------------------------------------------------------------------------------------
-- Serial Flash Loader for updating the EPCS64 via Altera Quartus.
------------------------------------------------------------------------------------
SERIALFLASHLOADER: if IMPL_SFL = true generate
-- Add the Serial Flash Loader megafunction to enable in-situ programming of the EPCS16 configuration memory.
--
SFL : entity work.sfl_iv
port map
(
noe_in => '0'
);
end generate;
------------------------------------------------------------------------------------
-- System Reset
------------------------------------------------------------------------------------
-- Process to reset the FPGA based on the external RESET trigger, PLL's being locked
-- and a counter to set minimum width.
--
FPGARESET: process(CLOCK_50, PLL_LOCKED)
begin
if PLL_LOCKED = '0' then
RESET_COUNTER <= (others => '1');
RESETn <= '0';
elsif PLL_LOCKED = '1' then
if rising_edge(CLOCK_50) then
if RESET_COUNTER /= 0 then
RESET_COUNTER <= RESET_COUNTER - 1;
elsif VIDEO_WRn = '0' and VIDEO_RDn = '0' then
RESETn <= '0';
elsif (VIDEO_WRn = '1' or VIDEO_RDn = '1') and RESET_COUNTER = 0 then
RESETn <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------
-- Video Controller
------------------------------------------------------------------------------------
vcCoreVideo : entity work.VideoController
--generic map
--(
--)
port map
(
-- Primary and video clocks.
CLOCK_50 => CLOCK_50, -- 50MHz main FPGA clock.
-- Reset.
VRESETn => CORE_RESETn, -- Internal reset.
-- V[name] = Voltage translated signals which mirror the mainboard signals but at a lower voltage.
-- Address Bus
VIDEO_ADDR => CORE_ADDR, -- 24bit Address bus.
-- Data Bus
VIDEO_DATA_IN => CORE_DATA_IN, -- Data bus from CPU into video module.
VIDEO_DATA_OUT => CORE_DATA_OUT, -- Data bus from video module to CPU.
-- Control signals.
VIDEO_IORQn => CORE_IORQn, -- IORQ signal, active low. When high, request is to memory.
VIDEO_RDn => CORE_VIDEO_RDn, -- Decoded Video Controller Read from CPLD memory manager.
VIDEO_WRn => CORE_VIDEO_WRn, -- Decoded Video Controller Write from CPLD memory manager.
VIDEO_WR_BYTE => CORE_VIDEO_WR_BYTE, -- Signal to indicate a byte should be written not a 32bit word.
VIDEO_WR_HWORD => CORE_VIDEO_WR_HWORD, -- Signal to indicate a 16bit half word should be written not a 32bit word.
-- VGA & Composite output signals.
VGA_R => VGA_R, -- 16 level Red output.
VGA_G => VGA_G, -- 16 level Green output.
VGA_B => VGA_B, -- 16 level Blue output.
VGA_R_COMPOSITE => VGA_R_COMPOSITE, -- RGB Red override for composite output.
VGA_G_COMPOSITE => VGA_G_COMPOSITE, -- RGB Green override for composite output.
VGA_B_COMPOSITE => VGA_B_COMPOSITE, -- RGB Blue override for composite output.
HSYNC_OUTn => HSYNC_OUTn, -- Horizontal sync.
VSYNC_OUTn => VSYNC_OUTn, -- Vertical sync.
COLR_OUT => COLOUR_CARRIER_FREQ, -- Composite colour and RF base frequency.
CSYNC_OUTn => CSYNC_OUTn, -- Composite sync (negative).
CSYNC_OUT => CSYNC_OUT, -- Composite sync (positive).
-- RGB & Composite input signals.
VWAITn_V_CSYNC => VWAITn_A21_V_CSYNC, -- Wait signal to the CPU when accessing FPGA video RAM / Composite sync from mainboard.
V_HSYNCn => VZ80_A20_RFSHn_V_HSYNCn, -- Horizontal sync (negative) from mainboard.
V_VSYNCn => VZ80_A19_HALTn_V_VSYNCn, -- Vertical sync (negative) from mainboard.
V_COLR => VZ80_A17_NMIn_V_COLR, -- Soft CPU NMIn / Composite and RF base frequency from mainboard.
V_G => VZ80_BUSRQn_V_G, -- Soft CPU BUSRQn / Digital Green (on/off) from mainboard.
V_B => VZ80_A16_WAITn_V_B, -- Soft CPU WAITn / Digital Blue (on/off) from mainboard.
V_R => VZ80_A18_INTn_V_R, -- Soft CPU INTn / Digital Red (on/off) from mainboard.
-- Configuration.
VIDEO_MODE => CPLD_CFG_DATA(2 downto 0), -- Video mode the controller should emulate.
MB_VIDEO_ENABLEn => MODE_CPLD_MB_VIDEOn -- Mainboard video enabled (=0) or FPGA advanced video (=1).
);
------------------------------------------------------------------------------------
-- T80 CPU
------------------------------------------------------------------------------------
CPU0: if IMPL_SOFTCPU_Z80 = true generate
signal T80_INTn : std_logic;
signal T80_NMIn : std_logic;
signal T80_BUSRQn : std_logic;
signal T80_WAITn : std_logic;
signal T80_DATA_IN : std_logic_vector(7 downto 0);
begin
T80CPU : entity work.softT80
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
SYS_CLK => CLOCK_50, -- System logic clock ~50MHz
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => MODE_SOFTCPU_RESET, -- Software controlled reset.
SW_CLKEN => MODE_SOFTCPU_CLKEN, -- Software controlled clock enable.
SW_CPUEN => MODE_SOFTCPU_Z80, -- Software controlled CPU enable.
-- Core Sharp MZ signals.
T80_WAITn => T80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
T80_INTn => T80_INTn, -- INTn signal for maskable interrupts.
T80_NMIn => T80_NMIn, -- NMIn non maskable interrupt input.
T80_BUSRQn => T80_BUSRQn, -- BUSRQn signal to request CPU go into tristate and relinquish bus.
T80_M1n => T80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
T80_MREQn => T80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
T80_IORQn => T80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
T80_RDn => T80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
T80_WRn => T80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
T80_RFSHn => T80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
T80_HALTn => T80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
T80_BUSACKn => T80_BUSACKn, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
T80_ADDR => T80_ADDR, -- 16 bit address lines.
T80_DATA_IN => T80_DATA_IN, -- 8 bit data bus in.
T80_DATA_OUT => T80_DATA_OUT -- 8 bit data bus out.
);
-- Soft CPU data input. Read directly from the Video Controller if selected, at all other times read from the CPLD which in turn reads from the tranZPUter or mainboard.
T80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and T80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT(7 downto 0) when CORE_VIDEO_RDn = '0'
else
VZ80_DATA when MODE_SOFTCPU_Z80 = '1' and T80_RDn = '0'
else (others => '0');
-- Direct routed signals to the T80 when not using mainboard video.
T80_INTn <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
T80_NMIn <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
T80_BUSRQn <= VZ80_BUSRQn when MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1'
else '1';
T80_WAITn <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_Z80 = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
else generate
T80_WRn <= '1';
T80_RDn <= '1';
T80_M1n <= '1';
T80_HALTn <= '1';
T80_MREQn <= '1';
T80_IORQn <= '1';
T80_BUSACKn <= '1';
T80_ADDR <= (others => 'X');
T80_DATA_OUT <= (others => 'X');
end generate;
------------------------------------------------------------------------------------
-- ZPU Evolution CPU
------------------------------------------------------------------------------------
CPU1: if IMPL_SOFTCPU_ZPUEVO = true generate
signal ZPU80_INTn : std_logic;
signal ZPU80_NMIn : std_logic;
signal ZPU80_WAITn : std_logic;
signal ZPU80_DATA_IN : std_logic_vector(7 downto 0);
signal ZPU_MEM_BUSRQ : std_logic; -- Memory bus request signal.
begin
ZPUCPU : entity work.softZPU
generic map (
SYSCLK_FREQUENCY => 75000000 -- Speed of clock used for the ZPU.
)
port map (
-- System signals and clocks.
SYS_RESETn => RESETn, -- System reset.
ZPU_CLK => CPUCLK_75MHZ, -- ZPU clock.
Z80_CLK => VZ80_CLK, -- Underlying hardware system clock
-- Software controlled signals.
SW_RESET => MODE_SOFTCPU_RESET, -- Software controlled reset.
SW_CLKEN => MODE_SOFTCPU_CLKEN, -- Software controlled clock enable.
SW_CPUEN => MODE_SOFTCPU_ZPUEVO, -- Software controlled CPU enable.
-- Direct access to the video controller, bypassing the CPLD Memory management.
VIDEO_ADDR => ZPU_VIDEO_ADDR, -- Direct video controller addressing, bypass CPLD memory manager and operate at 32bits.
VIDEO_DATA_IN => ZPU_VIDEO_DATA_IN, -- Video controller to ZPU data in.
VIDEO_DATA_OUT => ZPU_VIDEO_DATA_OUT, -- ZPU to Video controller data out.
VIDEO_WRn => ZPU_VIDEO_WRn, -- Direct video write from ZPU, bypass CPLD memory manager.
VIDEO_RDn => ZPU_VIDEO_RDn, -- Direct video read from ZPU, bypass CPLD memory manager.
VIDEO_WR_BYTE => ZPU_VIDEO_WR_BYTE, -- Direct video write byte signal, when set a byte should be written.
VIDEO_WR_HWORD => ZPU_VIDEO_WR_HWORD, -- Direct video write byte signal, when set a 16bit half word should be written.
-- External Direct addressing Bus. Ability to read and write to the internal ZPU memory for uploading new programs/debugging.
-- When BUSRQ is asserted, the external system can drive the signals to query memory.
-- A23 -A16
-- 00000000 - Normal Sharp MZ behaviour
-- 00001XXX - Video Controller
-- 00010000 ->
-- 00011000 - ZPU 128K Block. Boot and stack memory.
-- Access to internal BRAM access signals, become active when bus granted.
INT_MEM_DATA_IN => X"000000" & VZ80_DATA(7 downto 0), -- Internal RAM block data to write to RAM.
INT_MEM_DATA_OUT => ZPU_DATA_OUT, -- Internal RAM block data read from RAM.
INT_MEM_ADDR => VZ80_HI_ADDR & VZ80_ADDR, -- 24bit address bus to address RAM.
INT_MEM_WRITE_EN => not VZ80_WRn, -- Write to internal RAM.
INT_MEM_WRITE_BYTE_EN => '1', -- Write is 1 byte wide.
INT_MEM_WRITE_HWORD_EN => '0', -- Write is 1 half word wide.
-- Bus request/ack mechanism.
MEM_BUSRQ => ZPU_MEM_BUSRQ, -- Bus request signal. Set to 1 when external control is needed of the memory bus.
MEM_BUSACK => ZPU_MEM_BUSACK, -- Bus acknowledge signal, set to 1 when control of the bus is granted.
-- Core Sharp MZ signals.
ZPU80_WAITn => ZPU80_WAITn, -- WAITn signal into the CPU to prolong a memory cycle.
ZPU80_INTn => ZPU80_INTn, -- INTn signal for maskable interrupts.
ZPU80_NMIn => ZPU80_NMIn, -- NMIn non maskable interrupt input.
ZPU80_BUSRQn => '1', -- BUSRQn signal to request CPU go into tristate and relinquish bus. Not used in this design
ZPU80_M1n => ZPU80_M1n, -- M1n Machine Cycle 1 signal. M1 and MREQ active = opcode fetch, M1 and IORQ active = interrupt, vector can be read from D0-D7.
ZPU80_MREQn => ZPU80_MREQn, -- MREQn signal indicates that the address bus holds a valid address for reading or writing memory.
ZPU80_IORQn => ZPU80_IORQn, -- IORQn signal indicates that the address bus (A0-A7) holds a valid address for reading or writing and I/O device.
ZPU80_RDn => ZPU80_RDn, -- RDn signal indicates that data is ready to be read from a memory or I/O device to the CPU.
ZPU80_WRn => ZPU80_WRn, -- WRn signal indicates that data is going to be written from the CPU data bus to a memory or I/O device.
ZPU80_RFSHn => ZPU80_RFSHn, -- RFSHn signal to indicate dynamic memory refresh can take place.
ZPU80_HALTn => ZPU80_HALTn, -- HALTn signal indicates that the CPU has executed a "HALT" instruction.
ZPU80_BUSACKn => open, -- BUSACKn signal indicates that the CPU address bus, data bus, and control signals have entered their HI-Z states, and that the external circuitry can now control these lines.
ZPU80_ADDR => ZPU80_ADDR, -- 16 bit address lines.
ZPU80_DATA_IN => ZPU80_DATA_IN, -- 8 bit data bus in.
ZPU80_DATA_OUT => ZPU80_DATA_OUT, -- 8 bit data bus out.
-- Debug.
DEBUG_TXD_IN => COLOUR_CARRIER_FREQ, -- Serial debug loop, used as output when debug not enabled.
DEBUG_TXD_OUT => COLR_OUT -- Debug serial output when debug enabled. / DEBUG_TXD_IN when debug disabled.
);
-- Direct routed signals to the ZPU when not using mainboard video.
ZPU_VIDEO_DATA_IN <= CORE_DATA_OUT;
ZPU80_INTn <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_NMIn <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_WAITn <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '1' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1')
else '1';
ZPU80_DATA_IN <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and MODE_CPU_SOFT = '1' and ZPU80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and MODE_CPU_SOFT = '1' and ZPU80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT(7 downto 0) when CORE_VIDEO_RDn = '0'
else
VZ80_DATA when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_RDn = '0'
else (others => '0');
ZPU_MEM_BUSRQ <= '1' when VZ80_BUSRQn = '0' and (MODE_SOFTCPU_ZPUEVO = '1' or MODE_CPLD_MB_VIDEOn = '1') -- Incoming BUSRQ from the K64F requests the ZPU Bus as well.
else '0';
else generate
ZPU80_M1n <= '1';
ZPU80_MREQn <= '1';
ZPU80_IORQn <= '1';
ZPU80_RDn <= '1';
ZPU80_WRn <= '1';
ZPU80_RFSHn <= '1';
ZPU80_HALTn <= '1';
ZPU80_ADDR <= (others => '0');
ZPU80_DATA_OUT <= (others => '0');
ZPU_WRITE_EN <= '0';
ZPU_MEM_BUSACK <= '0';
ZPU_VIDEO_WRn <= '1';
ZPU_VIDEO_RDn <= '1';
end generate;
------------------------------------------------------------------------------------
-- Core Logic
------------------------------------------------------------------------------------
-- Common Control Registers
--
--
CTRLREGISTERS: process( RESETn, CLOCK_50, VZ80_CLK, CS_CPU_CFGn, CS_CPLD_CFGn, VZ80_WRn, VZ80_RDn )
variable SOFT_RESET_COUNTER : unsigned(3 downto 0); -- Down counter to set reset pulse width.
begin
-- Ensure default values at reset.
if RESETn='0' then
CTRLREG_RESET <= '1';
CPU_CFG_DATA(7 downto 6) <= "01"; -- Dont reset soft CPU selection flag on a reset.
MODE_SOFTCPU_RESET <= '0';
SOFT_RESET_COUNTER := (others => '0');
VZ80_CLK_LAST <= (others => '0');
elsif rising_edge(CLOCK_50) then
-- Hard reset we must return registers to the same as the CPLD.
if CTRLREG_RESET = '1' then
CTRLREG_RESET <= '0';
if CPLD_CFG_DATA(7) = '0' or CPU_CFG_DATA(5 downto 0) = "000000" then
CPLD_CFG_DATA <= "10000100"; -- Default to Sharp MZ700, mainboard video enabled, wait state off.
end if;
end if;
-- Detect clean edges.
VZ80_CLK_LAST <= VZ80_CLK_LAST(1 downto 0) & VZ80_CLK;
-- As the Z80 clock is originating in the CPLD and it is a mux between the mainboard generated clock and the K64F variable frequency clock, we need to bring it into this FPGA clock
-- domain for better sync and timing. We act on the negative edge as the T80 has slightly different timing thus to remain compatible with the Z80/T80 we clock on the negative edge.
--
if VZ80_CLK_LAST = "000" and VZ80_CLK = '1' then
-- CPLD/CPU Configuration registers.
--
-- CPU:
-- Version 1.3-> of the tranZPUter SW-700 provides the ability to instantiate alternative soft CPU's. This register configures the FPGA to enable a soft/hard CPU and the CPLD
-- is reconfigured to allow a CPU operation on the FPGA side rather than the physical hardware side.
--
-- [5:0] - R/W - CPU selection.
-- 000000 = Hard CPU
-- 000001 = T80 CPU
-- 000010 = ZPU Evolution
-- 000100 = Future CPU AAA
-- 001000 = Future CPU AAA
-- 010000 = Future CPU AAA
-- 100000 = Future CPU AAA
-- All other configurations reserved and default to Hard CPU.
-- [6] - R/W - Clock enable. Enable (1) or disable the soft CPU clock.
-- [7] - R/W - CPU Reset. When set to active ('1'), a reset pulse is generated and the bit state returned to 0.
--
-- CPLD:
-- The mode can be changed by a Z80 transaction write into the register and it is acted upon if the mode switches between differing values. The Z80 write is typically used
-- by host software such as RFS.
--
-- [2:0] - R/W - Mode/emulated machine.
-- 000 = MZ-80K
-- 001 = MZ-80C
-- 010 = MZ-1200
-- 011 = MZ-80A
-- 100 = MZ-700
-- 101 = MZ-800
-- 110 = MZ-80B
-- 111 = MZ-2000
-- [3] - R/W - Mainboard Video - 0 = Enable, 1 = Disable - This flag allows Z-80 transactions in the range D000:DFFF to be directed to the mainboard. When disabled all transactions
-- can only be seen by the FPGA video logic. The FPGA uses this flag to enable/disable it's functionality.
-- [4] - R/W - Enable WAIT state during frame display period. 1 = Enable, 0 = Disable (default). The flag enables Z80 WAIT assertion during the frame display period. Most video modes
-- use double buffering so this isnt needed, but use of direct writes to the frame buffer in 8 colour mode (ie. 640x200 or 320x200 8 colour) there
-- is not enough memory to double buffer so potentially there could be tear or snow, hence this optional wait generator.
-- [7] - R/W - Preserve configuration over reset (=1) or set to default on reset (=0).
--
if(CS_CPU_CFGn = '0' and VZ80_WRn = '0') then
-- Store the new value into the register, used for read operations.
CPU_CFG_DATA <= VZ80_DATA;
-- Check to ensure only one CPU selected, if more than one default to hard CPU. Also check to ensure only instantiated CPU's selected, otherwise default to hard CPU.
--
if (unsigned(VZ80_DATA(5 downto 0)) and (unsigned(VZ80_DATA(5 downto 0))-1)) /= 0 or (VZ80_DATA(5 downto 2) and "1111") /= "0000" or (IMPL_SOFTCPU_Z80 = false and VZ80_DATA(0) = '1') or (IMPL_SOFTCPU_ZPUEVO = false and VZ80_DATA(1) = '1') then
CPU_CFG_DATA(5 downto 0) <= (others => '0');
end if;
elsif(CS_CPLD_CFGn = '0' and VZ80_WRn = '0') then
-- Store the new value into the register, used for read operations.
CPLD_CFG_DATA <= VZ80_DATA;
end if;
-- Soft reset mechanism. If the reset flag was set on the previous cycle, toggle reset active and start a down counter. On zero, toggle reset to inactive.
if CPU_CFG_DATA(7) = '1' then
MODE_SOFTCPU_RESET <= '1';
SOFT_RESET_COUNTER := (others => '1');
CPU_CFG_DATA(7) <= '0';
end if;
if SOFT_RESET_COUNTER /= 0 then
SOFT_RESET_COUNTER := SOFT_RESET_COUNTER - 1;
else
MODE_SOFTCPU_RESET <= '0';
end if;
end if;
end if;
end process;
-- Mode flags to indicate a CPU is available and selected.
MODEZ80: if IMPL_SOFTCPU_Z80 = true generate
MODE_SOFTCPU_Z80 <= '1' when CPU_CFG_DATA(0) = '1'
else '0';
else generate
MODE_SOFTCPU_Z80 <= '0';
end generate;
MODEEVO: if IMPL_SOFTCPU_ZPUEVO = true generate
MODE_SOFTCPU_ZPUEVO <= '1' when CPU_CFG_DATA(1) = '1'
else '0';
else generate
MODE_SOFTCPU_ZPUEVO <= '0';
end generate;
--
MODE_SOFTCPU_CLKEN <= CPU_CFG_DATA(6);
-- CPU information register.
-- [5:0] - R/O - CPU Availability.
-- 000000 = Hard CPU
-- 000001 = T80 CPU
-- 000010 = ZPU Evolution
-- 000100 = Future CPU AAA
-- 001000 = Future CPU AAA
-- 010000 = Future CPU AAA
-- 100000 = Future CPU AAA
-- [7:6] - R/O - Soft CPU capable, 01 = capable, /01 = not capable (value to cater for non-FPGA reads which return 11 or 00).
--
CPU_INFO_DATA <= "01000001" when IMPL_SOFTCPU_Z80 = true and IMPL_SOFTCPU_ZPUEVO = false
else
"01000010" when IMPL_SOFTCPU_Z80 = false and IMPL_SOFTCPU_ZPUEVO = true
else
"01000011" when IMPL_SOFTCPU_Z80 = true and IMPL_SOFTCPU_ZPUEVO = true
else
"00000000";
-- CPLD configuration register range.
CS_IO_6XXn <= '0' when CORE_IORQn = '0' and CORE_ADDR(7 downto 4) = "0110"
else '1';
-- CPU configuration register range within the FPGA. These registers select and control the soft/hard CPU and parameters.
CS_CPU_CFGn <= '0' when CS_IO_6XXn = '0' and CORE_ADDR(3 downto 0) = "1100" -- IO 6C
else '1';
CS_CPU_INFOn <= '0' when CS_IO_6XXn = '0' and CORE_ADDR(3 downto 0) = "1101" -- IO 6D
else '1';
-- CPLD mirrored logic. Registers on the CPLD which need to be known by the FPGA are duplicated within the FPGA.
CS_CPLD_CFGn <= '0' when CS_IO_6XXn = '0' and CORE_ADDR(3 downto 0) = "1110" -- IO 6E - CPLD configuration register.
else '1';
-- Set the mainboard video state, 0 = enabled, 1 = disabled. Signal set to enabled if the soft cpu is enabled.
MODE_CPLD_MB_VIDEOn <= '1' when CPLD_CFG_DATA(3) = '1' or CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Flag to indicate Soft CPU is running,
MODE_CPU_SOFT <= '1' when CPU_CFG_DATA(5 downto 0) /= "000000"
else '0';
-- Mux the main Z80 control signals for internal use, either use the hard Z80 on the tranZPUter or the soft CPU in the FPGA.
--
CORE_MREQn <= VZ80_MREQn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_MREQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_MREQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_IORQn <= VZ80_IORQn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_IORQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_IORQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_RDn <= VZ80_RDn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_RDn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_WRn <= VZ80_WRn when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_WRn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_M1n <= VZ80_M1n when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else
T80_M1n when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_M1n when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_RFSHn <= T80_RFSHn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RFSHn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_HALTn <= T80_HALTn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_HALTn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else '1';
CORE_VIDEO_WRn <= '0' when VZ80_BUSACKni = '0' and VZ80_WRn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
ZPU_VIDEO_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else
VIDEO_WRn;
CORE_VIDEO_RDn <= '0' when VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_HI_ADDR(23 downto 19) = "00001"
else
ZPU_VIDEO_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else
VIDEO_RDn;
-- 32/16/8 bit write select. When the ZPU is writing, the signals are active and controlled by the ZPU, otherwise default to 1 byte writes.
CORE_VIDEO_WR_BYTE <= '1' when ZPU_VIDEO_WRn = '1'
else
ZPU_VIDEO_WR_BYTE;
CORE_VIDEO_WR_HWORD <= '0' when ZPU_VIDEO_WRn = '1'
else
ZPU_VIDEO_WR_HWORD;
-- Internal reset dependent on external reset or a change of the SOFT CPU.
CORE_RESETn <= '0' when RESETn = '0'
else '1';
-- Address lines driven according to the CPU being used. Hard CPU = address via CPLD, Soft CPU = address direct.
CORE_ADDR <= X"00" & T80_ADDR when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_VIDEO_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and (ZPU_VIDEO_WRn = '0' or ZPU_VIDEO_RDn = '0')
else
X"00" & ZPU80_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and ZPU_VIDEO_WRn = '1' and ZPU_VIDEO_RDn = '1'
else
VZ80_HI_ADDR & VZ80_ADDR when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else (others => '0');
-- Data into the core, generally the Video Controller, comes from the CPLD (hard CPU or mainboard) if the soft CPU is disabled else from the soft CPU.
CORE_DATA_IN <= X"000000" & T80_DATA_OUT when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU_VIDEO_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and (ZPU_VIDEO_WRn = '0' or ZPU_VIDEO_RDn = '0')
else
X"000000" & ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' and ZPU_VIDEO_WRn = '1' and ZPU_VIDEO_RDn = '1'
else
X"000000" & VZ80_DATA when MODE_CPU_SOFT = '0' or VZ80_BUSACKni = '0'
else (others => '0');
-- tranZPUter, hard CPU or mainboard data input. Read directly from the Video Controller if selected, else the data being output from the soft CPU if enabled otherwise
-- tri-state as data is coming from the CPLD.
VZ80_DATA <= CPU_CFG_DATA when CS_CPU_CFGn = '0' and VZ80_RDn = '0' -- Read current CPU register settings.
else
CPU_INFO_DATA when CS_CPU_INFOn = '0' and VZ80_RDn = '0' -- Read CPU version & hw build information.
else
CORE_DATA_OUT (7 downto 0) when CORE_VIDEO_RDn = '0' -- If the video resources are being read, either by the hard cpu or the K64f, output requested data.
else
T80_DATA_OUT when MODE_SOFTCPU_Z80 = '1' and T80_WRn = '0' and VZ80_BUSACKni = '1' -- T80 has control over writing data when enabled and bus not requested.
else
ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_WRn = '0' and VZ80_BUSACKni = '1' -- ZPU Evo Z80 Bus controller has control over writing data when enabled and bus not requested.
else
ZPU80_DATA_OUT when MODE_SOFTCPU_ZPUEVO = '1' and ZPU80_MREQn = '0' and ZPU80_IORQn = '0' and VZ80_BUSACKni = '1' -- ZPU has control when writing special control word to CPLD to enable memory mode.
-- When bus requested, K64F has control, reading data from the ZPU BRAM if selected.
else
ZPU_DATA_OUT(7 downto 0) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "11"
else
ZPU_DATA_OUT(15 downto 8) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "10"
else
ZPU_DATA_OUT(23 downto 16) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "01"
else
ZPU_DATA_OUT(31 downto 24) when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '0' and VZ80_RDn = '0' and VZ80_ADDR(1 downto 0) = "00"
else (others => 'Z');
-- Direct routed signals to the ZPU when not using mainboard video.
VZ80_HI_ADDR(16) <= VZ80_A16_WAITn_V_B when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(17) <= VZ80_A17_NMIn_V_COLR when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(18) <= VZ80_A18_INTn_V_R when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(19) <= VZ80_A19_HALTn_V_VSYNCn when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(20) <= VZ80_A20_RFSHn_V_HSYNCn when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(21) <= VWAITn_A21_V_CSYNC when VZ80_BUSACKni = '0'
else '0';
VZ80_HI_ADDR(22) <= '0';
VZ80_HI_ADDR(23) <= '0';
-- Tri-state controls. If the hard Z80 is being used then tri-state output signals.
VZ80_MREQn <= T80_MREQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1' -- When the T80 is selected and not under K64F control, drive the MREQ line output by the T80.
else
ZPU80_MREQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1' -- When the ZPU Evo is selected and not under K64F control, drive the MREQ line output by the T80.
else 'Z';
VZ80_IORQn <= T80_IORQn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_IORQn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_RDn <= T80_RDn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RDn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_WRn <= T80_WRn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_WRn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_M1n <= T80_M1n when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_M1n when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_A20_RFSHn_V_HSYNCn<=T80_RFSHn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_RFSHn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_A19_HALTn_V_VSYNCn<=T80_HALTn when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_HALTn when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else 'Z';
VZ80_ADDR <= T80_ADDR when MODE_SOFTCPU_Z80 = '1' and VZ80_BUSACKni = '1'
else
ZPU80_ADDR when MODE_SOFTCPU_ZPUEVO = '1' and VZ80_BUSACKni = '1'
else (others => 'Z');
VZ80_BUSACKni <= '0' when MODE_CPU_SOFT = '0' and VZ80_BUSRQn = '0' and MODE_CPLD_MB_VIDEOn = '1' -- When soft CPU's are disabled, generate a BUSACK when FPGA video is enabled and BUSRQ is asserted.
else
'0' when MODE_SOFTCPU_Z80 = '1' and T80_BUSACKn = '0'
else
'0' when MODE_SOFTCPU_ZPUEVO = '1' and ZPU_MEM_BUSACK = '1' -- The ZPU has priority, when it acknowledges then the Z80 BUS is already idle.
else '1';
VZ80_BUSRQn <= VZ80_BUSRQn_V_G when MODE_CPU_SOFT = '1' or MODE_CPLD_MB_VIDEOn = '1' -- Just a wire, demux of the VZ80_BUSRQn_V_G signal.
else '1';
VZ80_BUSACKn <= VZ80_BUSACKni;
end architecture;

181
FPGA/SW700/v1.3/coreMZ_SoftCPU_constraints.sdc Normal file
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@@ -0,0 +1,181 @@
## Generated SDC file "VideoController700_constraints.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
## DATE "Fri Jul 3 00:11:58 2020"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {VZ80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {VZ80_CLK}]
create_clock -name {softT80:\CPU0:T80CPU|T80_CLK} -period 50
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
create_generated_clock -name {CPUCLK_75MHZ} -source [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 3 -divide_by 2 -phase 0.00 -master_clock {CLOCK_50} [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|clk[0]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
set_input_delay -add_delay -clock [get_clocks {VZ80_CLK}] 1.000 [get_ports {VZ80_CLK}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIDEO_WRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VIDEO_RDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_MREQn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_M1n}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_ADDR[*]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_DATA[*]}]
# set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_B_COMPOSITE}]
# set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_G_COMPOSITE}]
# set_input_delay -add_delay -clock [get_clocks {SYS_CLK}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn_A21_V_CSYNC}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A20_RFSHn_V_HSYNCn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A19_HALTn_V_VSYNCn}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 0.000 [get_ports {VZ80_BUSRQn_V_G}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A16_WAITn_V_B}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A18_INTn_V_R}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A17_NMIn_V_COLR}]
# # Required for the Serial Flash Loader.
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tck}]
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tms}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_DATA[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_MREQn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_M1n}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_BUSACKn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn_A21_V_CSYNC}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A20_RFSHn_V_HSYNCn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_A19_HALTn_V_VSYNCn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_G_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R[*]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_R_COMPOSITE}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {HSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSYNC_OUTn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {COLR_OUT}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC_OUT}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSYNC_OUTn}]
# # Required for the Serial Flash Loader.
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {SFL_IV:\SERIALFLASHLOADER:SFL|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
set_output_delay -add_delay -clock { altera_reserved_tck } 1.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -setup -end 3
set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -hold -end 2
#**************************************************************
# Set Maximum Delay
#**************************************************************
set_max_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_ADDR[*]}] 100.00
set_max_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 100.00
set_max_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 100.00
set_max_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 100.00
set_max_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 100.00
set_max_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_RDn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_IORQn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VIDEO_RDn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_ADDR[*]} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VWAITn_A21_V_CSYNC} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A20_RFSHn_V_HSYNCn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A19_HALTn_V_VSYNCn} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A18_INTn_V_R} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A17_NMIn_V_COLR} -to [get_ports {VZ80_DATA[*]}] 50.00
set_max_delay -from {VZ80_A16_WAITn_V_B} -to [get_ports {VZ80_DATA[*]}] 50.00
#**************************************************************
# Set Minimum Delay
#**************************************************************
set_min_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_ADDR[*]}] 1.00
set_min_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 1.00
set_min_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_ADDR[*]}] 1.00
set_min_delay -from {CPLD_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {CPU_CFG_DATA[*]} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_BUSRQn_V_G} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_RDn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_IORQn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VIDEO_RDn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_ADDR[*]} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VWAITn_A21_V_CSYNC} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A20_RFSHn_V_HSYNCn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A19_HALTn_V_VSYNCn} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A18_INTn_V_R} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A17_NMIn_V_COLR} -to [get_ports {VZ80_DATA[*]}] 1.00
set_min_delay -from {VZ80_A16_WAITn_V_B} -to [get_ports {VZ80_DATA[*]}] 1.00
#**************************************************************
# Set Input Transition
#**************************************************************

8
FPGA/SW700/v1.3/coreMZ_constraints.sdc
View File

@@ -40,13 +40,13 @@ set_time_format -unit ns -decimal_places 3
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {VZ80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {VZ80_CLK}]
create_clock -name {softT80:\CPU0:T80CPU|T80_CLK} -period 50
#create_clock -name {softT80:\CPU0:T80CPU|T80_CLK} -period 50
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
create_generated_clock -name {CPUCLK_75MHZ} -source [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 3 -divide_by 2 -phase 0.00 -master_clock {CLOCK_50} [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|clk[0]}]
#create_generated_clock -name {CPUCLK_75MHZ} -source [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 3 -divide_by 2 -phase 0.00 -master_clock {CLOCK_50} [get_pins {COREMZPLL1|altpll_component|auto_generated|pll1|clk[0]}]
#**************************************************************
@@ -133,8 +133,8 @@ set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -setup -end 3
set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -hold -end 2
#set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -setup -end 3
#set_multicycle_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CPUCLK_75MHZ}] -hold -end 2
#**************************************************************
# Set Maximum Delay

2
FPGA/SW700/v1.3/coreMZ_pkg.vhd
View File

@@ -61,7 +61,7 @@ package coreMZ_pkg is
-- Add the Serial Flash Loader megafunction to enable programming of the EPCS64 NV FPGA Boot ROM.
constant IMPL_SFL : boolean := true;
-- Soft CPU's to embed in the core.
-- Soft CPU's to embed in the core for the SoftCPU build.
--
constant IMPL_SOFTCPU_Z80 : boolean := true;
constant IMPL_SOFTCPU_ZPUEVO : boolean := true;

1
FPGA/SW700/v1.3/softT80/softT80_pkg.vhd
View File

@@ -66,6 +66,7 @@ package softT80_pkg is
constant IMPL_SOFTCPU_T80 : boolean := true;
constant IMPL_SOFTCPU_AZ80 : boolean := false;
constant IMPL_SOFTCPU_NEXTZ80 : boolean := false;
--constant IMPL_SOFTCPU_Z80 : boolean := IMPL_SOFTCPU_T80 or IMPL_SOFTCPU_AZ80 or IMPL_SOFTCPU_NEXTZ80;
------------------------------------------------------------
-- Function prototypes

4
FPGA/SW700/v1.3/softZPU/ZPU/zpu_pkg.vhd
View File

@@ -139,6 +139,10 @@ package zpu_pkg is
RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU.
START_ADDR_MEM : integer := 0; -- Start address of program memory.
STACK_ADDR : integer := 0; -- Initial stack address on CPU start.
-- EXT_MEM_START : integer := 16#100000#; -- Start of off chip memory needing different timing to onchip resources.
-- EXT_MEM_SIZE : integer := 16#080000#; -- Size of off chip memory.
-- EXT_IO_START : integer := 16#D00000#; -- Start of off chip I/O region needing different timing to onchip resources.
-- EXT_IO_SIZE : integer := 16#200000#; -- Size of off chip I/O region.
CLK_FREQ : integer := 100000000 -- Frequency of the input clock.
);
port (

73
FPGA/SW700/v1.3/softZPU/softZPU.vhd
View File

@@ -206,6 +206,11 @@ architecture rtl of softZPU is
signal TIMER1_CS : std_logic; -- 0xC10-C1F
signal SOCCFG_CS : std_logic; -- 0xF00-F0F
-- Debug signals.
--signal BRAM_SELECT2 : std_logic;
--signal BRAM_WREN2 : std_logic;
--signal BRAM_DATA_READ2 : std_logic_vector(WORD_32BIT_RANGE); -- Data output from BRAM.
-- BRAM
signal BRAM_DATA_READ : std_logic_vector(WORD_32BIT_RANGE); -- Data output from BRAM.
@@ -325,6 +330,32 @@ begin
else
INT_MEM_DATA_IN;
-- Debug code to replace the external 512K RAM with a chunk of BRAM for debugging comparisons.
-- SOFTCPUBRAM2 : entity work.SinglePortBRAM
-- generic map (
-- addrbits => 15
-- )
-- port map (
-- clk => ZPU_CLK,
-- memAAddr => BRAM_ADDR(14 downto 0),
-- memAWriteEnable => BRAM_WREN2,
-- memAWriteByte => BRAM_BYTE_ENABLE,
-- memAWriteHalfWord => BRAM_HWORD_ENABLE,
-- memAWrite => BRAM_DATA_IN,
-- memARead => BRAM_DATA_READ2
-- );
--
-- BRAM_WREN2 <= '1' when BRAM_SELECT2 = '1' and MEM_WRITE_ENABLE = '1'
-- else
-- '1' when BRAM_SELECT2 = '1' and INT_MEM_WR_LASTn = "10"
-- else '0';
--
-- BRAM_SELECT2 <= '1' when MEM_ADDR(Z80BUS_DECODE_RANGE) = std_logic_vector(to_unsigned(1, maxAddrBit-WB_ACTIVE - maxZ80BusBit))
-- else '0';
------------------------------------------------------------------------------------
-- ZPU Evolution and SoC
------------------------------------------------------------------------------------
@@ -368,6 +399,10 @@ begin
RESET_ADDR_CPU => SOC_RESET_ADDR_CPU, -- Initial start address of the CPU.
START_ADDR_MEM => SOC_START_ADDR_MEM, -- Start address of program memory.
STACK_ADDR => SOC_STACK_ADDR, -- Initial stack address on CPU start.
-- EXT_MEM_START => Z80_MEM_START, -- Start of off chip memory needing different timing to onchip resources.
-- EXT_MEM_SIZE => Z80_MEM_SIZE, -- Size of off chip memory.
-- EXT_IO_START => Z80_IO_START, -- Start of off chip I/O region needing different timing to onchip resources.
-- EXT_IO_SIZE => Z80_IO_SIZE, -- Size of off chip I/O region.
CLK_FREQ => SYSCLK_FREQUENCY -- System clock frequency.
)
port map (
@@ -438,6 +473,8 @@ begin
-- Select CPU input source, memory or IO.
MEM_DATA_READ <= BRAM_DATA_READ when BRAM_SELECT = '1'
else
-- BRAM_DATA_READ2 when BRAM_SELECT2 = '1'
-- else
IO_DATA_READ_INTRCTL when SOC_IMPL_INTRCTL = true and INTR0_CS = '1'
else
IO_DATA_READ_SOCCFG when SOC_IMPL_SOCCFG = true and SOCCFG_CS = '1'
@@ -762,7 +799,7 @@ begin
Z80_BUS_BUSACKn <= '0';
-- Start a Z80 BUS Read or Write?
elsif Z80_START_XACT = '0' and Z80_XACT_RUN = '0' and ((MEM_WRITE_ENABLE_LAST = "001" and MEM_WRITE_ENABLE = '1') or (MEM_READ_ENABLE_LAST = "001" and MEM_READ_ENABLE = '1')) and Z80BUS_CS = '1' and Z80_BUS_BUSACKn = '1' then
elsif Z80_START_XACT = '0' and Z80_XACT_RUN = '0' and ((MEM_WRITE_ENABLE_LAST = "011" and MEM_WRITE_ENABLE = '1') or (MEM_READ_ENABLE_LAST = "001" and MEM_READ_ENABLE = '1')) and Z80BUS_CS = '1' and Z80_BUS_BUSACKn = '1' then
-- Halt the ZPU, Z80 transactions take a lot more time.
IO_WAIT_Z80BUS <= '1';
@@ -850,11 +887,11 @@ begin
Z80_START_XACT <= '0';
IO_WAIT_Z80BUS <= '0';
end if;
end if;
-- Z80 bus domain. Run according to transaction target, either full speed or at the frequency of the hard/soft Z80 to correctly emulate a Z80 bus transaction.
--
if Z80_BUS_XACT_FULLSPEED = '1' or (Z80_CLK_EDGE = "001" and Z80_CLK = '1') then
elsif Z80_BUS_XACT_FULLSPEED = '1' or (Z80_BUS_XACT_FULLSPEED = '0' and Z80_CLK_EDGE = "001" and Z80_CLK = '1') then
--elsif (Z80_CLK_EDGE = "001" and Z80_CLK = '1') then
-- Edge detection of completion flag.
Z80_XACT_RUN_LAST <= Z80_XACT_RUN;
@@ -889,7 +926,8 @@ begin
Z80_BUS_DATA_OUT <= Z80_BUS_HOST_ACCESS & "0000000";
Z80_BUS_M1n <= '1';
else
Z80_BUS_DATA_OUT <= (others => '0'); --Z80_ADDR(23 downto 16);
--Z80_BUS_DATA_OUT <= (others => '0'); --Z80_ADDR(23 downto 16);
Z80_BUS_DATA_OUT <= Z80_ADDR(23 downto 16);
Z80_BUS_M1n <= '0';
end if;
Z80_BUS_MREQn <= '0';
@@ -906,6 +944,8 @@ begin
--
case Z80BusFSMState is
when State_IDLE =>
Z80_BUS_XACT_FULLSPEED <= '0';
Z80_XACT_RUN <= '0';
-- Setup the address and clear all lines ready for the Z80 transaction.
when State_SETUP =>
@@ -920,7 +960,7 @@ begin
when State_MEM_READ =>
Z80_BUS_MREQn <= '0';
Z80_BUS_RDn <= '0';
Z80BusFSMState <= State_MEM_READ_2;
Z80BusFSMState <= State_MEM_READ_1;
-- Detect and insert wait states.
when State_MEM_READ_1 =>
@@ -937,20 +977,21 @@ begin
--Z80_DATA_IN <= ZPU80_DATA_IN & Z80_DATA_IN(31 downto 8);
Z80_DATA_IN <= Z80_DATA_IN(23 downto 0) & ZPU80_DATA_IN;
-- Read in upto Z80_BYTE_COUNT bytes then return to idle. When Z80_XACT_RUN is cleared the ZPU will latch the read word.
--
if Z80_BYTE_COUNT > 1 then
Z80_BYTE_COUNT <= Z80_BYTE_COUNT -1;
Z80_BYTE_ADDR <= Z80_BYTE_ADDR + 1;
Z80BusFSMState <= Z80_BUS_XACT;
else
Z80BusFSMState <= State_IDLE;
Z80_XACT_RUN <= '0';
end if;
-- Read sets signals on 1st transaction clock edge.
when State_MEM_BYTE_READ =>
Z80_BUS_MREQn <= '0';
Z80_BUS_RDn <= '0';
Z80BusFSMState <= State_MEM_BYTE_READ_2;
Z80BusFSMState <= State_MEM_BYTE_READ_1;
-- Detect and insert wait states.
when State_MEM_BYTE_READ_1 =>
@@ -966,7 +1007,7 @@ begin
-- Single byte appears in bits 7:0
Z80_DATA_IN <= X"000000" & ZPU80_DATA_IN;
Z80BusFSMState <= State_IDLE;
Z80_XACT_RUN <= '0';
-- Z80_XACT_RUN <= '0';
-- Write activates MREQ and prepares data on the bus.
-- Mechanism setup to write MSB Big Endian.
@@ -1003,9 +1044,9 @@ begin
-- Activate Write and detect and insert wait states.
when State_MEM_WRITE_1 =>
Z80_BUS_WRn <= '0';
-- if ZPU80_WAITn = '1' or Z80_BUS_VIDEO_WRITE = '1' then
if ZPU80_WAITn = '1' then -- or Z80_BUS_VIDEO_WRITE = '1' then
Z80BusFSMState <= State_MEM_WRITE_2;
-- end if;
end if;
when State_MEM_WRITE_2 =>
Z80_BUS_MREQn <= '1';
@@ -1016,7 +1057,7 @@ begin
Z80BusFSMState <= Z80_BUS_XACT;
else
Z80BusFSMState <= State_IDLE;
Z80_XACT_RUN <= '0';
-- Z80_XACT_RUN <= '0';
end if;
-- IO Read sets signals on 1st transaction clock edge as address already setup.
@@ -1031,9 +1072,9 @@ begin
-- Detect and insert further wait states.
when State_IO_READ_2 =>
-- if ZPU80_WAITn = '1' then
if ZPU80_WAITn = '1' then
Z80BusFSMState <= State_IO_READ_3;
-- end if;
end if;
-- End of read cycle we sample and store data.
when State_IO_READ_3 =>
@@ -1049,7 +1090,7 @@ begin
Z80BusFSMState <= Z80_BUS_XACT;
else
Z80BusFSMState <= State_IDLE;
Z80_XACT_RUN <= '0';
-- Z80_XACT_RUN <= '0';
end if;
-- IO Read sets signals on 1st transaction clock edge as address already setup.
@@ -1076,7 +1117,7 @@ begin
-- Single byte appears in bits 7:0
Z80_DATA_IN <= X"000000" & ZPU80_DATA_IN;
Z80BusFSMState <= State_IDLE;
Z80_XACT_RUN <= '0';
-- Z80_XACT_RUN <= '0';
-- Write prepares data on the bus.
when State_IO_WRITE =>
@@ -1129,7 +1170,7 @@ begin
Z80BusFSMState <= Z80_BUS_XACT;
else
Z80BusFSMState <= State_IDLE;
Z80_XACT_RUN <= '0';
-- Z80_XACT_RUN <= '0';
end if;
when others =>

8
FPGA/SW700/v1.3/softZPU/softZPU_pkg.vhd
View File

@@ -84,10 +84,16 @@ package softZPU_pkg is
constant ZPU_ID_EVO_MINIMAL : integer := 16#0501#; -- ID for the ZPU Evo Minimal in this package.
-- EVO CPU specific configuration.
constant MAX_EVO_L1CACHE_BITS : integer := 6; -- Maximum size in instructions of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
constant MAX_EVO_L1CACHE_BITS : integer := 5; -- Maximum size in instructions of the Level 1 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
constant MAX_EVO_L2CACHE_BITS : integer := 14; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
constant MAX_EVO_MXCACHE_BITS : integer := 4; -- Maximum size of the memory transaction cache governed by the number of bits.
-- Z80 BUS FSM memory ranges.
constant Z80_MEM_START : integer := 16#100000#; -- Start of the Z80 Memory (512KB/1MB) range.
constant Z80_MEM_SIZE : integer := 16#080000#; -- Size of the Z80 memory range.
constant Z80_IO_START : integer := 16#D00000#; -- Start of the Z80 Memory/IO mapped IO range.
constant Z80_IO_SIZE : integer := 16#200000#; -- Size of the Z80
-- Settings for various IO devices.
--
constant SYSTEM_FREQUENCY : integer := 100000000; -- Default system clock frequency if not overriden in top level.

232
cpu/zpu_core_evo.vhd Executable file → Normal file
View File

@@ -64,6 +64,8 @@
-- change could see the target address changing and the fetch from the old location stored into the new.
-- 210113 v1.5 Fixed shift operators, a misunderstanding of the requirements led to the wrong design which when activated (ie. hardware
-- options enabled at GCC compile time) failed.
-- 210506 v1.6 Added variable timing for external memory, specifically intended for the Z80 state machine, accessing 8 bit memory/IO
-- with 32bit ZPU transactions.
--
library ieee;
@@ -199,6 +201,10 @@ entity zpu_core_evo is
RESET_ADDR_CPU : integer := 0; -- Initial start address of the CPU.
START_ADDR_MEM : integer := 0; -- Start address of program memory.
STACK_ADDR : integer := 0; -- Initial stack address on CPU start.
EXT_MEM_START : integer := 16#100000#; -- Start of off chip memory needing different timing to onchip resources.
EXT_MEM_SIZE : integer := 16#080000#; -- Size of off chip memory.
EXT_IO_START : integer := 16#D00000#; -- Start of off chip I/O region needing different timing to onchip resources.
EXT_IO_SIZE : integer := 16#200000#; -- Size of off chip I/O region.
CLK_FREQ : integer := 100000000 -- Frequency of the input clock.
);
port (
@@ -549,7 +555,6 @@ architecture behave of zpu_core_evo is
signal debugRec : zpu_dbg_t; -- A complex register record for placing data to be serialised by the debug serialiser.
signal debugLoad : std_logic; -- Load a debug record into the debug serialiser fsm, 1 = load, 0 = inactive.
signal debugReady : std_logic; -- Flag to indicate serializer fsm is busy (0) or available (1).
---------------------------------------------
-- Functions specific to the CPU core.
---------------------------------------------
@@ -617,7 +622,7 @@ begin
and
(IMPL_USE_INSN_BUS = false or (IMPL_USE_INSN_BUS = true and unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr) >= to_unsigned(MAX_INSNRAM_SIZE, mxFifo(to_integer(mxFifoReadIdx)).addr'length)))
else '0';
cacheL2Full <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) - cacheL2StartAddr(ADDR_32BIT_RANGE) = MAX_L2CACHE_SIZE / 4
cacheL2Full <= '1' when cacheL2FetchIdx(ADDR_32BIT_RANGE) - cacheL2StartAddr(ADDR_32BIT_RANGE) = to_unsigned(MAX_L2CACHE_SIZE / 4, cacheL2StartAddr'length)
else '0';
cacheL2InsnAfterPC <= cacheL2FetchIdx - pc when cacheL2Invalid = '0'
else to_unsigned(0, cacheL2InsnAfterPC'length);
@@ -678,20 +683,6 @@ begin
------------------------
elsif falling_edge(CLK) then
-- TOS and NOS are multiplexed between an immediate result from the MXP (which is latched on the subsequent clock) and the latched value. The valid
-- flag indicates which to use.
-- muxTOS.valid <= mxTOS.valid or TOS.valid;
-- if mxTOS.valid = '1' then
-- muxTOS.word <= mxTOS.word;
-- else
-- muxTOS.word <= TOS.word;
-- end if;
-- muxNOS.valid <= mxNOS.valid or NOS.valid;
-- if mxNOS.valid = '1' then
-- muxNOS.word <= mxNOS.word;
-- else
-- muxNOS.word <= NOS.word;
-- end if;
-----------------------
-- RISING CLOCK EDGE --
@@ -702,15 +693,6 @@ begin
mxTOS.valid <= '0';
mxNOS.valid <= '0';
-- Memory signals are one clock width wide unless extended by a wait, if no wait, reset them to inactive to ensure this.
if MEM_BUSY = '0' and mxHoldCycles = 0 then
MEM_READ_ENABLE <= '0';
MEM_WRITE_ENABLE <= '0';
-- Width signals are one clock width wide unless extended by a wait signal.
MEM_WRITE_BYTE <= '0';
MEM_WRITE_HWORD <= '0';
end if;
-- Complete any active cache memory writes.
if cacheL2Write = '1' and mxHoldCycles = 0 then
@@ -749,22 +731,35 @@ begin
MEM_BUSACK <= '0';
end if;
-- Memory signals are one clock width wide unless extended by a wait, if no wait, reset them to inactive to ensure this.
if MEM_BUSY = '0' and (MEM_READ_ENABLE = '1' or MEM_WRITE_ENABLE = '1') and mxHoldCycles = 0 then
MEM_READ_ENABLE <= '0';
MEM_WRITE_ENABLE <= '0';
-- Width signals are one clock width wide unless extended by a wait signal.
MEM_WRITE_BYTE <= '0';
MEM_WRITE_HWORD <= '0';
-- When a bus request is made, wait until the mxp is idle, this is important as the mxp could read/write memory which gets updated by an external device.
elsif MEM_BUSRQ = '1' and MEM_BUSY = '0' and mxState = MemXact_Idle and mxXactSlotsUsed = 0 then
mxSuspend <= '1';
MEM_BUSACK <= '1';
-- If the hold cycle counter is not 0, then we are holding on the current transaction until it reaches zero, so decrement
-- ready to test next cycle. This mechanism is to prolong a memory cycle as without it, address setup and hold is 1 cycle and
-- valid data is expected at the end of the cycle. ie. the address and control signals are set on the current rising edge and become
-- active and on the next rising edge the data is expected to be valid, few components (ie. register ram) can meet this timing requirement.
if mxHoldCycles > 0 then
elsif mxHoldCycles > 0 then
mxHoldCycles <= mxHoldCycles - 1;
end if;
-- When a bus request is made, wait until the mxp is idle, this is important as the mxp could read/write memory which gets updated by an external device.
if MEM_BUSRQ = '1' and MEM_BUSY = '0' and mxState = MemXact_Idle and mxXactSlotsUsed = 0 then
mxSuspend <= '1';
MEM_BUSACK <= '1';
else
-- If the external memory is busy (1) or the wishbone interface is active and no ACK received then we have to back off and wait till next clock cycle and check again.
if MEM_BUSY = '0' and mxSuspend = '0' and mxHoldCycles = 0 and ((IMPL_USE_WB_BUS = true and ((wbXactActive = '1' and WB_ACK_I = '1') or wbXactActive = '0')) or IMPL_USE_WB_BUS = false) then
elsif MEM_BUSY = '0' and mxSuspend = '0' and ((IMPL_USE_WB_BUS = true and ((wbXactActive = '1' and WB_ACK_I = '1') or wbXactActive = '0')) or IMPL_USE_WB_BUS = false) then
-- For external operations involving memory to cache, preset the hold/busy sample counter because it is very hard to meet a single cycle BUSY assertion.
--
if cacheL2Active = '1' then
mxHoldCycles <= 1;
end if;
-- Memory transaction processor state machine. Idle is the control state and depending upon entries in the queue, debug or L2 usage, it
-- directs the FSM states accordingly.
@@ -870,8 +865,17 @@ begin
-- Initiate a cache memory write.
cacheL2Write <= '1';
end if;
mxState <= MemXact_Idle;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
else
mxHoldCycles <= 1;
end if;
mxState <= MemXact_Idle;
-- Read value at address, then write data to the value's address.
when MX_CMD_WRITETOINDADDR =>
@@ -881,8 +885,17 @@ begin
else
MEM_READ_ENABLE <= '1';
end if;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
else
mxHoldCycles <= 1;
end if;
mxState <= MemXact_WriteToAddr;
mxHoldCycles <= 2;
-- To write a byte, if hardware supports it, write out to the byte aligned address with data in bits 7-0 otherwise
-- we first read the 32bit word, update it and write it back.
@@ -928,8 +941,16 @@ mxHoldCycles <= 2;
end if;
mxFifoReadIdx <= mxFifoReadIdx + 1;
mxState <= MemXact_Idle;
mxHoldCycles <= 0;
mxHoldCycles <= 2;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
else
mxHoldCycles <= 1;
end if;
-- If the data write is to a cached location, update cache at same time.
if cacheL2MxAddrInCache = '1' then
@@ -989,8 +1010,16 @@ mxHoldCycles <= 2;
cacheL2WriteHword <= '1';
cacheL2Write <= '1';
end if;
mxHoldCycles <= 0;
mxHoldCycles <= 2;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
else
mxHoldCycles <= 1;
end if;
end if;
when others =>
@@ -998,28 +1027,6 @@ mxHoldCycles <= 2;
mxState <= MemXact_Idle;
end case;
-- If instruction queue is empty or there are no memory transactions to process and the instruction cache isnt full,
-- read the next instruction and fill the instruction cache.
elsif cacheL2Active = '1' and cacheL2Full = '0' and cacheL2IncAddr = '0' then
if IMPL_USE_WB_BUS = true and cacheL2FetchIdx(WB_SELECT_BIT) = '1' then
WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE));
WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0');
WB_WE_O <= '0';
WB_CYC_O <= '1';
WB_STB_O <= '1';
WB_CTI_O <= "000";
WB_SEL_O <= "1111";
wbXactActive <= '1';
mxHoldCycles <= 1;
else
MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE));
MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0');
MEM_READ_ENABLE <= '1';
mxHoldCycles <= 1;
end if;
cacheL2WriteAddr <= cacheL2FetchIdx(L2CACHE_BIT_RANGE);
mxState <= MemXact_OpcodeFetch;
-- If there are no memory transactions to complete, debugging is enabled and the debug outputter is active, read the memory location
-- according to the given index.
elsif DEBUG_CPU = true and (debugState /= Debug_Idle and debugState /= Debug_DumpL1 and debugState /= Debug_DumpL2 and debugState /= Debug_DumpMem) then
@@ -1040,6 +1047,34 @@ mxHoldCycles <= 2;
end if;
mxMemVal.valid <= '0';
mxState <= MemXact_MemoryFetch;
-- If instruction queue is empty or there are no memory transactions to process and the instruction cache isnt full,
-- read the next instruction and fill the instruction cache.
elsif cacheL2Active = '1' and cacheL2Full = '0' and cacheL2IncAddr = '0' then
if IMPL_USE_WB_BUS = true and cacheL2FetchIdx(WB_SELECT_BIT) = '1' then
WB_ADR_O(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE));
WB_ADR_O(minAddrBit-1 downto 0) <= (others => '0');
WB_WE_O <= '0';
WB_CYC_O <= '1';
WB_STB_O <= '1';
WB_CTI_O <= "000";
WB_SEL_O <= "1111";
wbXactActive <= '1';
else
MEM_ADDR(ADDR_32BIT_RANGE) <= std_logic_vector(cacheL2FetchIdx(ADDR_32BIT_RANGE));
MEM_ADDR(minAddrBit-1 downto 0) <= (others => '0');
MEM_READ_ENABLE <= '1';
end if;
cacheL2WriteAddr <= cacheL2FetchIdx(L2CACHE_BIT_RANGE);
mxState <= MemXact_OpcodeFetch;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
end if;
end if;
when MemXact_MemoryFetch =>
@@ -1074,9 +1109,6 @@ mxHoldCycles <= 2;
mxTOS.word <= unsigned(MEM_DATA_IN);
end if;
mxTOS.valid <= '1';
if cacheL2Active = '1' then
mxHoldCycles <= 1;
end if;
mxState <= MemXact_Idle;
when MemXact_NOS =>
@@ -1086,9 +1118,6 @@ mxHoldCycles <= 2;
mxNOS.word <= unsigned(MEM_DATA_IN);
end if;
mxNOS.valid <= '1';
if cacheL2Active = '1' then
mxHoldCycles <= 1;
end if;
mxState <= MemXact_Idle;
when MemXact_TOSNOS =>
@@ -1120,9 +1149,6 @@ mxHoldCycles <= 2;
mxFifoReadIdx <= mxFifoReadIdx + 1;
mxState <= MemXact_Idle;
end if;
if cacheL2Active = '1' then
mxHoldCycles <= 1;
end if;
when MemXact_TOSNOS_3 =>
if IMPL_USE_WB_BUS = true and wbXactActive = '1' then
@@ -1189,9 +1215,19 @@ mxHoldCycles <= 2;
-- Initiate a cache memory write.
cacheL2Write <= '1';
end if;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
else
mxHoldCycles <= 1;
end if;
mxFifoReadIdx <= mxFifoReadIdx + 1;
mxState <= MemXact_Idle;
mxHoldCycles <= 2;
when MemXact_WriteByteToAddr =>
-- For wishbone, we need to store the data and terminate the current cycle before we can commence a write cycle.
@@ -1210,6 +1246,7 @@ mxHoldCycles <= 2;
mxFifoReadIdx <= mxFifoReadIdx + 1;
mxState <= MemXact_Idle;
end if;
-- If the data write is to a cached location, we have read the original value, so update cache with modified version.
if cacheL2MxAddrInCache = '1' then
-- Update the data to write with the actual changed byte,
@@ -1218,7 +1255,16 @@ mxHoldCycles <= 2;
-- Initiate a cache memory write.
cacheL2Write <= '1';
end if;
mxHoldCycles <= 2;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
else
mxHoldCycles <= 1;
end if;
when MemXact_WriteByteToAddr2 =>
if IMPL_USE_WB_BUS = true then
@@ -1249,6 +1295,7 @@ mxHoldCycles <= 2;
mxFifoReadIdx <= mxFifoReadIdx + 1;
mxState <= MemXact_Idle;
end if;
-- If the data write is to a cached location, we have read the original value, so update cache with modified version.
if cacheL2MxAddrInCache = '1' then
-- Update the data to write with the actual changed byte,
@@ -1257,7 +1304,16 @@ mxHoldCycles <= 2;
-- Initiate a cache memory write.
cacheL2Write <= '1';
end if;
mxHoldCycles <= 2;
-- Different timing for external memory.
if ((to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_MEM_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_MEM_START+EXT_MEM_SIZE)
or
(to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) >= EXT_IO_START and to_integer(unsigned(mxFifo(to_integer(mxFifoReadIdx)).addr)) < EXT_IO_START+EXT_IO_SIZE)) then
mxHoldCycles <= 2;
else
mxHoldCycles <= 1;
end if;
when MemXact_WriteHWordToAddr2 =>
if IMPL_USE_WB_BUS = true then
@@ -1275,7 +1331,6 @@ mxHoldCycles <= 2;
when others =>
end case;
end if;
end if;
-- Instruction Level 2 cache, we read upto the limit then back off until the gap between executed and read instructions
-- gets to a watermark and then re-enable reading. This allows the cache to maintain a set of past and future instructions so that when a
@@ -1284,7 +1339,7 @@ mxHoldCycles <= 2;
if cacheL2Active = '1' then
-- If L2 fetching has been halted and the PC approaches the threshold (detault 3/4) then advance the Start Address of L2 data and re-enable L2 filling.
if cacheL2FetchIdx(ADDR_32BIT_RANGE) > pc(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) > cacheL2StartAddr(ADDR_32BIT_RANGE) and (pc - cacheL2StartAddr) > ((MAX_L2CACHE_SIZE/4)*3) and cacheL2Full = '1' then
if cacheL2FetchIdx(ADDR_32BIT_RANGE) > pc(ADDR_32BIT_RANGE) and pc(ADDR_32BIT_RANGE) > cacheL2StartAddr(ADDR_32BIT_RANGE) and (pc - cacheL2StartAddr) > to_unsigned(((MAX_L2CACHE_SIZE/4)*3), cacheL2StartAddr'length) and cacheL2Full = '1' then
cacheL2StartAddr <= cacheL2StartAddr + 16;
end if;
@@ -1620,14 +1675,16 @@ mxHoldCycles <= 2;
--end if;
-- Debug statement to output a block of data when a specific address is reached.
--if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"1002b67" then --cacheL1FetchIdx < cacheL1FetchIdx_last then
-- debugState <= Debug_Start;
--end if;
if DEBUG_CPU = true and debugState = Debug_Idle and pc = X"100076" then --cacheL1FetchIdx < cacheL1FetchIdx_last then
debugPC_StartAddr <= to_unsigned(16#0100200#, debugPC_StartAddr'LENGTH);
debugPC_EndAddr <= to_unsigned(16#0100300#, debugPC_EndAddr'LENGTH);
debugState <= Debug_DumpMem;
end if;
-- In debug mode, the memory dump start and stop address are controlled by 2 vectors, preload them with defaults if uninitialised.
if DEBUG_CPU = true and debugPC_EndAddr = 0 then
debugPC_StartAddr <= to_unsigned(16#1000000#, debugPC_StartAddr'LENGTH);
debugPC_EndAddr <= to_unsigned(16#1001000#, debugPC_EndAddr'LENGTH);
debugPC_StartAddr <= to_unsigned(16#0100000#, debugPC_StartAddr'LENGTH);
debugPC_EndAddr <= to_unsigned(16#0100100#, debugPC_EndAddr'LENGTH);
end if;
-- If the Memory Transaction processor has updated the stack parameters, update our working copy.
@@ -1676,7 +1733,6 @@ mxHoldCycles <= 2;
-- debugPC_Width <= 32;
-- debugState <= Debug_DumpMem;
--end if;
-------------------------------------
-- Execution Processor.
-------------------------------------
@@ -1791,8 +1847,8 @@ mxHoldCycles <= 2;
-- Execution depends on the L1 having decoded instructions stored at the current PC.
-- As a minimum the cache must be valid and that there is at least 1 instruction in the cache. The PC is 1 byte granularity, the cache pointers are 64bit word granularity.
elsif pc >= cacheL1StartAddr and pc < cacheL1FetchIdx and cacheL1StartAddr(ADDR_64BIT_RANGE) /= cacheL1FetchIdx(ADDR_64BIT_RANGE) then
elsif pc >= cacheL1StartAddr and pc(ADDR_64BIT_RANGE) < cacheL1FetchIdx(ADDR_64BIT_RANGE) and cacheL1StartAddr(ADDR_64BIT_RANGE) /= cacheL1FetchIdx(ADDR_64BIT_RANGE) then
--elsif pc >= cacheL1StartAddr and pc < cacheL1FetchIdx and cacheL1StartAddr(ADDR_64BIT_RANGE) /= cacheL1FetchIdx(ADDR_64BIT_RANGE) then
-- Set the stack offset for current instruction from its opcode.
tSpOffset(4) := not cacheL1(to_integer(pc))(4);
@@ -2855,7 +2911,7 @@ mxHoldCycles <= 2;
end if;
-- Debug code, if enabled, writes out the current instruction.
if (DEBUG_CPU = true and DEBUG_LEVEL >= 1) and tInsnExec = '1' and pc >= X"000000" then
if (DEBUG_CPU = true and DEBUG_LEVEL >= 1) and tInsnExec = '1' and pc >= X"100000" then --and pc /= X"100075" then
debugRec.FMT_DATA_PRTMODE <= "01";
debugRec.FMT_PRE_SPACE <= '0';
debugRec.FMT_POST_SPACE <= '1';
@@ -2897,7 +2953,7 @@ mxHoldCycles <= 2;
debugState <= Debug_DumpL2;
end if;
end if;
if (DEBUG_CPU = true and DEBUG_LEVEL >= 1) and pc >= X"000000" then
if (DEBUG_CPU = true and DEBUG_LEVEL >= 1) and pc >= X"100000" then
debugRec.FMT_DATA_PRTMODE <= "01";
debugRec.FMT_PRE_SPACE <= '0';
debugRec.FMT_POST_SPACE <= '1';
@@ -3360,7 +3416,7 @@ mxHoldCycles <= 2;
debugRec.FMT_POST_SPACE <= '0';
debugRec.FMT_PRE_CR <= '1';
debugRec.FMT_SPLIT_DATA <= "01";
if debugPC = MAX_L2CACHE_SIZE-1 or debugPC(4 downto 3) = "11" then
if debugPC = to_unsigned(MAX_L2CACHE_SIZE-1, debugPC'length) or debugPC(4 downto 3) = "11" then
debugRec.FMT_POST_CRLF <= '1';
else
debugRec.FMT_POST_CRLF <= '0';
@@ -3393,7 +3449,7 @@ mxHoldCycles <= 2;
when Debug_DumpL2_2 =>
-- Move onto next opcode in Fifo.
if debugPC = MAX_L2CACHE_SIZE then
if debugPC >= to_unsigned(MAX_L2CACHE_SIZE, debugPC'length) then
if debugAllInfo = '1' then
debugState <= Debug_DumpMem;
else

103766
devices/sysbus/BRAM/TZSW_DualPortBootBRAM.vhd
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File diff suppressed because it is too large Load Diff

103766
devices/sysbus/BRAM/TZSW_SinglePortBootBRAM.vhd
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File diff suppressed because it is too large Load Diff

2
software/asm/include/CPM_Definitions.asm
View File

@@ -313,6 +313,8 @@ CMD33 EQU 64 + 33 ; ERASE
CMD38 EQU 64 + 38 ; ERASE
CMD55 EQU 64 + 55 ; APP_CMD
CMD58 EQU 64 + 58 ; READ_OCR
SD_SECSIZE EQU 512 ; Default size of an SD Sector
SD_RETRIES EQU 00100H ; Number of retries before giving up.
; Card type flags (CardType)
CT_MMC EQU 001H ; MMC ver 3