Tidying up warnings

This commit is contained in:
Philip Smart
2026-03-25 19:58:49 +00:00
parent b6c7e8bc42
commit 125b907506
23 changed files with 201 additions and 107 deletions

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@@ -836,15 +836,60 @@ esp_err_t WiFi::expandVarsAndSend(httpd_req_t *req, std::string str)
keyValue.value = wifiCtrl.run.quickDiskImage[0].empty() ? "none" : wifiCtrl.run.quickDiskImage[0];
pairs.push_back(keyValue);
// System status items for the dashboard panel.
keyValue.value = "N/A";
keyValue.name = "%SK_FWVERSION%"; pairs.push_back(keyValue);
keyValue.name = "%SK_ESPVERSION%"; pairs.push_back(keyValue);
keyValue.name = "%SK_ACTIVEPARTITION%"; pairs.push_back(keyValue);
keyValue.name = "%SK_PERSONA%"; pairs.push_back(keyValue);
keyValue.name = "%SK_CPUCLOCK%"; pairs.push_back(keyValue);
keyValue.name = "%SK_PSRAMCLOCK%"; pairs.push_back(keyValue);
keyValue.name = "%SK_SDCARD%"; pairs.push_back(keyValue);
keyValue.name = "%SK_UPTIME%"; pairs.push_back(keyValue);
// Guard against uninitialised flash header (INF not yet received from RP2350).
{
uint8_t activeApp = wifiCtrl.run.rp2350FlashHeader.activeApp;
bool haveInfo = (wifiCtrl.run.rp2350FlashHeader.configured == FLASH_APP_CONFIGURED_FLAG &&
activeApp >= 1 && activeApp < FLASH_APP_MAX_INSTANCES);
t_FlashPartitionInstance *ai = haveInfo ? &wifiCtrl.run.rp2350FlashHeader.config[activeApp] : NULL;
keyValue.name = "%SK_FWVERSION%";
keyValue.value = (ai && ai->version[0]) ? std::string(ai->version) + " (" + std::string(ai->versionDate) + ")" : "N/A";
pairs.push_back(keyValue);
keyValue.name = "%SK_ESPVERSION%";
{
const esp_app_desc_t *desc = esp_app_get_description();
keyValue.value = std::string(desc->version) + " (" + std::string(desc->date) + ")";
}
pairs.push_back(keyValue);
keyValue.name = "%SK_ACTIVEPARTITION%";
keyValue.value = haveInfo ? std::to_string(activeApp) : "N/A";
pairs.push_back(keyValue);
keyValue.name = "%SK_PERSONA%";
keyValue.value = (ai && ai->description[0]) ? std::string(ai->description) : "N/A";
pairs.push_back(keyValue);
keyValue.name = "%SK_CPUCLOCK%";
keyValue.value = (wifiCtrl.run.rp2350CpuFreq > 0) ?
std::to_string(wifiCtrl.run.rp2350CpuFreq / 1000000) + " MHz" : "N/A";
pairs.push_back(keyValue);
keyValue.name = "%SK_PSRAMCLOCK%";
keyValue.value = (wifiCtrl.run.rp2350PsramFreq > 0) ?
std::to_string(wifiCtrl.run.rp2350PsramFreq / 1000000) + " MHz" : "N/A";
pairs.push_back(keyValue);
keyValue.name = "%SK_SDCARD%";
keyValue.value = (sdcard != NULL) ? "Mounted" : "Not available";
pairs.push_back(keyValue);
keyValue.name = "%SK_UPTIME%";
{
int64_t us = esp_timer_get_time();
int secs = (int)(us / 1000000);
int days = secs / 86400; secs %= 86400;
int hrs = secs / 3600; secs %= 3600;
int mins = secs / 60; secs %= 60;
char buf[32];
if (days > 0) snprintf(buf, sizeof(buf), "%dd %02d:%02d:%02d", days, hrs, mins, secs);
else snprintf(buf, sizeof(buf), "%02d:%02d:%02d", hrs, mins, secs);
keyValue.value = buf;
}
pairs.push_back(keyValue);
}
keyValue.name = "%SK_FILEDIR%";
keyValue.value = "";
pairs.push_back(keyValue);

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@@ -1 +1 @@
5.4
5.41

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@@ -42,6 +42,8 @@
#include "hardware/watchdog.h"
#include "cJSON.h"
#include "intercore.h"
#include "ESP.h"
#include "usb_bridge.h"
#include "z80.pio.h" // File is generated from z80.pio during make.
// Include Device drivers.
@@ -88,7 +90,8 @@ static uint sm_data = PIO_SM_1, offset_data = 0;
// PIO 1 state machines.
static uint smCycle = PIO_SM_0, offsetCycle = 0;
static uint sm_busrq = PIO_SM_1, offset_busrq = 0;
static uint sm_int = PIO_SM_2, offset_int = 0;
static uint __attribute__((unused)) sm_int = PIO_SM_2;
static uint __attribute__((unused)) offset_int = 0;
static uint sm_nmi = PIO_SM_3, offset_nmi = 0;
// PIO 2 state machines.
@@ -137,7 +140,7 @@ static const size_t memoryTypeMapSize = sizeof(memoryTypeMap) / sizeof(memoryTyp
// This table allows JSON configuration to specify a function by giving a text name which is then mapped to the actual
// internal function.
static const t_FuncMap funcMap[] = {
{"DRAMREFRESH", Z80CPU_refreshDRAM}, // This function is intended to perform dummy M1 Fetch cycles in order
{"DRAMREFRESH", (t_MemoryFunc) Z80CPU_refreshDRAM}, // This function is intended to perform dummy M1 Fetch cycles in order
// to refresh host DRAM during internal RAM access.
};
static const size_t funcMapSize = sizeof(funcMap) / sizeof(funcMap[0]);
@@ -148,8 +151,8 @@ static const size_t funcMapSize = sizeof(funcMap) / sizeof(funcMap[0]);
// to the JSON properties.
// ie. Copy host motherboard ROM to internal RAM based ROM (CPPTORAM).
static const t_TaskMap taskMap[] = {
{"COPYTOPHYSICAL", Z80CPU_taskMirrorInternalRAMToPhysical}, // This task copies internal RAM to host motherboard memory.
{"COPYTORAM", Z80CPU_taskMirrorPhysicalToInternalRAM}, // This task copies host motherboard memory into internal RAM.
{"COPYTOPHYSICAL", (t_MemoryTask) Z80CPU_taskMirrorInternalRAMToPhysical}, // This task copies internal RAM to host motherboard memory.
{"COPYTORAM", (t_MemoryTask) Z80CPU_taskMirrorPhysicalToInternalRAM}, // This task copies host motherboard memory into internal RAM.
};
static const size_t taskMapSize = sizeof(taskMap) / sizeof(taskMap[0]);
@@ -162,7 +165,7 @@ static const size_t taskMapSize = sizeof(taskMap) / sizeof(taskMap[0]);
// exist according to requirements.
static const t_VirtualFuncMap virtualFuncMap[] = {
#ifdef INCLUDE_SHARP_DRIVERS
{"MZ700", MZ700_Init}, // This virtual function creates a Sharp MZ700 'persona' whereby
{"MZ700", (t_VirtualFunc) MZ700_Init}, // This virtual function creates a Sharp MZ700 'persona' whereby
// it sets up devices and memory structure to replicate the MZ700 logic.
#endif
};
@@ -289,7 +292,7 @@ uint32_t Z80CPU_ReadROM(t_FlashAppConfigHeader *appConfig,
// If a callback is provided, call it to handle the ROM otherwise manually copy.
if (cb != NULL)
{
cb(ctx, cfg, (uint8_t *) (FLASH_RAM_BASE + appConfig->s.ROMS[idx].addr), (int) appConfig->s.ROMS[idx].size);
cb(ctx, cfg, (char *) (FLASH_RAM_BASE + appConfig->s.ROMS[idx].addr), (int) appConfig->s.ROMS[idx].size);
}
else
{
@@ -1647,7 +1650,7 @@ bool Z80CPU_parseJSONStore(t_Z80CPU *cpu, cJSON *configRoot, uint8_t cfgApp, cha
debugf("Error: Virtual driver \"rom\" item %zu, driver %zu, \"file\" (%s) is not valid, skipping\r\n",
i3,
drvConfig,
drvROMFile == NULL ? "" : drvROMFile);
drvROMFile == NULL ? "" : drvROMFile->valuestring);
result = false;
continue;
}
@@ -2339,6 +2342,8 @@ t_Z80CPU *Z80CPU_init(void)
{
// Locals.
uint8_t loBank, hiBank;
(void) loBank;
(void) hiBank;
// Allocate memory to hold the control structure, initialise to defaults.
/*
@@ -2364,18 +2369,18 @@ t_Z80CPU *Z80CPU_init(void)
cpu->_Z80.fetch_opcode = Z80CPU_fetchPhysicalMem;
cpu->_Z80.write = Z80CPU_writePhysicalMem;
*/
cpu._Z80.in = Z80CPU_readIO;
cpu._Z80.out = Z80CPU_writeIO;
cpu._Z80.in = (Z80Read) Z80CPU_readIO;
cpu._Z80.out = (Z80Write) Z80CPU_writeIO;
cpu._Z80.inta = Z80CPU_readIntAck;
cpu._Z80.int_fetch = Z80CPU_fetchIntAckIM0; // Special handler for IM0 opcode fetch.
cpu._Z80.nmia = Z80CPU_nmia;
cpu._Z80.nop = Z80CPU_nop;
cpu._Z80.halt = Z80CPU_halt;
cpu._Z80.halt = (Z80Halt) Z80CPU_halt;
cpu._Z80.reti = Z80CPU_reti;
cpu._Z80.retn = Z80CPU_retn;
cpu._Z80.ld_i_a = Z80CPU_ldia;
cpu._Z80.ld_r_a = Z80CPU_ldra;
cpu._Z80.illegal = Z80CPU_illegal;
cpu._Z80.illegal = (Z80Illegal) Z80CPU_illegal;
cpu._z80PSRAM = NULL;
cpu._drivers.driver = NULL;
@@ -2735,7 +2740,7 @@ uint8_t __func_in_RAM(Z80CPU_readMem)(t_Z80CPU *cpu, uint16_t addr, uint32_t mem
{
// Call the function passing in the data from the current RAM address. If the function doesnt provide or
// override the data, then return what is in the RAM.
data = cpu->_z80PSRAM->memioPtr[addr](cpu, true, addr, cpu->_z80PSRAM->RAM[RAMaddr + blockaddr]);
data = (uint8_t)(uintptr_t) cpu->_z80PSRAM->memioPtr[addr](cpu, true, addr, cpu->_z80PSRAM->RAM[RAMaddr + blockaddr]);
}
else
{
@@ -2754,7 +2759,7 @@ uint8_t __func_in_RAM(Z80CPU_readMem)(t_Z80CPU *cpu, uint16_t addr, uint32_t mem
if (cpu->_z80PSRAM->memioPtr[addr])
{
//data = cpu->_z80PSRAM->memioPtr[block | blockaddr](cpu, true, addr, 0);
data = cpu->_z80PSRAM->memioPtr[addr](cpu, true, addr, 0);
data = (uint8_t)(uintptr_t) cpu->_z80PSRAM->memioPtr[addr](cpu, true, addr, 0);
}
break;
@@ -2799,7 +2804,7 @@ bool __func_in_RAM(Z80CPU_writeMem)(t_Z80CPU *cpu, uint16_t addr, uint32_t memba
if (cpu->_z80PSRAM->memioPtr[addr])
{
//data = cpu->_z80PSRAM->memioPtr[block | blockaddr](cpu, true, addr, data);
data = cpu->_z80PSRAM->memioPtr[addr](cpu, false, addr, data);
data = (uint8_t)(uintptr_t) cpu->_z80PSRAM->memioPtr[addr](cpu, false, addr, data);
}
else
{
@@ -2816,7 +2821,7 @@ bool __func_in_RAM(Z80CPU_writeMem)(t_Z80CPU *cpu, uint16_t addr, uint32_t memba
if (cpu->_z80PSRAM->memioPtr[addr])
{
//data = cpu->_z80PSRAM->memioPtr[block | blockaddr](cpu, true, addr, data);
data = cpu->_z80PSRAM->memioPtr[addr](cpu, false, addr, data);
data = (uint8_t)(uintptr_t) cpu->_z80PSRAM->memioPtr[addr](cpu, false, addr, data);
}
result = false;
break;
@@ -2828,7 +2833,7 @@ bool __func_in_RAM(Z80CPU_writeMem)(t_Z80CPU *cpu, uint16_t addr, uint32_t memba
if (cpu->_z80PSRAM->memioPtr[addr])
{
//data = cpu->_z80PSRAM->memioPtr[block | blockaddr](cpu, false, addr, data);
data = cpu->_z80PSRAM->memioPtr[addr](cpu, false, addr, data);
data = (uint8_t)(uintptr_t) cpu->_z80PSRAM->memioPtr[addr](cpu, false, addr, data);
}
else
{
@@ -2858,7 +2863,7 @@ uint8_t __func_in_RAM(Z80CPU_readIO)(t_Z80CPU *cpu, uint16_t addr)
if (cpu->_z80PSRAM->ioPtr[addr])
{
data = cpu->_z80PSRAM->ioPtr[addr](cpu, true, addr, 0);
data = (uint8_t)(uintptr_t) cpu->_z80PSRAM->ioPtr[addr](cpu, true, addr, 0);
}
else
{
@@ -2878,7 +2883,7 @@ bool __func_in_RAM(Z80CPU_writeIO)(t_Z80CPU *cpu, uint16_t addr, uint8_t data)
if (cpu->_z80PSRAM->ioPtr[addr])
{
result = cpu->_z80PSRAM->ioPtr[addr](cpu, false, addr, data);
result = (bool)(uintptr_t) cpu->_z80PSRAM->ioPtr[addr](cpu, false, addr, data);
}
else
{
@@ -2976,7 +2981,7 @@ uint8_t __func_in_RAM(Z80CPU_readByte)(void *context, uint16_t address)
// except the odd address.
if (cpu->_z80PSRAM->memioPtr[address])
{
data = cpu->_z80PSRAM->memioPtr[address](cpu, true, address, 0);
data = (uint8_t)(uintptr_t) cpu->_z80PSRAM->memioPtr[address](cpu, true, address, 0);
}
else
{
@@ -3124,6 +3129,7 @@ void __func_in_RAM(Z80CPU_retn)(void *context)
{
// Locals.
t_Z80CPU *cpu = (t_Z80CPU *) context;
(void) cpu;
debugf("RETN\r\n");
}

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@@ -112,13 +112,13 @@ uint8_t MZ1E05_Init(t_Z80CPU *cpu, t_drvIFConfig *config)
for (int idx = 0; idx < IO_PAGE_SIZE; idx++)
{
if ((idx & 0xff) >= 0xd8 && (idx & 0xff) < 0xdc)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1E05_IO_WD1773;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1E05_IO_WD1773;
if ((idx & 0xff) == 0xdc)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1E05_IO_DriveSel;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1E05_IO_DriveSel;
if ((idx & 0xff) == 0xdd)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1E05_IO_SideSel;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1E05_IO_SideSel;
if ((idx & 0xff) == 0xde)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1E05_IO_DDENSel;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1E05_IO_DDENSel;
}
}
}

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@@ -108,7 +108,7 @@ uint8_t MZ1E14_Init(t_Z80CPU *cpu, t_drvIFConfig *config)
for (int idx = 0; idx < IO_PAGE_SIZE; idx++)
{
if ((idx & 0xff) >= 0xf4 && (idx & 0xff) < 0xf8)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1E14_IO_QD;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1E14_IO_QD;
}
}
}

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@@ -113,7 +113,7 @@ uint8_t MZ1E19_Init(t_Z80CPU *cpu, t_drvIFConfig *config)
for (int idx = 0; idx < IO_PAGE_SIZE; idx++)
{
if ((idx & 0xff) >= 0xf4 && (idx & 0xff) < 0xf8)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1E19_IO_QD;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1E19_IO_QD;
}
}
}
@@ -198,6 +198,7 @@ uint8_t MZ1E19_PollCB(t_Z80CPU *cpu)
static uint32_t stallPollCount = 0;
static uint8_t lastPostEndBlk = 0;
static uint32_t postResetPollCount = 0;
(void)postResetPollCount;
// Process all responses from issued tasks to core 0.
qdProcessResponses(&mz1e19Ctrl->qd);
@@ -274,6 +275,7 @@ uint8_t MZ1E19_IO_QD(t_Z80CPU *cpu, bool read, uint16_t addr, uint8_t data)
// Locals.
uint8_t result = 0;
uint8_t prevPostEnd = mz1e19Ctrl->qd.postEndBlkDiag;
(void)prevPostEnd;
if (read)
{

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@@ -113,11 +113,11 @@ uint8_t MZ1R12_Init(t_Z80CPU *cpu, t_drvIFConfig *config)
// 0xF9 - MZ-1R12 S-Ram Set Low Address (W) or Read Data (R)
// 0xFA - MZ-1R12 S-Ram Write Date (W).
if ((idx & 0x00ff) == regStart)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1R12_IO_Reg1;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1R12_IO_Reg1;
if ((idx & 0x00ff) == (regStart + 1))
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1R12_IO_Reg2;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1R12_IO_Reg2;
if ((idx & 0x00ff) == (regStart + 2))
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1R12_IO_Reg3;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1R12_IO_Reg3;
}
// See if backup RAM file is present. No file then pesistance is disabled.
@@ -233,6 +233,9 @@ int MZ1R12_ProcessQueueResponses(t_Z80CPU *cpu, int boardNo)
if (!response.response.success)
;
break;
default:
break;
}
processedCount++;
}

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@@ -84,9 +84,9 @@ uint8_t MZ1R18_Init(t_Z80CPU *cpu, t_drvIFConfig *config)
// 0xEA - MZ-1R18 Ram File Data Register.
// 0xEB - MZ-1R18 Ram File Control Register.
if ((idx & 0x00ff) == 0xea)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1R18_DataReg;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1R18_DataReg;
if ((idx & 0x00ff) == 0xeb)
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc *) MZ1R18_CtrlReg;
cpu->_z80PSRAM->ioPtr[idx] = (t_MemoryFunc) MZ1R18_CtrlReg;
}
}

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@@ -702,6 +702,7 @@ uint8_t MZ700_IO_Debug(t_Z80CPU *cpu, bool read, uint16_t addr, uint8_t data)
{
// Locals.
uint8_t port = (uint8_t) addr & 0xff;
(void)port;
// No action on Read.
if (read)
@@ -844,7 +845,7 @@ uint8_t MZ700_Init(t_Z80CPU *cpu, t_FlashAppConfigHeader *appConfig, t_drvConfig
// Locals.
uint8_t result = 0;
char *fileBuffer = NULL;
bool isPhysical;
(void)fileBuffer;
// Call to check validity of interface for this driver.
if (ifName != NULL && config == NULL)
@@ -952,29 +953,28 @@ uint8_t MZ700_Init(t_Z80CPU *cpu, t_FlashAppConfigHeader *appConfig, t_drvConfig
}
for (int idx = 0; idx < MEMORY_PAGE_SIZE; idx++)
{
uint32_t memPtr = 0x00000000;
cpu->_z80PSRAM->memioPtr[idx] = memPtr;
cpu->_z80PSRAM->memioPtr[idx] = (t_MemoryFunc) NULL;
}
for (int idx = 0; idx < IO_PAGE_SIZE; idx++)
{
uint32_t ioPtr = 0x00000000;
t_MemoryFunc ioPtr = (t_MemoryFunc) NULL;
if (!isPhysical)
{
// RS-232C SIO ports (0xB0-0xB3) — return idle "not present" status in VIRTUAL mode.
// Prevents BASIC from hanging on SIO status polls when no RS-232C board is installed.
if ((idx & 0xff) >= 0xB0 && (idx & 0xff) <= 0xB3)
{
ioPtr = (t_MemoryFunc *) MZ700_IO_SIO_NotPresent;
ioPtr = (t_MemoryFunc) MZ700_IO_SIO_NotPresent;
}
// Memory mapping ports must be assigned to an internal function so that each I/O operation on these ports calls
// the function to change internal memory layout. As these ports are not 16bit sensitive, mask out the MSB.
if ((idx & 0xff) >= 0xE0 && (idx & 0xff) <= 0xE6)
{
ioPtr = (t_MemoryFunc *) MZ700_IO_MemoryBankPorts;
ioPtr = (t_MemoryFunc) MZ700_IO_MemoryBankPorts;
}
}
// Debug output handler.
if ((idx & 0xff) == 0x50) ioPtr = (t_MemoryFunc *) MZ700_IO_Debug;
if ((idx & 0xff) == 0x50) ioPtr = (t_MemoryFunc) MZ700_IO_Debug;
cpu->_z80PSRAM->ioPtr[idx] = ioPtr;
}

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@@ -236,6 +236,9 @@ void qdSioWriteControl(t_QdDrive *qd, t_sioChannel *ch, uint8_t val, bool isChan
}
}
// Forward declaration.
void qdUpdateStatus(t_QdDrive *qd);
// SIO Control Read
uint8_t qdSioReadControl(t_QdDrive *qd, t_sioChannel *ch, bool isChannelB)
{
@@ -335,6 +338,9 @@ int qdProcessDeviceResponses(t_QdDrive *qd, queue_t *responseQueue)
qd->intrq = true;
}
break;
default:
break;
}
processedCount++;
}
@@ -364,6 +370,7 @@ void qdUpdateStatus(t_QdDrive *qd)
{
homeReady = diskReady && spinUpOk && (qd->currentPosition < qd->diskSize - 256);
}
(void)homeReady;
// Allow a fixed time to elapse from Hunt start to hunt found, the BIOS has a max 220ms timer so
// we keep under this value.

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@@ -40,6 +40,7 @@
#include "intercore.h"
#include "drivers/Sharp/MZ.h"
#include "drivers/Sharp/RFS.h"
#include "ESP.h"
#ifndef MROMSIZE
#define MROMSIZE 4096 // Monitor ROM size (4K for MZ-700/MZ-80A).
@@ -98,15 +99,15 @@ uint8_t RFS_Init(t_Z80CPU *cpu, t_drvIFConfig *config)
rfsCtrl->upCntr = ((rfsCtrl->regCtrl & 0x20) >> 2) | ((rfsCtrl->regCtrl & 0x10) >> 2) | ((rfsCtrl->regCtrl & 0x08) >> 2);
// Install Memory I/O handlers.
cpu->_z80PSRAM->memioPtr[BNKCTRLRST] = (t_MemoryFunc *) RFS_IO_BNKCTRLRST;
cpu->_z80PSRAM->memioPtr[BNKCTRLDIS] = (t_MemoryFunc *) RFS_IO_BNKCTRLDIS;
cpu->_z80PSRAM->memioPtr[HWSPIDATA] = (t_MemoryFunc *) RFS_IO_HWSPIDATA;
cpu->_z80PSRAM->memioPtr[HWSPISTART] = (t_MemoryFunc *) RFS_IO_HWSPISTART;
cpu->_z80PSRAM->memioPtr[BNKSELMROM] = (t_MemoryFunc *) RFS_IO_BNKSELMROM;
cpu->_z80PSRAM->memioPtr[BNKSELUSER] = (t_MemoryFunc *) RFS_IO_BNKSELUSER;
cpu->_z80PSRAM->memioPtr[BNKCTRL] = (t_MemoryFunc *) RFS_IO_BNKCTRL;
cpu->_z80PSRAM->memioPtr[MEMSW] = (t_MemoryFunc *) RFS_IO_MEMSW;
cpu->_z80PSRAM->memioPtr[MEMSWR] = (t_MemoryFunc *) RFS_IO_MEMSWR;
cpu->_z80PSRAM->memioPtr[BNKCTRLRST] = (t_MemoryFunc) RFS_IO_BNKCTRLRST;
cpu->_z80PSRAM->memioPtr[BNKCTRLDIS] = (t_MemoryFunc) RFS_IO_BNKCTRLDIS;
cpu->_z80PSRAM->memioPtr[HWSPIDATA] = (t_MemoryFunc) RFS_IO_HWSPIDATA;
cpu->_z80PSRAM->memioPtr[HWSPISTART] = (t_MemoryFunc) RFS_IO_HWSPISTART;
cpu->_z80PSRAM->memioPtr[BNKSELMROM] = (t_MemoryFunc) RFS_IO_BNKSELMROM;
cpu->_z80PSRAM->memioPtr[BNKSELUSER] = (t_MemoryFunc) RFS_IO_BNKSELUSER;
cpu->_z80PSRAM->memioPtr[BNKCTRL] = (t_MemoryFunc) RFS_IO_BNKCTRL;
cpu->_z80PSRAM->memioPtr[MEMSW] = (t_MemoryFunc) RFS_IO_MEMSW;
cpu->_z80PSRAM->memioPtr[MEMSWR] = (t_MemoryFunc) RFS_IO_MEMSWR;
// Invoke the reset handler as it sets the initial state of the RFS board.
RFS_Reset(cpu);
@@ -331,6 +332,7 @@ uint8_t RFS_IO_BNKCTRLDIS(t_Z80CPU *cpu, bool read, uint16_t addr, uint8_t data)
{
// Disable bank control registers by resetting the coded latch.
uint8_t oldCntr = rfsCtrl->upCntr;
(void)oldCntr;
rfsCtrl->upCntr = (rfsCtrl->regCtrl >> 2) & 0x0E;
// debugf("BNKCTRLDIS: %s old=%d new=%d regCtrl=%02x\r\n", read ? "RD" : "WR", oldCntr, rfsCtrl->upCntr, rfsCtrl->regCtrl);
}
@@ -574,7 +576,7 @@ uint8_t RFS_IO_MEMSW(t_Z80CPU *cpu, bool read, uint16_t addr, uint8_t data)
// Exit if already switched.
if (rfsCtrl->memSwitch == true)
return;
return (result);
// Update memory map to reflect register change.
uint8_t offset = 0xC000 / MEMORY_BLOCK_SIZE;
@@ -609,7 +611,7 @@ uint8_t RFS_IO_MEMSWR(t_Z80CPU *cpu, bool read, uint16_t addr, uint8_t data)
// Exit if already reverted.
if (rfsCtrl->memSwitch == false)
return;
return (result);
// Update memory map to restore the change.
uint8_t offset = 0xC000 / MEMORY_BLOCK_SIZE;
@@ -646,6 +648,7 @@ void rfsSDCard(t_Z80CPU *cpu)
// Locals.
//
int noBytes;
(void)noBytes;
// Process any intercore responses.
if (rfsCtrl->loadPending)
@@ -677,7 +680,8 @@ void rfsSDCard(t_Z80CPU *cpu)
if (rfsCtrl->sd.trainingCnt == 0)
{
t_CoreMsg msg = {.type = MSG_READ_SECTOR, .context = rfsCtrl, .requestId = 0};
strncpy(msg.sectorOp.filename, SD_CARD_FILENAME, strlen(SD_CARD_FILENAME));
strncpy(msg.sectorOp.filename, SD_CARD_FILENAME, sizeof(msg.sectorOp.filename) - 1);
msg.sectorOp.filename[sizeof(msg.sectorOp.filename) - 1] = '\0';
msg.sectorOp.buffer = &sdRcvResponse[2];
msg.sectorOp.offset = rfsCtrl->sd.lbaAddr * SD_SECSIZE;
msg.sectorOp.size = SD_SECSIZE;

View File

@@ -214,6 +214,9 @@ int wd1773_processDeviceResponses(t_WD1773 *wd, queue_t *responseQueue)
wd->intrq = true;
}
break;
default:
break;
}
count++;
}
@@ -337,7 +340,7 @@ bool wd1773_init(t_WD1773 *wd, queue_t *req, queue_t *resp, const char *filename
{
wd->opState.loadPending = true;
t_CoreMsg msg = {.type = MSG_LOAD_FLOPPYDISK, .context = wd};
strncpy(msg.fileOp.filename, filename, MAX_IC_FILENAME_LEN);
snprintf(msg.fileOp.filename, MAX_IC_FILENAME_LEN, "%s", filename);
msg.fileOp.buffer = img;
msg.fileOp.size = wd->diskSize;
msg.fileOp.diskNo = 0;
@@ -812,7 +815,7 @@ void wd1773_writeSector(t_WD1773 *wd)
wd->opState.writePending = true;
t_CoreMsg msg = {.type = MSG_WRITE_SECTOR, .context = wd, .requestId = wd->opState.pendingWriteId};
strncpy(msg.sectorOp.filename, wd->filename, MAX_IC_FILENAME_LEN);
snprintf(msg.sectorOp.filename, MAX_IC_FILENAME_LEN, "%s", wd->filename);
msg.sectorOp.offset = offset;
msg.sectorOp.size = sectorSize;
msg.sectorOp.buffer = wd->diskImage + offset;
@@ -855,7 +858,7 @@ void wd1773_writeSector(t_WD1773 *wd)
wd->opState.writePending = true;
t_CoreMsg msg = {.type = MSG_WRITE_SECTOR, .context = wd, .requestId = wd->opState.pendingWriteId};
strncpy(msg.sectorOp.filename, wd->filename, MAX_IC_FILENAME_LEN);
snprintf(msg.sectorOp.filename, MAX_IC_FILENAME_LEN, "%s", wd->filename);
msg.sectorOp.offset = dataOffset;
msg.sectorOp.size = dataLength;
msg.sectorOp.buffer = wd->diskImage + dataOffset;
@@ -974,7 +977,7 @@ void wd1773_writeTrack(t_WD1773 *wd)
wd->opState.writePending = true;
t_CoreMsg msg = {.type = MSG_WRITE_SECTOR, .context = wd, .requestId = wd->opState.pendingWriteId};
strncpy(msg.sectorOp.filename, wd->filename, MAX_IC_FILENAME_LEN);
snprintf(msg.sectorOp.filename, MAX_IC_FILENAME_LEN, "%s", wd->filename);
msg.sectorOp.offset = offset;
msg.sectorOp.size = size;
msg.sectorOp.buffer = wd->diskImage + offset;
@@ -1014,7 +1017,7 @@ void wd1773_writeTrack(t_WD1773 *wd)
wd->opState.writePending = true;
t_CoreMsg msg = {.type = MSG_WRITE_SECTOR, .context = wd, .requestId = wd->opState.pendingWriteId};
strncpy(msg.sectorOp.filename, wd->filename, MAX_IC_FILENAME_LEN);
snprintf(msg.sectorOp.filename, MAX_IC_FILENAME_LEN, "%s", wd->filename);
msg.sectorOp.offset = dataStart;
msg.sectorOp.size = dataSize;
msg.sectorOp.buffer = wd->diskImage + dataStart;

View File

@@ -56,7 +56,9 @@
#define ESP_SEND_VER_INFO "INF"
// Macros
#ifndef NUMELEM
#define NUMELEM(a) sizeof(a) / sizeof(a[0])
#endif
#define ESP_VERSION 1.10
// Struct definition for t_ESP

View File

@@ -32,7 +32,9 @@
#define Z80CPU_H
//#pragma GCC optimize ("O3")
#ifndef Z80_STATIC
#define Z80_STATIC
#endif
#include "Z80.h"
#include <pico/stdlib.h>
#include <pico/printf.h>
@@ -160,7 +162,7 @@
} \
}
*/
#define SERVICE_REQUESTS() if (pio_1->irq & ((1u << 6) | (1u << 4)) != 0) \
#define SERVICE_REQUESTS() if ((pio_1->irq & ((1u << 6) | (1u << 4))) != 0) \
{ \
WAIT_TX_FIFO_EMPTY(pio_1, smCycle); \
if ((pio_1->irq & (1u << 6)) != 0) \
@@ -181,7 +183,7 @@
} \
}
//cpu->interrupt = true; \
//cpu->interrupt = true;
// Externally triggered tasks which the Z80CPU or drivers must execute.
enum Z80CPU_TASK_NAME
{

View File

@@ -66,7 +66,7 @@ extern mutex_t debugMutex;
#define debug_putchar(a) \
({ \
mutex_enter_blocking(&debugMutex); \
if (debugBuffer != NULL && (debugBufferSize + strlen(a)) < MAX_DEBUG_BUFFER_SIZE - 2) \
if (debugBuffer != NULL && (debugBufferSize + 1) < MAX_DEBUG_BUFFER_SIZE - 2) \
{ \
debugBuffer[debugBufferSize++] = a; \
} \
@@ -96,7 +96,7 @@ extern mutex_t debugMutex;
#define debug_putchar(a) \
({ \
mutex_enter_blocking(&debugMutex); \
if ((strlen(a) + strlen(debugBuffer)) < MAX_STATIC_DEBUG_BUFFER_SIZE - 100) \
if ((1 + strlen(debugBuffer)) < MAX_STATIC_DEBUG_BUFFER_SIZE - 100) \
{ \
debugBuffer[strlen(debugBuffer)] = a; \
debugWrite(debugBuffer, 1); \

View File

@@ -54,8 +54,12 @@
// Sharp QD values
#define MAX_QD_SIZE 61455U // Standard QD disk image size (~60KB)
#define MAX_QD_FORMAT_SIZE 64139U // Formatted size of a QD.
#ifndef ROTATION_US
#define ROTATION_US 200000ULL // 300 RPM spiral track rotation period
#endif
#ifndef PULSE_WIDTH_US
#define PULSE_WIDTH_US 2000ULL // Index pulse width (1% of rotation)
#endif
#define MAX_HUNT_TIME_US 200000ULL // Maximum time a hunt for next block should take.
#define QD_MARK_FLAG 0x00 // SYNC marker byte.
#define QD_SYNC_FLAG 0x16 // SYNC byte.

View File

@@ -61,7 +61,9 @@
#define FLASH_MAX_ROM_FILENAME_SIZE 256 // Maximum size of a ROM filename including path.
#define FLASH_MAX_ROM_IMAGES 64 // Maximum number of ROMS which can be stored in FlashRAM (subject to space).
#define FLASH_MAX_ROM_IMAGE_SIZE (512 * 1024) // Maximum single ROM image size.
#ifndef FLASH_SECTOR_SIZE
#define FLASH_SECTOR_SIZE (4 * 1024) // Same as FW_SECTOR_SIZE but may not be defined in all includes.
#endif
#define FLASH_APP_MAX_JSON_SIZE (64 * 1024) // 64K to store minified JSON configuration.
//
#define FLASH_APP_BOOTLOADER_SIZE (128 * 1024) // 128K Bootloader App.

View File

@@ -179,7 +179,7 @@ extern t_doubleValuePair voltageMap[];
uint8_t *FLASH_CONTENTS = (uint8_t *) (HW_FLASHADDR_START);
// Flash RAM. Overlay the configuration structure to enable access to elements.
static t_FlashLayout *flashLayout = (t_FlashLayout *) (HW_FLASHADDR_START);
static t_FlashLayout *flashLayout __attribute__((unused)) = (t_FlashLayout *) (HW_FLASHADDR_START);
static t_FlashConfigHeader *flashConfigHeader = (t_FlashConfigHeader *) (FLASH_START_CONFIG_ADDR);
static t_FlashPartitionHeader *flashPart = (t_FlashPartitionHeader *) (FLASH_START_PARTITION_TABLE_ADDR);
static t_FlashAppConfigHeader *flashAppConfigHeader;
@@ -188,9 +188,9 @@ static t_FlashAppConfigHeader *flashAppConfigHeader;
static t_Z80CPU *z80CPU = NULL;
static size_t psramSize;
// Queue definitions (global, shared by ALL devices)
static queue_t requestQueue;
static queue_t responseQueue;
// Queue definitions (global, shared by ALL devices — referenced via z80CPU->requestQueue/responseQueue)
static queue_t requestQueue __attribute__((unused));
static queue_t responseQueue __attribute__((unused));
// Max number of pending writes (e.g., number of unique files/disks)
#define MAX_PENDING_WRITES 4
@@ -523,8 +523,8 @@ void dumpStructs(t_Z80CPU *cpu, int whichStruct)
}
if (addr < MEMORY_PAGE_SIZE)
{
uint32_t memPtr = z80CPU->_z80PSRAM->memioPtr[addr];
debugf("%08x ", memPtr);
uintptr_t memPtr = (uintptr_t)z80CPU->_z80PSRAM->memioPtr[addr];
debugf("%08x ", (uint32_t)memPtr);
}
for (int flush = 0; flush < 100; flush++)
pollUSBtoUART();
@@ -544,8 +544,8 @@ void dumpStructs(t_Z80CPU *cpu, int whichStruct)
}
if (addr < IO_PAGE_SIZE)
{
uint32_t memPtr = z80CPU->_z80PSRAM->ioPtr[addr];
debugf("%08x ", memPtr);
uintptr_t memPtr = (uintptr_t)z80CPU->_z80PSRAM->ioPtr[addr];
debugf("%08x ", (uint32_t)memPtr);
}
for (int flush = 0; flush < 100; flush++)
pollUSBtoUART();
@@ -680,7 +680,7 @@ bool processJSONConfig(uint8_t cfgApp)
// Read file from ESP32. Request the json config file for the specified configuration.
watchdog_update();
debugf("CFG: Reading %s from ESP32...\r\n", CONFIG_FILE_NAME);
fileSize = ESP_readFile(CONFIG_FILE_NAME, NULL, NULL, NULL, (uint8_t *) &jsonBuffer, (FLASH_APP_MAX_JSON_SIZE * 2) - 1, false, 0);
fileSize = ESP_readFile(CONFIG_FILE_NAME, NULL, NULL, NULL, (uint8_t **) &jsonBuffer, (FLASH_APP_MAX_JSON_SIZE * 2) - 1, false, 0);
if (fileSize == 0)
{
debugf("Error: Failed to read file %s\n", CONFIG_FILE_NAME);
@@ -694,10 +694,10 @@ bool processJSONConfig(uint8_t cfgApp)
jsonBuffer[fileSize] = '\0';
// Minify the string before processing. The minified string will be stored in FlashRAM.
cJSON_Minify(jsonBuffer);
cJSON_Minify((char *)jsonBuffer);
// Parse the JSON data
jsonRoot = cJSON_Parse(jsonBuffer);
jsonRoot = cJSON_Parse((const char *)jsonBuffer);
if (!jsonRoot)
{
debugf("Error: JSON parsing failed: %s\n", cJSON_GetErrorPtr());
@@ -719,7 +719,7 @@ bool processJSONConfig(uint8_t cfgApp)
// This downloads ROM files (up to 512K each) and writes them to flash.
watchdog_update();
debugf("CFG: Storing Z80 config + ROM files...\r\n");
if (!Z80CPU_parseJSONStore(z80CPU, rp2350, cfgApp, jsonBuffer))
if (!Z80CPU_parseJSONStore(z80CPU, rp2350, cfgApp, (char *)jsonBuffer))
{
debugf("Error: Cannot parse JSON, error in configuration.\r\n");
cJSON_Delete(jsonRoot);
@@ -1000,7 +1000,7 @@ void processInterCoreCommands(void)
watchdog_update();
qmsg.fileOp.buffer = bufBefore; // Reset in case realloc changed it on a failed partial read.
plogf("a%d>", attempt);
bytesXfer = ESP_readFloppyDiskFile(qmsg.fileOp.filename, NULL, NULL, NULL, &qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0, qmsg.fileOp.diskNo);
bytesXfer = ESP_readFloppyDiskFile(qmsg.fileOp.filename, NULL, NULL, NULL, (uint8_t **)&qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0, qmsg.fileOp.diskNo);
plogf("r%lu>", bytesXfer);
if (bytesXfer > 0)
break;
@@ -1064,7 +1064,7 @@ void processInterCoreCommands(void)
for (int attempt = 0; attempt < 10; attempt++)
{
qmsg.fileOp.buffer = bufBefore; // Reset in case realloc changed it on a failed partial read.
bytesXfer = ESP_readQuickDiskFile(qmsg.fileOp.filename, NULL, NULL, NULL, &qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0);
bytesXfer = ESP_readQuickDiskFile(qmsg.fileOp.filename, NULL, NULL, NULL, (uint8_t **)&qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0);
if (bytesXfer > 0)
break;
debugf("QD_LOAD: attempt %d failed, retrying in 500ms...\r\n", attempt);
@@ -1090,7 +1090,7 @@ void processInterCoreCommands(void)
for (int attempt = 0; attempt < 10; attempt++)
{
qmsg.fileOp.buffer = bufBefore;
bytesXfer = ESP_readRamFile(qmsg.fileOp.filename, NULL, NULL, NULL, &qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0);
bytesXfer = ESP_readRamFile(qmsg.fileOp.filename, NULL, NULL, NULL, (uint8_t **)&qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0);
if (bytesXfer > 0)
break;
watchdog_update();
@@ -1114,7 +1114,7 @@ void processInterCoreCommands(void)
for (int attempt = 0; attempt < 10; attempt++)
{
qmsg.fileOp.buffer = bufBefore;
bytesXfer = ESP_readFile(qmsg.fileOp.filename, NULL, NULL, NULL, &qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0);
bytesXfer = ESP_readFile(qmsg.fileOp.filename, NULL, NULL, NULL, (uint8_t **)&qmsg.fileOp.buffer, qmsg.fileOp.size, true, 0);
if (bytesXfer > 0)
break;
watchdog_update();

View File

@@ -1 +1 @@
3.258
3.263

View File

@@ -1 +1 @@
1.104
1.105

View File

@@ -452,6 +452,7 @@ void writeUSB(uint8_t itf)
// Locals.
t_UartData *ud = &UART_DATA[itf];
const t_UartId *ui = &UART_ID[itf];
(void)ui;
#if defined(BOOTLOADER)
if (itf != ESP_CHANNEL || (itf == ESP_CHANNEL && ud->fwUpdateMode == false))
@@ -505,6 +506,9 @@ int debugRead(char *buf, int max_len)
}
#endif
// Forward declaration.
void usb_cdc_process(uint8_t itf);
// Debug channel - a channel within the USB device purely for sending debug information.
//
#if defined(DEBUG)
@@ -514,7 +518,8 @@ int debugWrite(char *dbgMsg, int len)
static int syncCnt = 1;
int maxLen = 0;
t_UartData *ud = &UART_DATA[DEBUG_CHANNEL];
t_UartId *ui = &UART_ID[DEBUG_CHANNEL];
const t_UartId *ui = &UART_ID[DEBUG_CHANNEL];
(void)ui;
// Only log if there is actually a message?
if (len > 0)
@@ -643,7 +648,8 @@ int uartReadFrame(char *msg)
int result = 0;
#ifndef BOOTLOADER
t_UartData *ud = &UART_DATA[ESP_CHANNEL];
t_UartId *ui = &UART_ID[ESP_CHANNEL];
const t_UartId *ui = &UART_ID[ESP_CHANNEL];
(void)ui;
// Ensure IRQ for this channel is disabled.
//irq_set_enabled(ui->irq, false);
@@ -696,6 +702,7 @@ bool uartWriteFrame(const char *msg, int len)
char charToSend;
const t_UartId *ui = &UART_ID[ESP_CHANNEL];
t_UartData *ud = &UART_DATA[ESP_CHANNEL];
(void)ud;
//if(ui->inst != NULL && mutex_try_enter(&ud->uartMutex, NULL))
if (ui->inst != NULL)
@@ -750,6 +757,7 @@ bool uartWriteOOB(uint32_t oobCmd)
char charToSend;
const t_UartId *ui = &UART_ID[ESP_CHANNEL];
t_UartData *ud = &UART_DATA[ESP_CHANNEL];
(void)ud;
//if(ui->inst != NULL && mutex_try_enter(&ud->uartMutex, NULL))
if (ui->inst != NULL)
@@ -794,7 +802,8 @@ int uartReadCmd(char *msg)
int result = 0;
#ifndef BOOTLOADER
t_UartData *ud = &UART_DATA[ESP_CHANNEL];
t_UartId *ui = &UART_ID[ESP_CHANNEL];
const t_UartId *ui = &UART_ID[ESP_CHANNEL];
(void)ui;
// Ensure IRQ for this channel is disabled.
//irq_set_enabled(ui->irq, false);
@@ -1047,7 +1056,7 @@ void writeUART(uint8_t itf)
if (itf >= CFG_TUD_CDC)
return;
t_UartId *ui = &UART_ID[itf];
const t_UartId *ui = &UART_ID[itf];
t_UartData *ud = &UART_DATA[itf];
if (ui->inst != NULL && ud->usbPos && mutex_try_enter(&ud->usbMutex, NULL))
@@ -1125,7 +1134,7 @@ void updateFlashSectors(uint32_t flashAddr, uint8_t *src, uint32_t sectors)
flash_range_erase(flashAddr + (idx * FLASH_PARTITION_SIZE), FW_SECTOR_SIZE);
// Program a sector from data held at src.
flash_range_program(flashAddr + (idx * FLASH_PARTITION_SIZE), &flashbuf, FW_SECTOR_SIZE);
flash_range_program(flashAddr + (idx * FLASH_PARTITION_SIZE), (const uint8_t *)flashbuf, FW_SECTOR_SIZE);
}
// Restore the interrupts.
@@ -1149,7 +1158,7 @@ void updateFlashPartitionHeader(t_FlashPartitionHeader *header)
// Program the partition header contents into flash, normally in page (256 byte) blocks, but use a full sector which
// is the size of the partition table header.
flash_range_program(FLASH_HEADER_OFFSET, &flashbuf, FW_SECTOR_SIZE);
flash_range_program(FLASH_HEADER_OFFSET, (const uint8_t *)flashbuf, FW_SECTOR_SIZE);
return;
}
@@ -1290,14 +1299,18 @@ void pollUSBtoUART(void)
{
// Extract the programming address from the frame.
int bufIdx = 0;
flashPartitionInstance.addr = (uint32_t) (ud->fromUartBuffer[bufIdx++] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx++] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx++] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx++]);
flashPartitionInstance.size = (uint32_t) (ud->fromUartBuffer[bufIdx++] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx++] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx++] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx++]);
updInstance = (uint8_t) ((uint32_t) (ud->fromUartBuffer[bufIdx++] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx++] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx++] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx++]));
flashPartitionInstance.chksum = (uint32_t) (ud->fromUartBuffer[bufIdx++] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx++] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx++] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx++]);
flashPartitionInstance.addr = (uint32_t) (ud->fromUartBuffer[bufIdx] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx + 1] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx + 2] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx + 3]);
bufIdx += 4;
flashPartitionInstance.size = (uint32_t) (ud->fromUartBuffer[bufIdx] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx + 1] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx + 2] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx + 3]);
bufIdx += 4;
updInstance = (uint8_t) ((uint32_t) (ud->fromUartBuffer[bufIdx] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx + 1] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx + 2] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx + 3]));
bufIdx += 4;
flashPartitionInstance.chksum = (uint32_t) (ud->fromUartBuffer[bufIdx] << 24) | (uint32_t) (ud->fromUartBuffer[bufIdx + 1] << 16) |
(uint32_t) (ud->fromUartBuffer[bufIdx + 2] << 8) | (uint32_t) (ud->fromUartBuffer[bufIdx + 3]);
bufIdx += 4;
// If instance is given and valid, we ignore the address and use static values. If instance is 0 or not valid, then use the address and instance 1 (none standard, for testing).
if (updInstance == FLASH_APP_INSTANCE1)
@@ -1315,17 +1328,17 @@ void pollUSBtoUART(void)
updInstance = FLASH_APP_INSTANCE1;
// Get version and licensing data.
strcpy(flashPartitionInstance.license, &ud->fromUartBuffer[bufIdx]);
strcpy(flashPartitionInstance.license, (const char *)&ud->fromUartBuffer[bufIdx]);
bufIdx += strlen(flashPartitionInstance.license) + 1;
strcpy(flashPartitionInstance.author, &ud->fromUartBuffer[bufIdx]);
strcpy(flashPartitionInstance.author, (const char *)&ud->fromUartBuffer[bufIdx]);
bufIdx += strlen(flashPartitionInstance.author) + 1;
strcpy(flashPartitionInstance.description, &ud->fromUartBuffer[bufIdx]);
strcpy(flashPartitionInstance.description, (const char *)&ud->fromUartBuffer[bufIdx]);
bufIdx += strlen(flashPartitionInstance.description) + 1;
strcpy(flashPartitionInstance.version, &ud->fromUartBuffer[bufIdx]);
strcpy(flashPartitionInstance.version, (const char *)&ud->fromUartBuffer[bufIdx]);
bufIdx += strlen(flashPartitionInstance.version) + 1;
strcpy(flashPartitionInstance.versionDate, &ud->fromUartBuffer[bufIdx]);
strcpy(flashPartitionInstance.versionDate, (const char *)&ud->fromUartBuffer[bufIdx]);
bufIdx += strlen(flashPartitionInstance.versionDate) + 1;
strcpy(flashPartitionInstance.copyright, &ud->fromUartBuffer[bufIdx]);
strcpy(flashPartitionInstance.copyright, (const char *)&ud->fromUartBuffer[bufIdx]);
bufIdx += strlen(flashPartitionInstance.copyright) + 1;
// If checksum matches, verify the programming address, then we can send an OK, otherwise ignore packet.

View File

@@ -101,6 +101,7 @@ const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid)
{
const char *str;
char serial[USBD_STR_SERIAL_LEN];
(void)serial;
if (index >= sizeof(usbdDescStr) / sizeof(usbdDescStr[0]))
return NULL;

View File

@@ -1 +1 @@
3.186
3.189