337 lines
25 KiB
VHDL
337 lines
25 KiB
VHDL
-- ZPU
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--
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-- Copyright 2004-2008 oharboe - <20>yvind Harboe - oyvind.harboe@zylin.com
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-- Copyright 2018-2019 psmart - Philip Smart
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--
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-- The FreeBSD license
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- The views and conclusions contained in the software and documentation
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-- are those of the authors and should not be interpreted as representing
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-- official policies, either expressed or implied, of the ZPU Project.
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library ieee;
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library pkgs;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.zpu_pkg.all;
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package zpu_soc_pkg is
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-- Choose which CPU to instantiate depending on requirements. Warning, keep the below 5 lines exactly the same
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-- or ensure you update the Makefile as they are set by the Makefile to generate zpu_soc_pkg.vhd
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--
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constant ZPU_SMALL : integer := 0; -- Use the SMALL CPU.
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constant ZPU_MEDIUM : integer := 0; -- Use the MEDIUM CPU.
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constant ZPU_FLEX : integer := 0; -- Use the FLEX CPU.
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constant ZPU_EVO : integer := 1; -- Use the EVOLUTION CPU.
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constant ZPU_EVO_MINIMAL : integer := 0; -- Use the Minimalist EVOLUTION CPU.
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-- Frequencies for the various boards.
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--
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constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board
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constant SYSCLK_QMV_FREQ : integer := 100000000; -- QMTECH Cyclone V FPGA Board
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constant SYSCLK_DE0_FREQ : integer := 100000000; -- DE0-Nano FPGA Board
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constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board
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constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board
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-- ID for the various ZPU models. The format is 2 bytes, MSB=<Model>, LSB=<Revision>
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constant ZPU_ID_SMALL : integer := 16#0101#; -- ID for the ZPU Small in this package.
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constant ZPU_ID_MEDIUM : integer := 16#0201#; -- ID for the ZPU Medium in this package.
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constant ZPU_ID_FLEX : integer := 16#0301#; -- ID for the ZPU Flex in this package.
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constant ZPU_ID_EVO : integer := 16#0401#; -- ID for the ZPU Evo in this package.
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constant ZPU_ID_EVO_MINIMAL : integer := 16#0501#; -- ID for the ZPU Evo Minimal in this package.
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-- EVO CPU specific configuration.
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constant MAX_EVO_L1CACHE_BITS : integer := 5; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
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constant MAX_EVO_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
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constant MAX_EVO_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits.
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constant MAX_EVO_MIN_L1CACHE_BITS : integer := 4; -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
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constant MAX_EVO_MIN_L2CACHE_BITS : integer := 12; -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
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constant MAX_EVO_MIN_MXCACHE_BITS : integer := 3; -- Maximum size of the memory transaction cache governed by the number of bits.
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-- Settings for various IO devices.
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--
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constant MAX_RX_FIFO_BITS : integer := 8; -- Size of UART RX Fifo.
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constant MAX_TX_FIFO_BITS : integer := 8; -- Size of UART TX Fifo.
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constant MAX_UART_DIVISOR_BITS : integer := 16; -- Maximum number of bits for the UART clock rate generator divisor.
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constant INTR_MAX : integer := 16; -- Maximum number of interrupt inputs.
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constant SYSTEM_FREQUENCY : integer := 100000000; -- Default system clock frequency if not overriden by top level.
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-- constant SYSCLK_FREQUENCY : integer := 1000; -- System clock in MHz x 10
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-- constant SYSCLK_HZ : integer := SYSCLK_FREQUENCY*100000; -- System clock in Hertz
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-- constant UART_RESET_COUNT : integer := ((SYSCLK_FREQUENCY*100000)/300)*8; -- Count of system clock ticks for a UART break to be recognised as a system reset.
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-- SoC specific options.
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--
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constant SOC_IMPL_WB : boolean := EVO_USE_WB_BUS; -- Implement the Wishbone bus and all enabled devices.
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constant SOC_IMPL_WB_I2C : boolean := true; -- Implement I2C over wishbone interface.
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constant SOC_IMPL_WB_SDRAM : boolean := true; -- Implement SDRAM over wishbone interface.
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constant SOC_IMPL_TIMER1 : boolean := true; -- Implement Timer 1, an array of prescaled downcounter with enable.
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constant SOC_TIMER1_COUNTERS : integer := 0; -- Number of downcounters in Timer 1. Value is a 2^ array of counters, so 0 = 1 counter.
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constant SOC_IMPL_PS2 : boolean := true; -- Implement PS2 keyboard and mouse hardware.
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constant SOC_IMPL_SPI : boolean := true; -- Implement Serial Peripheral Inteface(s).
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constant SOC_IMPL_SD : boolean := true; -- Implement SD Card interface.
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constant SOC_SD_DEVICES : integer := 1; -- Number of SD card channels implemented.
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constant SOC_IMPL_INTRCTL : boolean := true; -- Implement the prioritised interrupt controller.
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constant SOC_IMPL_IOCTL : boolean := false; -- Implement the IOCTL controller (specific to the MiSTer project).
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constant SOC_IMPL_SOCCFG : boolean := true; -- Implement the SoC Configuration information registers.
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constant SOC_IMPL_BRAM : boolean := true; -- Implement BRAM for the BIOS and initial Stack.
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constant SOC_IMPL_RAM : boolean := false; -- Implement RAM using BRAM, typically for Application programs seperate to BIOS.
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constant SOC_IMPL_DRAM : boolean := false; -- Implement Dynamic RAM and controller.
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constant SOC_IMPL_INSN_BRAM : boolean := true; -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory.
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constant SOC_MAX_ADDR_BRAM_BIT : integer := 16; -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same.
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constant SOC_ADDR_BRAM_START : integer := 0; -- Start address of BRAM.
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constant SOC_ADDR_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT); -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
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constant SOC_MAX_ADDR_RAM_BIT : integer := 23; -- Max address bit of the System RAM.
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constant SOC_ADDR_RAM_START : integer := 16777216; -- Start address of RAM.
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constant SOC_ADDR_RAM_END : integer := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
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constant SOC_MAX_ADDR_INSN_BRAM_BIT: integer := SOC_MAX_ADDR_BRAM_BIT; -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words.
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constant SOC_ADDR_INSN_BRAM_START : integer := 0; -- Start address of dedicated instrution BRAM.
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constant SOC_ADDR_INSN_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_INSN_BRAM_BIT); -- End address of dedicated instruction BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
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constant SOC_RESET_ADDR_CPU : integer := SOC_ADDR_BRAM_START; -- Initial address to start execution from after reset.
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constant SOC_START_ADDR_MEM : integer := SOC_ADDR_BRAM_START; -- Start location of program memory (BRAM/ROM/RAM).
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constant SOC_STACK_ADDR : integer := SOC_ADDR_BRAM_END - 8; -- Stack start address (BRAM/RAM).
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constant SOC_ADDR_IO_START : integer := (2**(maxAddrBit-WB_ACTIVE)) - (2**maxIOBit); -- Start address of the Evo Direct Memory Mapped IO region.
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constant SOC_ADDR_IO_END : integer := (2**(maxAddrBit-WB_ACTIVE)) - 1; -- End address of the Evo Direct Memory Mapped IO region.
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constant SOC_WB_IO_START : integer := 32505856; -- Start address of IO range.
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constant SOC_WB_IO_END : integer := 33554431; -- End address of IO range.
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-- Ranges used throughout the SOC source.
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subtype ADDR_BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0; -- Address range of the onboard B(lock)RAM - 1 byte aligned
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subtype ADDR_BIT_BRAM_16BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 1; -- Address range of the onboard B(lock)RAM - 2 bytes aligned
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subtype ADDR_BIT_BRAM_32BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto minAddrBit; -- Address range of the onboard B(lock)RAM - 4 bytes aligned
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subtype ADDR_BIT_RAM_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 0; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
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subtype ADDR_BIT_RAM_16BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto 1; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
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subtype ADDR_BIT_RAM_32BIT_RANGE is natural range SOC_MAX_ADDR_RAM_BIT-1 downto minAddrBit; -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
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-- subtype ADDR_DECODE_BRAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_BRAM_BIT;-- Decode range for selection of the BRAM within the address space.
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-- subtype ADDR_DECODE_RAM_RANGE is natural range maxAddrBit-1 downto SOC_MAX_ADDR_RAM_BIT; -- Decode range for selection of the RAM within the address space.
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subtype IO_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
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-- subtype WB_IO_DECODE_RANGE is natural range maxAddrBit-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
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-- Start byte address of stack for non-EVO CPU. Point to top of BRAM or a dedicated blcck of RAM - 2*words. Once booted the stack frame can be shifted to any memory location.
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-- constant spStart : std_logic_vector(maxAddrBit-1 downto 0) := std_logic_vector(to_unsigned((2**(SOC_MAX_ADDR_BRAM_BIT))-8, maxAddrBit));
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-- Device options
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type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards.
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------------------------------------------------------------
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-- constants
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------------------------------------------------------------
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constant YES : std_logic := '1';
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constant NO : std_logic := '0';
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constant HI : std_logic := '1';
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constant LO : std_logic := '0';
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constant ONE : std_logic := '1';
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constant ZERO : std_logic := '0';
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constant HIZ : std_logic := 'Z';
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------------------------------------------------------------
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-- functions
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------------------------------------------------------------
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-- Find the maximum of two integers.
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function IntMax(a : in integer; b : in integer) return integer;
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------------------------------------------------------------
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-- records
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------------------------------------------------------------
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------------------------------------------------------------
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-- components
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------------------------------------------------------------
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component dualport_ram is
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port (
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clk : in std_logic;
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memAWriteEnable : in std_logic;
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memAAddr : in std_logic_vector(ADDR_32BIT_RANGE);
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memAWrite : in std_logic_vector(WORD_32BIT_RANGE);
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memARead : out std_logic_vector(WORD_32BIT_RANGE);
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memBWriteEnable : in std_logic;
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memBAddr : in std_logic_vector(ADDR_32BIT_RANGE);
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memBWrite : in std_logic_vector(WORD_32BIT_RANGE);
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memBRead : out std_logic_vector(WORD_32BIT_RANGE)
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);
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end component;
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component cacheL2 is
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generic (
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MAX_CACHE_BITS : integer := 12
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);
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port (
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clk : in std_logic;
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areset : in std_logic := '0';
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memAWriteEnable : in std_logic;
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memAAddr : in std_logic_vector(MAX_CACHE_BITS-3 downto 0);
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memAWrite : in std_logic_vector(55 downto 0);
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memBWriteEnable : in std_logic;
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memBAddr : in std_logic_vector(MAX_CACHE_BITS-3 downto 0);
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memBWrite : in std_logic_vector(55 downto 0);
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memARead : out std_logic_vector(55 downto 0);
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memBRead : out std_logic_vector(55 downto 0)
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);
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end component;
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component dpram
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generic (
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init_file : string;
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widthad_a : natural;
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width_a : natural;
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widthad_b : natural;
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width_b : natural;
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outdata_reg_a : string := "UNREGISTERED";
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outdata_reg_b : string := "UNREGISTERED"
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);
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port (
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clock_a : in std_logic := '1';
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clocken_a : in std_logic := '1';
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address_a : in std_logic_vector (widthad_a-1 downto 0);
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data_a : in std_logic_vector (width_a-1 downto 0);
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wren_a : in std_logic := '0';
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q_a : out std_logic_vector (width_a-1 downto 0);
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clock_b : in std_logic;
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clocken_b : in std_logic := '1';
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address_b : in std_logic_vector (widthad_b-1 downto 0);
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data_b : in std_logic_vector (width_b-1 downto 0);
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wren_b : in std_logic := '0';
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q_b : out std_logic_vector (width_b-1 downto 0)
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);
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end component;
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component signed_divider is
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port (
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clk : in std_logic;
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ena : in std_logic;
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z : in unsigned(63 downto 0);
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d : in unsigned(WORD_32BIT_RANGE);
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q : out signed(63 downto 0);
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s : out signed(63 downto 0)
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);
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end component;
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component unsigned_divider is
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port (
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clk : in std_logic;
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ena : in std_logic;
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z : in unsigned(63 downto 0);
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d : in unsigned(WORD_32BIT_RANGE);
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q : out unsigned(WORD_32BIT_RANGE);
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s : out unsigned(WORD_32BIT_RANGE);
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div0 : out std_logic;
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ovf : out std_logic
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);
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end component;
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component qdiv is
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port (
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dividend : in signed(WORD_32BIT_RANGE);
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divisor : in signed(WORD_32BIT_RANGE);
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start : in std_logic;
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clk : in std_logic;
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quotient_out : out signed(WORD_32BIT_RANGE);
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complete : out std_logic
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);
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end component;
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component SDCard is
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generic (
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FREQ_G : real := 100.0; -- Master clock frequency (MHz).
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INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
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SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
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BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
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CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
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);
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port (
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-- Host-side interface signals.
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clk_i : in std_logic; -- Master clock.
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reset_i : in std_logic := NO; -- active-high, synchronous reset.
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rd_i : in std_logic := NO; -- active-high read block request.
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wr_i : in std_logic := NO; -- active-high write block request.
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continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
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addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
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data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
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data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
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busy_o : out std_logic; -- High when controller is busy performing some operation.
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hndShk_i : in std_logic; -- High when host has data to give or has taken data.
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hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
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error_o : out std_logic_vector(15 downto 0) := (others => NO);
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-- I/O signals to the external SD card.
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cs_bo : out std_logic := HI; -- Active-low chip-select.
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sclk_o : out std_logic := LO; -- Serial clock to SD card.
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mosi_o : out std_logic := HI; -- Serial data output to SD card.
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miso_i : in std_logic := ZERO -- Serial data input from SD card.
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);
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end component;
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component sdram_v is
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port (
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-- interface to the MT48LC16M16 chip
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sd_clk : in std_logic; -- sdram is accessed at 128MHz
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sd_rst : in std_logic; -- reset the sdram controller.
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sd_cke : out std_logic; -- clock enable.
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sd_dq : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
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sd_addr : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
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sd_dqm : out std_logic_vector(1 downto 0); -- two byte masks
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sd_ba : out std_logic_vector(1 downto 0); -- two banks
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sd_cs_n : out std_logic; -- a single chip select
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sd_we_n : out std_logic; -- write enable
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sd_ras_n : out std_logic; -- row address select
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sd_cas_n : out std_logic; -- columns address select
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sd_ready : out std_logic; -- sd ready.
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-- cpu/chipset interface
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wb_clk : in std_logic; -- 32MHz chipset clock to which sdram state machine is synchonized
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wb_dat_i : in std_logic_vector(31 downto 0); -- data input from chipset/cpu
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wb_dat_o : out std_logic_vector(31 downto 0); -- data output to chipset/cpu
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wb_ack : out std_logic;
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wb_adr : in std_logic_vector(23 downto 0); -- lower 2 bits are ignored.
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wb_sel : in std_logic_vector(3 downto 0);
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wb_cti : in std_logic_vector(2 downto 0); -- cycle type.
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wb_stb : in std_logic;
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wb_cyc : in std_logic; -- cpu/chipset requests cycle
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wb_we : in std_logic -- cpu/chipset requests write
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);
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end component;
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end zpu_soc_pkg;
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package body zpu_soc_pkg is
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-- Find the maximum of two integers.
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function IntMax(a : in integer; b : in integer) return integer is
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begin
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if a > b then
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return a;
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else
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return b;
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end if;
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return a;
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end function IntMax;
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end package body;
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