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This commit is contained in:
Philip Smart
2019-11-17 21:52:33 +00:00
parent c89039370b
commit 929f495445
20 changed files with 1465 additions and 912 deletions
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33
.gitignore vendored
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@@ -3,3 +3,36 @@
.gradle
/Releases
/.nb-gradle/
*.bin
*.dmp
*.elf
*.lss
*.map
*.rpt
*.srec
*.swp
*.zpu
*.log
*.done
*.smsg
*.summary
*.jdi
*.pin
*.out.sdc
*.sof
*.sld
*.rbf
*.qws
*.sav
*.pof
*.qdf
*.srf
c5_pin_model_dump.txt
build/db/
build/incremental_db/
build/output_files/
build/simulation/
software/apps/*/*_obj/
software/zputa/zpu_obj/
software/iocp/iocp_obj/
software/build/

792
build/DE0_nano_zpu.qsf
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@@ -2,311 +2,310 @@
# Build by Terasic System Builder
#============================================================
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA4U23C6
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA4U23C6
set_global_assignment -name TOP_LEVEL_ENTITY "DE0_nano_zpu"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:58:03 DECEMBER 18,2014"
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name SDC_FILE DE0_nano_zpu.sdc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:58:03 DECEMBER 18,2014"
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
#============================================================
# ADC
#============================================================
set_location_assignment PIN_U9 -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
set_location_assignment PIN_AG10 -to ARDUINO_IO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
set_location_assignment PIN_AG10 -to ARDUINO_IO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
#============================================================
# CLOCK
#============================================================
#set_location_assignment PIN_V11 -to FPGA_CLK1_50
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
#set_location_assignment PIN_R8 -to CLOCK_50
set_location_assignment PIN_V11 -to CLOCK_50
set_location_assignment PIN_V11 -to CLOCK_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
#============================================================
# HPS
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
#============================================================
# KEY
#============================================================
set_location_assignment PIN_AH17 -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
set_location_assignment PIN_AH17 -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
#============================================================
# LED
#============================================================
set_location_assignment PIN_W15 -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
set_location_assignment PIN_W15 -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
#============================================================
# SW
#============================================================
set_location_assignment PIN_L10 -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_location_assignment PIN_L9 -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_location_assignment PIN_H6 -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_location_assignment PIN_H5 -to SW[3]
#============================================================
set_location_assignment PIN_L10 -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_location_assignment PIN_L9 -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_location_assignment PIN_H6 -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_location_assignment PIN_H5 -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
#============================================================
# GPIO_0, GPIO connect to GPIO Default
#============================================================
set_location_assignment PIN_V12 -to GPIO_0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
set_location_assignment PIN_AF7 -to GPIO_0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
set_location_assignment PIN_W12 -to GPIO_0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
set_location_assignment PIN_AF8 -to GPIO_0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
set_location_assignment PIN_Y8 -to GPIO_0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
set_location_assignment PIN_AB4 -to GPIO_0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
set_location_assignment PIN_W8 -to GPIO_0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
set_location_assignment PIN_Y4 -to GPIO_0[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
set_location_assignment PIN_Y5 -to GPIO_0[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
set_location_assignment PIN_U11 -to GPIO_0[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
set_location_assignment PIN_T8 -to GPIO_0[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
set_location_assignment PIN_T12 -to GPIO_0[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
set_location_assignment PIN_AH5 -to GPIO_0[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
set_location_assignment PIN_AH6 -to GPIO_0[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
set_location_assignment PIN_AH4 -to GPIO_0[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
set_location_assignment PIN_AG5 -to GPIO_0[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
set_location_assignment PIN_AH3 -to GPIO_0[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
set_location_assignment PIN_AH2 -to GPIO_0[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
set_location_assignment PIN_AF4 -to GPIO_0[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
set_location_assignment PIN_AG6 -to GPIO_0[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
set_location_assignment PIN_AF5 -to GPIO_0[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
set_location_assignment PIN_AE4 -to GPIO_0[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
set_location_assignment PIN_T13 -to GPIO_0[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
set_location_assignment PIN_T11 -to GPIO_0[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
set_location_assignment PIN_AE7 -to GPIO_0[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
set_location_assignment PIN_AF6 -to GPIO_0[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
set_location_assignment PIN_AF9 -to GPIO_0[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
set_location_assignment PIN_AE8 -to GPIO_0[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
set_location_assignment PIN_AD10 -to GPIO_0[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
set_location_assignment PIN_AE9 -to GPIO_0[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
set_location_assignment PIN_AD11 -to GPIO_0[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
set_location_assignment PIN_AF10 -to GPIO_0[31]
#============================================================
set_location_assignment PIN_V12 -to GPIO_0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
set_location_assignment PIN_AF7 -to GPIO_0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
set_location_assignment PIN_W12 -to GPIO_0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
set_location_assignment PIN_AF8 -to GPIO_0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
set_location_assignment PIN_Y8 -to GPIO_0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
set_location_assignment PIN_AB4 -to GPIO_0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
set_location_assignment PIN_W8 -to GPIO_0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
set_location_assignment PIN_Y4 -to GPIO_0[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
set_location_assignment PIN_Y5 -to GPIO_0[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
set_location_assignment PIN_U11 -to GPIO_0[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
set_location_assignment PIN_T8 -to GPIO_0[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
set_location_assignment PIN_T12 -to GPIO_0[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
set_location_assignment PIN_AH5 -to GPIO_0[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
set_location_assignment PIN_AH6 -to GPIO_0[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
set_location_assignment PIN_AH4 -to GPIO_0[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
set_location_assignment PIN_AG5 -to GPIO_0[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
set_location_assignment PIN_AH3 -to GPIO_0[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
set_location_assignment PIN_AH2 -to GPIO_0[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
set_location_assignment PIN_AF4 -to GPIO_0[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
set_location_assignment PIN_AG6 -to GPIO_0[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
set_location_assignment PIN_AF5 -to GPIO_0[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
set_location_assignment PIN_AE4 -to GPIO_0[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
set_location_assignment PIN_T13 -to GPIO_0[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
set_location_assignment PIN_T11 -to GPIO_0[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
set_location_assignment PIN_AE7 -to GPIO_0[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
set_location_assignment PIN_AF6 -to GPIO_0[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
set_location_assignment PIN_AF9 -to GPIO_0[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
set_location_assignment PIN_AE8 -to GPIO_0[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
set_location_assignment PIN_AD10 -to GPIO_0[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
set_location_assignment PIN_AE9 -to GPIO_0[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
set_location_assignment PIN_AD11 -to GPIO_0[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
set_location_assignment PIN_AF10 -to GPIO_0[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
#set_location_assignment PIN_AD12 -to GPIO_0[32]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
@@ -319,90 +318,90 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
#============================================================
# GPIO_1, GPIO connect to GPIO Default
#============================================================
set_location_assignment PIN_Y15 -to GPIO_1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
set_location_assignment PIN_AG28 -to GPIO_1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
set_location_assignment PIN_AA15 -to GPIO_1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
set_location_assignment PIN_AH27 -to GPIO_1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
set_location_assignment PIN_AG26 -to GPIO_1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
set_location_assignment PIN_AH24 -to GPIO_1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
set_location_assignment PIN_AF23 -to GPIO_1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
set_location_assignment PIN_AE22 -to GPIO_1[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
set_location_assignment PIN_AF21 -to GPIO_1[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
set_location_assignment PIN_AG20 -to GPIO_1[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
set_location_assignment PIN_AG19 -to GPIO_1[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
set_location_assignment PIN_AF20 -to GPIO_1[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
set_location_assignment PIN_AC23 -to GPIO_1[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
set_location_assignment PIN_AG18 -to GPIO_1[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
set_location_assignment PIN_AH26 -to GPIO_1[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
set_location_assignment PIN_AA19 -to GPIO_1[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
set_location_assignment PIN_AG24 -to GPIO_1[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
set_location_assignment PIN_AF25 -to GPIO_1[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
set_location_assignment PIN_AH23 -to GPIO_1[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
set_location_assignment PIN_AG23 -to GPIO_1[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
set_location_assignment PIN_AE19 -to GPIO_1[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
set_location_assignment PIN_AF18 -to GPIO_1[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
set_location_assignment PIN_AD19 -to GPIO_1[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
set_location_assignment PIN_AE20 -to GPIO_1[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
set_location_assignment PIN_AE24 -to GPIO_1[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
set_location_assignment PIN_AD20 -to GPIO_1[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
set_location_assignment PIN_AF22 -to GPIO_1[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
set_location_assignment PIN_AH22 -to GPIO_1[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
set_location_assignment PIN_AH19 -to GPIO_1[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
set_location_assignment PIN_AH21 -to GPIO_1[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
set_location_assignment PIN_AG21 -to GPIO_1[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
set_location_assignment PIN_AH18 -to GPIO_1[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
set_location_assignment PIN_AD23 -to GPIO_1[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
set_location_assignment PIN_AE23 -to GPIO_1[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
set_location_assignment PIN_AA18 -to GPIO_1[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
set_location_assignment PIN_AC22 -to GPIO_1[35]
#============================================================
set_location_assignment PIN_Y15 -to GPIO_1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
set_location_assignment PIN_AG28 -to GPIO_1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
set_location_assignment PIN_AA15 -to GPIO_1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
set_location_assignment PIN_AH27 -to GPIO_1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
set_location_assignment PIN_AG26 -to GPIO_1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
set_location_assignment PIN_AH24 -to GPIO_1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
set_location_assignment PIN_AF23 -to GPIO_1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
set_location_assignment PIN_AE22 -to GPIO_1[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
set_location_assignment PIN_AF21 -to GPIO_1[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
set_location_assignment PIN_AG20 -to GPIO_1[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
set_location_assignment PIN_AG19 -to GPIO_1[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
set_location_assignment PIN_AF20 -to GPIO_1[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
set_location_assignment PIN_AC23 -to GPIO_1[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
set_location_assignment PIN_AG18 -to GPIO_1[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
set_location_assignment PIN_AH26 -to GPIO_1[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
set_location_assignment PIN_AA19 -to GPIO_1[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
set_location_assignment PIN_AG24 -to GPIO_1[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
set_location_assignment PIN_AF25 -to GPIO_1[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
set_location_assignment PIN_AH23 -to GPIO_1[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
set_location_assignment PIN_AG23 -to GPIO_1[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
set_location_assignment PIN_AE19 -to GPIO_1[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
set_location_assignment PIN_AF18 -to GPIO_1[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
set_location_assignment PIN_AD19 -to GPIO_1[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
set_location_assignment PIN_AE20 -to GPIO_1[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
set_location_assignment PIN_AE24 -to GPIO_1[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
set_location_assignment PIN_AD20 -to GPIO_1[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
set_location_assignment PIN_AF22 -to GPIO_1[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
set_location_assignment PIN_AH22 -to GPIO_1[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
set_location_assignment PIN_AH19 -to GPIO_1[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
set_location_assignment PIN_AH21 -to GPIO_1[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
set_location_assignment PIN_AG21 -to GPIO_1[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
set_location_assignment PIN_AH18 -to GPIO_1[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
set_location_assignment PIN_AD23 -to GPIO_1[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
set_location_assignment PIN_AE23 -to GPIO_1[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
set_location_assignment PIN_AA18 -to GPIO_1[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
set_location_assignment PIN_AC22 -to GPIO_1[35]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
set_location_assignment PIN_AE12 -to UART_TX_0
set_location_assignment PIN_AE11 -to UART_RX_0
set_location_assignment PIN_AF11 -to UART_TX_1
set_location_assignment PIN_AD12 -to UART_RX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
set_location_assignment PIN_AE12 -to UART_TX_0
set_location_assignment PIN_AE11 -to UART_RX_0
set_location_assignment PIN_AF11 -to UART_TX_1
set_location_assignment PIN_AD12 -to UART_RX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
#============================================================
@@ -410,46 +409,59 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX
#============================================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name VHDL_FILE ../DE0_nano_zpu_Toplevel.vhd
set_global_assignment -name QIP_FILE Clock_50to100.qip
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
set_global_assignment -name VHDL_FILE ../dpram.vhd
set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
set_global_assignment -name VHDL_FILE ../DE0_nano_zpu_Toplevel.vhd
set_global_assignment -name QIP_FILE Clock_50to100.qip
set_global_assignment -name SDC_FILE DE0_nano_zpu_constraints.sdc
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/sdram.qip
set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/sdram.vhd
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"

81
build/DE0_nano_zpu_Toplevel.vhd
View File

@@ -14,28 +14,46 @@ entity DE0_nano_zpu is
-- DIP switches
SW : in std_logic_vector(3 downto 0);
-- TDI : in std_logic;
-- TCK : in std_logic;
-- TCS : in std_logic;
-- TDO : out std_logic;
TDI : out std_logic;
TCK : out std_logic;
TCS : out std_logic;
TDO : in std_logic;
-- I2C_SDAT : inout std_logic;
-- I2C_SCLK : out std_logic;
-- GPIO_0 : inout std_logic_vector(33 downto 0);
-- GPIO_1 : inout std_logic_vector(33 downto 0);
-- SD Card 1
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-- UART Serial channels.
UART_RX_0 : in std_logic;
UART_TX_0 : out std_logic;
UART_RX_1 : in std_logic;
UART_TX_1 : out std_logic
-- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
-- SDRAM_CKE : out std_logic; -- clock enable.
-- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
-- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
-- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
-- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
-- SDRAM_CS : out std_logic; -- a single chip select
-- SDRAM_WE : out std_logic; -- write enable
-- SDRAM_RAS : out std_logic; -- row address select
-- SDRAM_CAS : out std_logic -- columns address select
);
END entity;
architecture rtl of DE0_nano_zpu is
signal reset : std_logic;
signal sysclk : std_logic;
signal pll_locked : std_logic;
signal reset : std_logic;
signal sysclk : std_logic;
signal memclk : std_logic;
signal pll_locked : std_logic;
--signal ps2m_clk_in : std_logic;
--signal ps2m_clk_out : std_logic;
@@ -56,14 +74,15 @@ begin
--GPIO_0(33 downto 2) <= (others => 'Z');
--GPIO_1 <= (others => 'Z');
--LED <= "101010" & reset & UART_RX_0;
LED <= "00000000";
mypll : entity work.Clock_50to100
port map
(
inclk0 => CLOCK_50,
c0 => sysclk,
c1 => open, --DRAM_CLK,
locked => pll_locked
inclk0 => CLOCK_50,
c0 => sysclk,
c1 => memclk,
locked => pll_locked
);
reset<=(not SW(0) xor KEY(0)) and pll_locked;
@@ -71,11 +90,12 @@ reset<=(not SW(0) xor KEY(0)) and pll_locked;
myVirtualToplevel : entity work.zpu_soc
generic map
(
sysclk_frequency => SYSCLK_FREQUENCY
SYSCLK_FREQUENCY => SYSCLK_DE0_FREQ
)
port map
(
SYSCLK => sysclk,
MEMCLK => memclk,
RESET_IN => reset,
-- RS232
@@ -85,10 +105,17 @@ port map
UART_TX_1 => UART_TX_1,
-- SPI signals
SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
SPI_MOSI => open,
SPI_CLK => open,
SPI_CS => open,
SPI_MISO => TDO, -- Allow the SPI interface not to be plumbed in.
SPI_MOSI => TDI,
SPI_CLK => TCK,
SPI_CS => TCS,
-- SD Card (SPI) signals
SDCARD_MISO => SDCARD_MISO,
SDCARD_MOSI => SDCARD_MOSI,
SDCARD_CLK => SDCARD_CLK,
SDCARD_CS => SDCARD_CS,
-- PS/2 signals
PS2K_CLK_IN => '1',
@@ -100,7 +127,10 @@ port map
PS2M_CLK_OUT => open,
PS2M_DAT_OUT => open,
LED => LED,
-- I²C signals
I2C_SCL_IO => open,
I2C_SDA_IO => open,
-- IOCTL Bus --
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
@@ -112,7 +142,20 @@ LED => LED,
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
IOCTL_ADDR => open, -- Address in FPGA to write into.
IOCTL_DOUT => open, -- Data to be written into FPGA.
IOCTL_DIN => (others => '0') -- Data to be read into HPS.
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-- SDRAM signals
SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
SDRAM_BA => open, --SDRAM_BA, -- two banks
SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
SDRAM_WE_n => open, --SDRAM_WE, -- write enable
SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
SDRAM_READY => open
);

137
build/DE0_nano_zpu_constraints.sdc Normal file
View File

@@ -0,0 +1,137 @@
## Generated SDC file "hello_led.out.sdc"
## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
## DATE "Fri Jul 06 23:05:47 2012"
##
## DEVICE "EP3C25Q240C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 12 -divide_by 2 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
#derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
# Delays for async signals - not necessary, but might as well avoid
# having unconstrained ports in the design
#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
#**************************************************************
# Set Output Delay
#**************************************************************
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_keepers {KEY*}]
set_false_path -from [get_keepers {SW*}]
#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1
set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

3
build/DE10_nano_zpu.qsf
View File

@@ -463,7 +463,6 @@ set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_cacheL2.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
@@ -491,4 +490,4 @@ set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
build/DE10_nano_zpu_Toplevel.vhd
View File

@@ -17,7 +17,7 @@ entity DE10_nano_zpu is
TDI : out std_logic;
TCK : out std_logic;
TCS : out std_logic;
TDO : in std_logic;
TDO : in std_logic;
-- I2C_SDAT : inout std_logic;
-- I2C_SCLK : out std_logic;
-- GPIO_0 : inout std_logic_vector(33 downto 0);
@@ -90,7 +90,7 @@ reset<=(not SW(0) xor KEY(0)) and pll_locked;
myVirtualToplevel : entity work.zpu_soc
generic map
(
SYSCLK_FREQUENCY => SYSCLK_DE10_FREQ
SYSCLK_FREQUENCY => SYSCLK_DE10_FREQ
)
port map
(

108
build/Makefile
View File

@@ -56,14 +56,17 @@ SOC = $(ROOT)/zpu_soc.vhd $(ROOT)/zpu_soc_pkg.vhd
ZPU_EVO = $(ROOT)/cpu/zpu_core_evo.vhd $(ROOT)/cpu/zpu_pkg.vhd
.PHONY: all
all: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL
all: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL
DE0_nano: DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL
DE10_nano: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL
E115: E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL
SMALL: DE10_nano_SMALL E115_SMALL
MEDIUM: DE10_nano_MEDIUM E115_MEDIUM
FLEX: DE10_nano_FLEX E115_FLEX
EVO: DE10_nano_EVO E115_EVO
EVO_MINIMAL: DE10_nano_EVO_MINIMAL E115_EVO_MINIMAL
QMV: QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL
CYC1000: CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL
SMALL: DE10_nano_SMALL E115_SMALL DE0_nano_SMALL QMV_SMALL CYC1000_SMALL
MEDIUM: DE10_nano_MEDIUM E115_MEDIUM DE0_nano_MEDIUM QMV_MEDIUM CYC1000_MEDIUM
FLEX: DE10_nano_FLEX E115_FLEX DE0_nano_FLEX QMV_FLEX CYC1000_FLEX
EVO: DE10_nano_EVO E115_EVO DE0_nano_EVO QMV_EVO CYC1000_EVO
EVO_MINIMAL: DE10_nano_EVO_MINIMAL E115_EVO_MINIMAL DE0_nano_EVO_MINIMAL QMV_EVO_MINIMAL CYC1000_EVO_MINIMAL
DE10_nano_SMALL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
@@ -110,6 +113,51 @@ DE10_nano_EVO_MINIMAL:
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
DE0_SMALL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) DE0_nano_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
DE0_MEDIUM:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) DE0_nano_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
DE0_FLEX:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) DE0_nano_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
DE0_EVO:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) DE0_nano_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
DE0_EVO_MINIMAL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) DE0_nano_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
E115_SMALL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@@ -155,9 +203,55 @@ E115_EVO_MINIMAL:
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
QMV_SMALL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) QMV_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
QMV_MEDIUM:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) QMV_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
QMV_FLEX:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) QMV_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
QMV_EVO:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) QMV_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
QMV_EVO_MINIMAL:
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
> $(ROOT)/zpu_soc_pkg.vhd
@$(ECHO) "Compiling $@..."
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
@$(MV) QMV_zpu.sof $@.sof
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
@$(ECHO) "$@.sof and $@.rbf generated..."
clean:
@$(ECHO) "Removing all temporary files..."
@$(RM) -fr c5_pin_model_dump.txt ./db ./simulation DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE10*.log DE10_nano*.rbf DE10_nano*.sof DE10_nano*.sta.smsg
@$(RM) -fr c5_pin_model_dump.txt ./db ./simulation DE0_nano_zpu.asm.rpt DE0_nano_zpu.done DE0_nano_zpu.fit.rpt DE0_nano_zpu.fit.smsg DE0_nano_zpu.fit.summary DE0_nano_zpu.flow.rpt DE0_nano_zpu.jdi DE0_nano_zpu.map.rpt DE0_nano_zpu.map.smsg DE0_nano_zpu.map.summary DE0_nano_zpu.pin DE0_nano_zpu.rbf DE0_nano_zpu.sld DE0_nano_zpu.sof DE0_nano_zpu.sta.rpt DE0_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE0*.log DE0_nano*.rbf DE0_nano*.sof DE0_nano*.sta.smsg
@$(RM) -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE10*.log DE10_nano*.rbf DE10_nano*.sof DE10_nano*.sta.smsg
@$(RM) -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof E115*.log E115*.rbf E115*.sof E115*.sta.smsg
@$(RM) -fr c5_pin_model_dump.txt ./db CYC1000_zpu.asm.rpt CYC1000_zpu.done CYC1000_zpu.fit.rpt CYC1000_zpu.fit.smsg CYC1000_zpu.fit.summary CYC1000_zpu.flow.rpt CYC1000_zpu.jdi CYC1000_zpu.map.rpt CYC1000_zpu.map.smsg CYC1000_zpu.map.summary CYC1000_zpu.pin CYC1000_zpu.rbf CYC1000_zpu.sld CYC1000_zpu.sof CYC1000_zpu.sta.rpt CYC1000_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt CYC1000_zpu.pof CYC1000*.log CYC1000*.rbf CYC1000*.sof CYC1000*.sta.smsg
@$(RM) -fr c5_pin_model_dump.txt ./db QMV_zpu.asm.rpt QMV_zpu.done QMV_zpu.fit.rpt QMV_zpu.fit.smsg QMV_zpu.fit.summary QMV_zpu.flow.rpt QMV_zpu.jdi QMV_zpu.map.rpt QMV_zpu.map.smsg QMV_zpu.map.summary QMV_zpu.pin QMV_zpu.rbf QMV_zpu.sld QMV_zpu.sof QMV_zpu.sta.rpt QMV_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt QMV_zpu.pof QMV*.log QMV*.rbf QMV*.sof QMV*.sta.smsg

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{ "" "" "" "*" { } { } 0 10037 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 14130 "" 0 0 "Design Software" 0 -1 0 ""}

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## Foreword
This document is a work in progress with the intention of it ending up as a comprehensive user guide. It may appear a bit disjointed but will get better. The same goes for the ZPU Evo and SoC RTL as both are evolving as I further the emulator project it was originally destined to go into and any improvements/deficiencies corrected.
## Overview
The ZPU is a 32bit Stack based microprocessor and was designed by Øyvind Harboe from Zylin AS ( https://opensource.zylin.com/ ) and original documentation can be found on the Zylin/OpenCore website or Wikipedia ( https://en.wikipedia.org/wiki/ZPU_(microprocessor) ). It is a microprocessor intended for FPGA embedded applications with minimal logic element and BRAM usage with the sacrifice of speed of execution.
Zylin produced two designs which it made open source, namely the Small and Medium ZPU versions. Additional designs were produced by external developers such as the Flex and ZPUino variations, each offering enhancements to the original design such as Wishbone interface, performance etc.
This document describes another design which I like to deem as the ZPU Evo(lution) model whose focus is on performance, connectivity and instruction expansion. This came about as I needed a CPU for an emulator of a vintage computer i am writing which would act as the IO processor to provide Menu, Peripheral and SD services.
An example of the performance of the ZPU Evo can be seen using CoreMark which returns a value of 19.1 @ 100MHz on Altera fabric using BRAM and for Dhrystone 11.2DMIPS. Connectivity can be seen via implementation of both System and Wishbone buses, allowing for connection of many opensource IP devices. Instruction expansion can be seen by the inclusion of a close coupled L1 cache where multiple instruction bytes are sourced and made available to the CPU which in turn can be used for optimization (ie. upto 5 IM instructions executed in 1 cycle) or for extended multi-byte instructions (ie. implementation of a LoaD Increment Repeat instruction). There is room for a lot more improvements such as stack cache, SDRAM to L2 burst mode, parallel instruction execution (ie. and + neqbranch) which are on my list.
## ZPU Evo
The ZPU Evo follows on from the ZPU Medium and Flex and areas of the code are similar, for example the instruction decoding. The design differs though due to caching and implementation of a Memory Transaction Processor where all Memory/IO operations (except for direct Instruction reads if dual-port instruction bus is enabled) are routed. The original CPU's all handled their memory requirements in-situ or part of the state machine whereas the Evo submits a request to the MXP whenever a memory operation is required.
The following sections indicate some of the features and changes to original ZPU designs.
#### Bus structure
The ZPU has a linear address space with all memory and IO devices directly addressable within this space. Existing ZPU designs either provide a system bus or a wishbone bus whereas the Evo provides both. The ZPU Evo creates up to two distinct regions within the address space depending on configuration, to provide a *system bus* and a *wishbone bus*.
All models have the system bus instantiated which starts at cpu address 0 and expands up-to the limit imposed by the configurable maximum address bit (ie. 0x000000 - 0xFFFFFF for 24bit). A dedicated memory mapped IO region is set aside at the top of the address space (albeit it could quite easily be in any location) ie. 0xFF0000 - 0xFFFFFF.
If configured, a wishbone bus can be instantiated and this extends the maximum address bit by 1 (ie. 0x1000000 - 0x1FFFFFF for 24bit example). This in effect creates 2 identical regions, the lower being controlled via the system bus, the upper via the wishbone bus. As per the system bus, the upper area of the wishbone address space is reserved for IO devices.
A third bus can be configured, which is for instruction reads only. This bus typically shadows the system bus in memory region but is deemed to be connected to fast access memory for reading of instructions without the need for L2 Cache. This would typically be the 2nd port of a dual-port BRAM block with the 1st port connected to the system bus.
#### L1 Cache
In order to gain performance but more especially for instruction optimisations and extended instructions, an L1 cache is implemented using registers. Using registers consumes fabric space so should be very small but it allows random access in a single cycle which is needed for example if compacting a 32bit IM load (which can be 5 instructions) into a single cycle. Also for extended instructions, the first byte indicates an extended instruction and the following 1-5 bytes defines the instruction which is then executed in a single cycle.
#### L2 Cache
Internal BRAM (on-board Block RAM within the FPGA) doesn't need an L2 Cache as it's access time is 1-2 cycles. As BRAM is a limited resource it is assumed external RAM or SDRAM will be used which is much slower and this needs to be cached to increase throughput. The L2 Cache is used for this purpose, to read ahead a block of external RAM and feed the L1 Cache as needed. On analysis, the C programs generated by GCC are typically loops and calls within a local area (unless using large libraries), so implementing a simple direct mapping cache between external RAM and BRAM (used for the L2 Cache) indexed relative to the Program Counter is sufficient to keep the CPU from stalling most of the time.
#### Instruction Set
A feature of the ZPU is it's use of a minimal fixed set of hardware implemented instructions and a soft set of additional instructions which are implemented in pseudo micro-code (ie. the fixed set of instructions). This is achieved by 32byte vectors in the region 0x0000 - 0x0400 and each soft instruction branches to the vector if it is not implemented in hardware. The benefit is reduced FPGA resources but the penalty is performance.
The ZPU Evo implements all instructions in hardware but this can be adjusted in the configuration to use soft instructions if required in order to conserve FPGA resources. This allows for a balance of resources versus performance. Ultimately though, if resources are tight then the use of the Small/Flex ZPU models may be a better choice.
In addition to the original instructions, a mechanism exists to extend the instruction set using multi-byte instructions of the format:-
***Extend Instruction,<new insn[7:2]+ParamSize[1:0]>,[byte],[byte],[byte],[byte]***
Where ParamSize = 00 - No parameter bytes
01 - 8 bit parameter
10 - 16 bit parameter
11 - 32 bit parameter
Some extended instructions are under development (ie. LDIR) an exact opcode value and extended instruction set has not yet been fully defined. The GNU AS assembler will be updated with these instructions so they can be invoked within a C program and eventually if they have benefit to C will be migrated into the GCC compiler (ie. ADD32/DIV32/MULT32/LDIR/LDDR as from what I have seen, these will have a big impact on CoreMark/Dhrystone tests).
##### Implemented Instruction Set
| Name | Opcode | | Description |
|------------------|-----------|-----------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| BREAKPOINT | 0 | 00000000 | The debugger sets a memory location to this value to set a breakpoint. Once a JTAG-like debugger interface is added, it will be convenient to be able to distinguish between a breakpoint and an illegal(possibly emulated) instruction. |
| IM | 1xxx xxxx | 1xxx xxxx | Pushes 7 bit sign extended integer and sets the a «instruction decode interrupt mask» flag(IDIM). |
| | | | |
| | | | If the IDIM flag is already set, this instruction shifts the value on the stack left by 7 bits and stores the 7 bit immediate value into the lower 7 bits. |
| | | | |
| | | | Unless an instruction is listed as treating the IDIM flag specially, it should be assumed to clear the IDIM flag. |
| | | | |
| | | | To push a 14 bit integer onto the stack, use two consecutive IM instructions. |
| | | | |
| | | | If multiple immediate integers are to be pushed onto the stack, they must be interleaved with another instruction, typically NOP. |
| | | | |
| | | | |
| | | | |
| STORESP | 010x xxxx | 010x xxxx | Pop value off stack and store it in the SP+xxxxx*4 memory location, where xxxxx is a positive integer. |
| LOADSP | 011x xxxx | 011x xxxx | Push value of memory location SP+xxxxx*4, where xxxxx is a positive integer, onto stack. |
| ADDSP | 0001 xxxx | 0001 xxxx | Add value of memory location SP+xxxx*4 to value on top of stack. |
| EMULATE | 001x xxxx | 010x xxxx | Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction |
| | | | |
| | | | One way to improve performance of the ZPU is to implement some of the EMULATE instructions. |
| PUSHPC | emulated | emulated | Pushes program counter onto the stack. |
| POPPC | 0000 0100 | 0000 0100 | Pops address off stack and sets PC |
| LOAD | 0000 1000 | 0000 1000 | Pops address stored on stack and loads the value of that address onto stack. |
| | | | |
| | | | Bit 0 and 1 of address are always treated as 0(i.e. ignored) by the HDL implementations and C code is guaranteed by the programming model never to use 32 bit LOAD on non-32 bit aligned addresses(i.e. if a program does this, then it has a bug). |
| STORE | 0000 1100 | 0000 1100 | Pops address, then value from stack and stores the value into the memory location of the address. |
| | | | |
| | | | Bit 0 and 1 of address are always treated as 0 |
| PUSHSP | 0000 0010 | 0000 0010 | Pushes stack pointer. |
| POPSP | 0000 1101 | 0000 1101 | Pops value off top of stack and sets SP to that value. Used to allocate/deallocate space on stack for variables or when changing threads. |
| ADD | 0000 0101 | 0000 0101 | Pops two values on stack adds them and pushes the result |
| AND | 0000 0110 | 0000 0110 | Pops two values off the stack and does a bitwise-and & pushes the result onto the stack |
| OR | 0000 0111 | 0000 0111 | Pops two integers, does a bitwise or and pushes result |
| NOT | 0000 1001 | 0000 1001 | Bitwise inverse of value on stack |
| FLIP | 0000 1010 | 0000 1010 | Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc. |
| | | | |
| | | | The raison d'etre for this instruction is mainly to emulate other instructions. |
| NOP | 0000 1011 | 0000 1011 | No operation, clears IDIM flag as side effect, i.e. used between two consecutive IM instructions to push two values onto the stack. |
| PUSHSPADD | 61 | 00111101 | a=sp; |
| | | | b=popIntStack()*4; |
| | | | pushIntStack(a+b); |
| POPPCREL | 57 | 00111001 | setPc(popIntStack()+getPc()); |
| SUB | 49 | 00110001 | int a=popIntStack(); |
| | | | int b=popIntStack(); |
| | | | pushIntStack(b-a); |
| XOR | 50 | | pushIntStack(popIntStack() ^ popIntStack()); |
| LOADB | 51 | | 8 bit load instruction. Really only here for compatibility with C programming model. Also it has a big impact on DMIPS test. |
| | | | |
| | | | pushIntStack(cpuReadByte(popIntStack())&0xff); |
| STOREB | 52 | | 8 bit store instruction. Really only here for compatibility with C programming model. Also it has a big impact on DMIPS test. |
| | | | |
| | | | addr = popIntStack(); |
| | | | val = popIntStack(); |
| | | | cpuWriteByte(addr, val); |
| | | | |
| LOADH | 34 | | 16 bit load instruction. Really only here for compatibility with C programming model. |
| | | | |
| | | | pushIntStack(cpuReadWord(popIntStack())); |
| STOREH | 35 | | 16 bit store instruction. Really only here for compatibility with C programming model. |
| | | | |
| | | | addr = popIntStack(); |
| | | | val = popIntStack(); |
| | | | cpuWriteWord(addr, val); |
| | | | |
| LESSTHAN | 36 | | Signed comparison |
| | | | a = popIntStack(); |
| | | | b = popIntStack(); |
| | | | pushIntStack((a < b) ? 1 : 0); |
| LESSTHANOREQUAL | 37 | | Signed comparison |
| | | | a = popIntStack(); |
| | | | b = popIntStack(); |
| | | | pushIntStack((a <= b) ? 1 : 0); |
| ULESSTHAN | 38 | | Unsigned comparison |
| | | | long a;//long is here 64 bit signed integer |
| | | | long b; |
| | | | a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff |
| | | | b = ((long) popIntStack()) & INTMASK; |
| | | | pushIntStack((a < b) ? 1 : 0); |
| ULESSTHANOREQUAL | 39 | | Unsigned comparison |
| | | | long a;//long is here 64 bit signed integer |
| | | | long b; |
| | | | a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff |
| | | | b = ((long) popIntStack()) & INTMASK; |
| | | | pushIntStack((a <= b) ? 1 : 0); |
| EQBRANCH | 55 | | int compare; |
| | | | int target; |
| | | | target = popIntStack() + pc; |
| | | | compare = popIntStack(); |
| | | | if (compare == 0) |
| | | | { |
| | | | setPc(target); |
| | | | } else |
| | | | { |
| | | | setPc(pc + 1); |
| | | | } |
| NEQBRANCH | 56 | | int compare; |
| | | | int target; |
| | | | target = popIntStack() + pc; |
| | | | compare = popIntStack(); |
| | | | if (compare != 0) |
| | | | { |
| | | | setPc(target); |
| | | | } else |
| | | | { |
| | | | setPc(pc + 1); |
| | | | } |
| MULT | 41 | | Signed 32 bit multiply |
| | | | pushIntStack(popIntStack() * popIntStack()); |
| DIV | 53 | | Signed 32 bit integer divide. |
| | | | a = popIntStack(); |
| | | | b = popIntStack(); |
| | | | if (b == 0) |
| | | | { |
| | | | // undefined |
| | | | } pushIntStack(a / b); |
| MOD | 54 | | Signed 32 bit integer modulo. |
| | | | a = popIntStack(); |
| | | | b = popIntStack(); |
| | | | if (b == 0) |
| | | | { |
| | | | // undefined |
| | | | } |
| | | | pushIntStack(a % b); |
| LSHIFTRIGHT | 42 | | unsigned shift right. |
| | | | long shift; |
| | | | long valX; |
| | | | int t; |
| | | | shift = ((long) popIntStack()) & INTMASK; |
| | | | valX = ((long) popIntStack()) & INTMASK; |
| | | | t = (int) (valX >> (shift & 0x3f)); |
| | | | pushIntStack(t); |
| ASHIFTLEFT | 43 | | arithmetic(signed) shift left. |
| | | | long shift; |
| | | | long valX; |
| | | | shift = ((long) popIntStack()) & INTMASK; |
| | | | valX = ((long) popIntStack()) & INTMASK; |
| | | | int t = (int) (valX << (shift & 0x3f)); |
| | | | pushIntStack(t); |
| ASHIFTRIGHT | 43 | | arithmetic(signed) shift left. |
| | | | long shift; |
| | | | int valX; |
| | | | shift = ((long) popIntStack()) & INTMASK; |
| | | | valX = popIntStack(); |
| | | | int t = valX >> (shift & 0x3f); |
| | | | pushIntStack(t); |
| CALL | 45 | | call procedure. |
| | | | |
| | | | int address = pop(); |
| | | | push(pc + 1); |
| | | | setPc(address); |
| CALLPCREL | 63 | | call procedure pc relative |
| | | | |
| | | | int address = pop(); |
| | | | push(pc + 1); |
| | | | setPc(address+pc); |
| EQ | 46 | | pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); |
| NEQ | 47 | | pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); |
| NEG | 48 | | pushIntStack(-popIntStack()); |
##### Implemented Instructions Comparison Table
![alt text](https://github.com/pdsmart/ZPU/blob/master/docs/ImplInstructions.png)
#### Hardware Variable Byte Write
In the original ZPU designs there was scope but not the implementation to allow the ZPU to perform byte/half-word/full-word writes. Either the CPU always had to perform 32bit Word aligned operations or it performed the operation in micro-code.
In the Evo, hardware was implemented (build time selectable) to allow Byte and Half-Word writes and also hardware Read-Update-Write operations. If the hardware Byte/Half-Word logic is not enabled then it falls back to the 32bit Word Read-Update-Write logic. Both methods have performance benefits, the latter taking 3 cycles longer.
#### Hardware Debug Serializer
In order to debug the CPU or just provide low level internal operating information, a cached UART debug module is implemented. Currently this is only for output but has the intention to be tied into the IOCP for in-situ debugging when Simulation/Signal-Tap is not available.
Embedded within the CPU RTL are statements which issue snapshot information to the serialiser, if enabled in the configuration along with the information level. This is then serialized and output to a connected terminal. A snapshot of the output information can be seen below (with manual comments):
| 000477 01ffec 00001ae4 00000000 70.17 04770484 046c047c 08f0046c 0b848015 17700500 05000500 05001188 11ef2004 <br/><br/><u>Break Point - Illegal instruction</u><br/>000478 01ffe8 00001ae4 00001ae4 00.05 04780484 046c0478 08f0046c 0b888094 05000500 05000500 118811ef 20041188 <br/><br/><u>L1 Cache Dump</u><br/>000478 (480)-> 11 e2 2a 51 11 a0 11 8f <-(483) (004)->11 ed 20 04 05 00 05 00 05 00 05 00 05 00 05 00 20 (46c)->04 11 b5 11 e4 17 70 <-(46f)<br/> (004)-> 11 ed 20 04 05 00 05 00 05 00 05 00 05 00 05 00 20 (46c)->04 11 b5 11 e4 17 70 11 b6 11 c4 2d 27 11 8b <-(473)<br/> 05 00 05 00 05 00 05 00 (46c)->20 04 11 b5 11 e4 17 70 11 b6 11 c4 2d 27 11 8b 1c 38 11 80 17 71 17 70 -<(477)<br/>(46c)->20 04 11 b5 11 e4 17 70 11 b6 11 c4 2d 27 11 8b 1c 38 11 80 17 71 17 70 -<(477) 05 00 05 00 05 00 05 00 <br/>(470)->11 b6 11 c4 2d 27 11 8b 1c 38 11 80 17 71 17 70 <-(477) -> 05 00 05 00 05 00 05 00 (47c)->11 88 11 ef 20 04 11 88 <-(47f)<br/>(474)->1c 38 11 80 17 71 17 70 05 00 05 00 05 00 05 00 11 88 11 ef 20 04 11 88 11 e2 2a 51 11 a0 11 8f <br/> 05 00 05 00 05 00 05 00 11 88 11 ef 20 04 11 88 11 e2 2a 51 11 a0 11 8f 11 ed 20 04 05 00 05 00 <br/> 11 88 11 ef 20 04 11 88 11 e2 2a 51 11 a0 11 8f 11 ed 20 04 05 00 05 00 05 00 05 00 05 00 05 00 <br/><u>L2 Cache Dump</u><br/>000000 88 08 8c 08 ed 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <br/>000020 88 08 8c 08 90 08 0b 0b 0b 88 80 08 2d 90 0c 8c 0c 88 0c 04 00 00 00 00 00 00 00 00 00 00 00 00 <br/>000040 71 fd 06 08 72 83 06 09 81 05 82 05 83 2b 2a 83 ff ff 06 52 04 00 00 00 00 00 00 00 00 00 00 00 |
| :----------------------------------------------------------- |
| |
All critical information such as current instruction being executed (or not if stalled), Signals/Flags, L1/L2 Cache contents and Memory contents can be output.
## System On a Chip
In order to provide a working framework in which the ZPU Evo could be used, a System On a Chip wrapper was created which allows for the instantiation of various devices (ie. UART/SD card).
As part of the development, the ZPU Small/Medium/Flex models were incorporated into the framework allowing the choice of CPU when fabric space is at a premium or comparing CPU's, albeit features such as Wishbone are not available on the original ZPU models. I didn't include the ZPUino as this design already has a very good eco system or the ZY2000.
The SoC currently implements (in the build tree):
| Component | Selectable (ie not hardwired) |
| ------------------------- | ------------------------------------------------------------ |
| CPU | Choice of ZPU Small, Medium, Flex, Evo or Evo Minimal. |
| Wishbone Bus | Yes, 32 bit bus. |
| (SB) BRAM | Yes, implement a configurable block of BRAM as the boot loader and stack. |
| Instruction Bus BRAM | Yes, enable a separate bus (or Dual-Port) to the boot code implemented in BRAM. This is generally a dual-port BRAM shared with the Sysbus BRAM but can be independent. |
| (SB) RAM | Implement a block of BRAM as RAM, seperate from the BRAM used for the boot loader/stack. |
| (WB) SDRAM | Yes, implement an SDRAM controller over the Wishbone bus. |
| (WB) I2C | Yes, implements an I2C Controller over the Wishbone bus. |
| (SB) Timer 0 | No, implements a hardware 12bit Second, 18bit milliSec and 24bit uSec down counter with interrupt, a 32bit milliSec up counter with interrupt and a YMD HMS Real Time Clock. The down counters are ideal for scheduling. |
| (SB) Timer 1 | Yes, a selectable number of pre-scaled 32bit down counters. |
| (SB) UART 0 | No, a cached UART used for monitor output and command input/program load. |
| (SB) UART 1 | No, a cached UART used for software (C program)/hardware (ZPU debug serializer) output. |
| (SB) Interrupt Controller | Yes, a prioritized configurable (# of inputs) interrupt controller. |
| (SB) PS2 | Yes, a PS2 Keyboard and Mouse controller. |
| (SB) SPI | Yes, a configurable number of Serial Peripheral Interface controllers. |
| (SB) SD | Yes, a configurable number of hardware based SPI SD controllers. |
| (SB) SOCCFG | Yes, a set of registers to indicate configuration of the ZPU and SoC to the controlling program. |
Within the SoC configuration, items such as starting Stack Address, Reset Vector, IO Start/End (SB) and (WB) can be specified. Given the wishbone bus, it is very easy to add further opencore IP devices, for the system bus some work may be needed as the opencore IP devices use differing signals.
## GIT Folder Structure
#### RTL Structure
| Folder | RTL File | Description |
| ---------------- | -------------------- | ------------------------------------------------------------ |
| < root > | zpu_soc_pkg.tmpl.vhd | A templated version of zpu_soc_pkg.vhd used by the build/Makefile to configure and make a/all versions of the SoC. |
| | zpu_soc_pkg.vhd | The SoC configuration file, this enables/disables components within the SoC. |
| | zpu_soc.vhd | The SoC definition and glue logic between enabled components. |
| cpu/ | zpu_core_evo.vhd | The ZPU Evo CPU. |
| | zpu_core_flex.vhd | The ZPU Flex CPU re-factored to keep the same style as the Evo and additional hardware debug output added. |
| | zpu_core_medium.vhd | The ZPU Medium (4) CPU re-factored to keep the same style as the Evo and additional hardware debug output added. |
| | zpu_core_small.vhd | The ZPU Small CPU re-factored to keep the same style as the Evo and additional hardware debug output added. |
| | zpu_pkg.vhd | The CPU configuration, bus address width etc. |
| | zpu_uart_debug.vhd | A hardware debug serializer to output runtime data to a connected serial port. |
| devices/sysbus | BRAM | Block RAM RTL |
| | intr | Interrupt Controller |
| | ps2 | PS2 Keyboard/Mouse Controller |
| | RAM | Dual Port RAM |
| | SDMMC | SD Controller |
| | spi | Serial Peripheral Interface Controller |
| | timer | Timer |
| | uart | Full duplex cached UART Controller |
| devices/WishBone | I2C | I2C Controller |
| | SRAM | Encapsulated Byte Addressable BRAM |
| | SDRAM | Byte Addressable 32Bit SDRAM Controller |
| build | CYC1000 | Quartus definition files and Top Level VHDL for the Trenz Electronic CYC1000 Cyclone 10LP development board. |
| | E115 | Quartus definition files and Top Level VHDL for the Cyclone IV EP4CE115 DDR2 64BIT development board. |
| | QMV | Quartus definition files and Top Level VHDL for the QMTech Cyclone V development board. |
| | DE10 | Quartus definition files and Top Level VHDL for the Altera DE10 development board as used in the MiSTer project. |
| | DE0 | Quartus definition files and Top Level VHDL for the Altera DE0 development board. |
| | Clock_* | Refactored Altera PLL definitions for various development board source clocks. These need to be made more generic for eventual inclusion of Xilinx fabric. |
#### Software Structure
| Folder | Module | Description |
| ------- | -------- | ------------------------------------------------------------ |
| apps | | The ZPUTA application can either have a feature embedded or as a separate standalone disk based applet in addition to extended applets. The purpose is to allow control of the ZPUTA application size according to available BRAM and SD card availability.<br/>All applets for ZPUTA are stored in this folder. |
| build | | Build tree output suitable for direct copy to an SD card.<br/> The initial bootloader and/or application as selected are compiled directly into a VHDL file for preloading in BRAM in the devices/sysbus/BRAM folder. |
| common | | Common C modules such as Elm Chan's excellent Fat FileSystem. |
| include | | C Include header files. |
| iocp | | A small bootloader/monitor application for initialization of the ZPU. Depending upon configuration this program can either boot an application from SD card or via the Serial Line and also provide basic tools such as memory examination. |
| startup | | Assembler and Linker files for generating ZPU applications. These files are critical for defining how GCC creates and links binary images as well as providing the micro-code for ZPU instructions not implemented in hardware. |
| utils | | Some small tools for converting binary images into VHDL initialization data. |
| zputa | | The ZPU Test Application. This is an application for testing the ZPU and the SoC components. It can either be built as a single image for pre-loading into a BRAM via VHDL or as a standalone application loaded by the IOCP bootloader from an SD card. The services it provides can either be embedded or available on the SD card as applets depending on memory restrictions. |
| | build.sh | Unix shell script to build IOCP, ZPUTA and Apps for a given design.<br/>NAME<br/> build.sh - Shell script to build a ZPU program or OS.<br/><br/>SYNOPSIS<br/> build.sh [-dOBAh]<br/><br/>DESCRIPTION<br/><br/>OPTIONS<br/> -I < iocp ver > = 0 - Full, 1 - Medium, 2 - Minimum, 3 - Tiny (bootstrap only)<br/> -O < os > = zputa, zos<br/> -o < os ver > = 0 - Standalone, 1 - As app with IOCP Bootloader,<br/> 2 - As app with tiny IOCP Bootloader, 3 - As app in RAM<br/> -B < addr > = Base address of < os >, default 0x01000<br/> -A < addr > = App address of < os >, default 0x0C000<br/> -d = Debug mode.<br/> -h = This help screen.<br/><br/>EXAMPLES<br/> build.sh -I 3 -O zputa -o 2 -B 0x00000 -A 0x50000<br/><br/>EXIT STATUS<br/> 0 The command ran successfully<br/> >0 An error ocurred. |
#### Memory Maps
The I/O Control Program (IOCP) is basically a bootloader, it can operate standalone or as the first stage in booting an application. At the time of writing the following memory maps have been defined in the build.sh and parameterisation of the IOCP/ZPUTA/RTL but any other is possible by adjusting the parameters.
The memory maps are as follows:-
Tiny - IOCP is the smallest size possible to boot from SD Card. It is useful for a SoC configuration where there is limited BRAM and the applications loaded from the SD card would potentially run in external RAM.
Minimum - Full - IOCP has various inbuilt functions, such as application upload from serial port, memory edit/exam.
![alt text](https://github.com/pdsmart/ZPU/blob/master/docs/IOCPMemoryMap.png)
For ZPUTA, it can either be configured to be the boot application (ie. no IOCP) or it can be configured as an App booted by IOCP. Depending upon how ZPUTA is built. it can have applets (portions of its functionality created as dedicated executables on the SD card) or standalone with all functionality inbuilt. The former is used when there is limited memory or a set of loadable programs is desired.
![alt text](https://github.com/pdsmart/ZPU/blob/master/docs/ZPUTAMemoryMap.png)
## Credits
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. Some devices are purely 3rd party (ie. I2C) and they remain untouched carrying the original copyright header.
## Licenses
The original ZPU uses the Free BSD license and such the Evo is also released under FreeBSD. SoC components and other developments written by me are currently licensed using the GPL. 3rd party components maintain their original copyright notices.
## Links
| Reference | URL |
| ----------------------------------- | -------------------------------------------------------- |
| Original Zylin ZPU repository | https://github.com/zylin/zpu |
| Original Zylin GCC v3.4.2 toolchain | https://github.com/zylin/zpugcc |
| Flex ZPU repository | https://github.com/robinsonb5/ZPUFlex |
| ZPUino and Eco System | http://papilio.cc/index.php?n=Papilio.ZPUinoIntroduction |
| Wikipedia ZPU Reference | https://en.wikipedia.org/wiki/ZPU_(microprocessor) |
Please consult my [GitHub](https://pdsmart.github.io) website for more upto date information.
<br>
The ZPU is a 32bit Stack based microprocessor and was designed by Øyvind Harboe from [Zylin AS](https://opensource.zylin.com/) and original documentation can be found on the [Zylin/OpenCore website or Wikipedia](https://en.wikipedia.org/wiki/ZPU_(microprocessor). It is a microprocessor intended for FPGA embedded applications with minimal logic element and BRAM usage with the sacrifice of speed of execution.
Zylin produced two designs which it made open source, namely the Small and Medium ZPU versions. Additional designs were produced by external developers such as the Flex and ZPUino variations, each offering enhancements to the original design such as Wishbone interface, performance etc.
This document describes another design which I like to deem as the ZPU Evo(lution) model whose focus is on performance, connectivity and instruction expansion. This came about as I needed a CPU for an emulator of a vintage computer i am writing which would act as the IO processor to provide Menu, Peripheral and SD services.
An example of the performance of the ZPU Evo can be seen using CoreMark which returns a value of 19.1 @ 100MHz on Altera fabric using BRAM and for Dhrystone 11.2DMIPS. Connectivity can be seen via implementation of both System and Wishbone buses, allowing for connection of many opensource IP devices. Instruction expansion can be seen by the inclusion of a close coupled L1 cache where multiple instruction bytes are sourced and made available to the CPU which in turn can be used for optimization (ie. upto 5 IM instructions executed in 1 cycle) or for extended multi-byte instructions (ie. implementation of a LoaD Increment Repeat instruction). There is room for a lot more improvements such as stack cache, SDRAM to L2 burst mode, parallel instruction execution (ie. and + neqbranch) which are on my list.
# The CPU
The ZPU Evo follows on from the ZPU Medium and Flex and areas of the code are similar, for example the instruction decoding. The design differs though due to caching and implementation of a Memory Transaction Processor where all Memory/IO operations (except for direct Instruction reads if dual-port instruction bus is enabled) are routed. The original CPU's all handled their memory requirements in-situ or part of the state machine whereas the Evo submits a request to the MXP whenever a memory operation is required.
The following sections indicate some of the features and changes to original ZPU designs.
### Bus structure
The ZPU has a linear address space with all memory and IO devices directly addressable within this space. Existing ZPU designs either provide a system bus or a wishbone bus whereas the Evo provides both. The ZPU Evo creates up to two distinct regions within the address space depending on configuration, to provide a *system bus* and a *wishbone bus*.
All models have the system bus instantiated which starts at cpu address 0 and expands up-to the limit imposed by the configurable maximum address bit (ie. 0x000000 - 0xFFFFFF for 24bit). A dedicated memory mapped IO region is set aside at the top of the address space (albeit it could quite easily be in any location) ie. 0xFF0000 - 0xFFFFFF.
If configured, a wishbone bus can be instantiated and this extends the maximum address bit by 1 (ie. 0x1000000 - 0x1FFFFFF for 24bit example). This in effect creates 2 identical regions, the lower being controlled via the system bus, the upper via the wishbone bus. As per the system bus, the upper area of the wishbone address space is reserved for IO devices.
A third bus can be configured, which is for instruction reads only. This bus typically shadows the system bus in memory region but is deemed to be connected to fast access memory for reading of instructions without the need for L2 Cache. This would typically be the 2nd port of a dual-port BRAM block with the 1st port connected to the system bus.
### L1 Cache
In order to gain performance but more especially for instruction optimisations and extended instructions, an L1 cache is implemented using registers. Using registers consumes fabric space so should be very small but it allows random access in a single cycle which is needed for example if compacting a 32bit IM load (which can be 5 instructions) into a single cycle. Also for extended instructions, the first byte indicates an extended instruction and the following 1-5 bytes defines the instruction which is then executed in a single cycle.
### L2 Cache
Internal BRAM (on-board Block RAM within the FPGA) doesn't need an L2 Cache as it's access time is 1-2 cycles. As BRAM is a limited resource it is assumed external RAM or SDRAM will be used which is much slower and this needs to be cached to increase throughput. The L2 Cache is used for this purpose, to read ahead a block of external RAM and feed the L1 Cache as needed. On analysis, the C programs generated by GCC are typically loops and calls within a local area (unless using large libraries), so implementing a simple direct mapping cache between external RAM and BRAM (used for the L2 Cache) indexed relative to the Program Counter is sufficient to keep the CPU from stalling most of the time.
### Instruction Set
A feature of the ZPU is it's use of a minimal fixed set of hardware implemented instructions and a soft set of additional instructions which are implemented in pseudo micro-code (ie. the fixed set of instructions). This is achieved by 32byte vectors in the region 0x0000 - 0x0400 and each soft instruction branches to the vector if it is not implemented in hardware. The benefit is reduced FPGA resources but the penalty is performance.
The ZPU Evo implements all instructions in hardware but this can be adjusted in the configuration to use soft instructions if required in order to conserve FPGA resources. This allows for a balance of resources versus performance. Ultimately though, if resources are tight then the use of the Small/Flex ZPU models may be a better choice.
In addition to the original instructions, a mechanism exists to extend the instruction set using multi-byte instructions of the format:-
***Extend Instruction,<new insn[7:2]+ParamSize[1:0]>,[byte],[byte],[byte],[byte]***
Where ParamSize = 00 - No parameter bytes
01 - 8 bit parameter
10 - 16 bit parameter
11 - 32 bit parameter
Some extended instructions are under development (ie. LDIR) an exact opcode value and extended instruction set has not yet been fully defined. The GNU AS assembler will be updated with these instructions so they can be invoked within a C program and eventually if they have benefit to C will be migrated into the GCC compiler (ie. ADD32/DIV32/MULT32/LDIR/LDDR as from what I have seen, these will have a big impact on CoreMark/Dhrystone tests).
### Implemented Instruction Set
| Name | Opcode | | Description |
|------------------|-----------|-----------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| BREAKPOINT | 0 | 00000000 | The debugger sets a memory location to this value to set a breakpoint. Once a JTAG-like debugger interface is added, it will be convenient to be able to distinguish between a breakpoint and an illegal(possibly emulated) instruction. |
| IM | 1xxx xxxx | 1xxx xxxx | Pushes 7 bit sign extended integer and sets the a «instruction decode interrupt mask» flag(IDIM).<br>If the IDIM flag is already set, this instruction shifts the value on the stack left by 7 bits and stores the 7 bit immediate value into the lower 7 bits.<br>Unless an instruction is listed as treating the IDIM flag specially, it should be assumed to clear the IDIM flag.<br>To push a 14 bit integer onto the stack, use two consecutive IM instructions.<br> If multiple immediate integers are to be pushed onto the stack, they must be interleaved with another instruction, typically NOP. |
| STORESP | 010x xxxx | 010x xxxx | Pop value off stack and store it in the SP+xxxxx*4 memory location, where xxxxx is a positive integer. |
| LOADSP | 011x xxxx | 011x xxxx | Push value of memory location SP+xxxxx*4, where xxxxx is a positive integer, onto stack. |
| ADDSP | 0001 xxxx | 0001 xxxx | Add value of memory location SP+xxxx*4 to value on top of stack. |
| EMULATE | 001x xxxx | 010x xxxx | Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction.<br>One way to improve performance of the ZPU is to implement some of the EMULATE instructions.|
| PUSHPC | emulated | emulated | Pushes program counter onto the stack. |
| POPPC | 0000 0100 | 0000 0100 | Pops address off stack and sets PC |
| LOAD | 0000 1000 | 0000 1000 | Pops address stored on stack and loads the value of that address onto stack.<br>Bit 0 and 1 of address are always treated as 0(i.e. ignored) by the HDL implementations and C code is guaranteed by the programming model never to use 32 bit LOAD on non-32 bit aligned addresses(i.e. if a program does this, then it has a bug).|
| STORE | 0000 1100 | 0000 1100 | Pops address, then value from stack and stores the value into the memory location of the address.<br>Bit 0 and 1 of address are always treated as 0 |
| PUSHSP | 0000 0010 | 0000 0010 | Pushes stack pointer. |
| POPSP | 0000 1101 | 0000 1101 | Pops value off top of stack and sets SP to that value. Used to allocate/deallocate space on stack for variables or when changing threads. |
| ADD | 0000 0101 | 0000 0101 | Pops two values on stack adds them and pushes the result |
| AND | 0000 0110 | 0000 0110 | Pops two values off the stack and does a bitwise-and & pushes the result onto the stack |
| OR | 0000 0111 | 0000 0111 | Pops two integers, does a bitwise or and pushes result |
| NOT | 0000 1001 | 0000 1001 | Bitwise inverse of value on stack |
| FLIP | 0000 1010 | 0000 1010 | Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc.<br>The raison d'etre for this instruction is mainly to emulate other instructions. |
| NOP | 0000 1011 | 0000 1011 | No operation, clears IDIM flag as side effect, i.e. used between two consecutive IM instructions to push two values onto the stack. |
| PUSHSPADD | 61 | 00111101 | a=sp;<br>b=popIntStack()*4;<br>pushIntStack(a+b);<br> |
| POPPCREL | 57 | 00111001 | setPc(popIntStack()+getPc()); |
| SUB | 49 | 00110001 | int a=popIntStack();<br>int b=popIntStack();<br>pushIntStack(b-a); |
| XOR | 50 | | pushIntStack(popIntStack() ^ popIntStack()); |
| LOADB | 51 | | 8 bit load instruction. Really only here for compatibility with C programming model. Also it has a big impact on DMIPS test.<br>pushIntStack(cpuReadByte(popIntStack())&0xff); |
| STOREB | 52 | | 8 bit store instruction. Really only here for compatibility with C programming model. Also it has a big impact on DMIPS test. <br>addr = popIntStack();<br>val = popIntStack();<br>cpuWriteByte(addr, val); |
| LOADH | 34 | | 16 bit load instruction. Really only here for compatibility with C programming model.<br>pushIntStack(cpuReadWord(popIntStack())); |
| STOREH | 35 | | 16 bit store instruction. Really only here for compatibility with C programming model.<br>addr = popIntStack();<br>val = popIntStack();<br>cpuWriteWord(addr, val);<br> |
| LESSTHAN | 36 | | Signed comparison<br>a = popIntStack();<br>b = popIntStack();<br>pushIntStack((a < b) ? 1 : 0); |
| LESSTHANOREQUAL | 37 | | Signed comparison<br>a = popIntStack();<br>b = popIntStack();<br>pushIntStack((a <= b) ? 1 : 0); |
| ULESSTHAN | 38 | | Unsigned comparison<br>long a; //long is here 64 bit signed integer<br>long b;<br>a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff<br>b = ((long) popIntStack()) & INTMASK;<br>pushIntStack((a < b) ? 1 : 0); |
| ULESSTHANOREQUAL | 39 | | Unsigned comparison<br>long a; //long is here 64 bit signed integer<br>long b;<br>a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff<br>b = ((long) popIntStack()) & INTMASK;<br>pushIntStack((a <= b) ? 1 : 0); |
| EQBRANCH | 55 | | int compare;<br>int target;<br>target = popIntStack() + pc;<br>compare = popIntStack();<br>if (compare == 0)<br>{<br>setPc(target);<br>} else<br>{<br>setPc(pc + 1);<br>} |
| NEQBRANCH | 56 | | int compare;<br>int target;<br>target = popIntStack() + pc;<br>compare = popIntStack();<br>if (compare != 0)<br>{<br>setPc(target);<br>} else<br>{<br>setPc(pc + 1);<br>} |
| MULT | 41 | | Signed 32 bit multiply<br>pushIntStack(popIntStack() * popIntStack()); |
| DIV | 53 | | Signed 32 bit integer divide.<br>a = popIntStack();<br>b = popIntStack();<br>if (b == 0)<br>{<br>// undefined<br>} pushIntStack(a / b); |
| MOD | 54 | | Signed 32 bit integer modulo.<br>a = popIntStack();<br>b = popIntStack();<br>if (b == 0)<br>{<br>// undefined<br>}<br>pushIntStack(a % b); |
| LSHIFTRIGHT | 42 | | unsigned shift right.<br>long shift;<br>long valX;<br>int t;<br>shift = ((long) popIntStack()) & INTMASK;<br>valX = ((long) popIntStack()) & INTMASK;<br>t = (int) (valX >> (shift & 0x3f));<br>pushIntStack(t); |
| ASHIFTLEFT | 43 | | arithmetic(signed) shift left.<br>long shift;<br>long valX;<br>shift = ((long) popIntStack()) & INTMASK;<br>valX = ((long) popIntStack()) & INTMASK;<br>int t = (int) (valX << (shift & 0x3f));<br>pushIntStack(t); |
| ASHIFTRIGHT | 43 | | arithmetic(signed) shift left.<br>long shift;<br>int valX;<br>shift = ((long) popIntStack()) & INTMASK;<br>valX = popIntStack();<br>int t = valX >> (shift & 0x3f);<br>pushIntStack(t); |
| CALL | 45 | | call procedure.<br>int address = pop();<br>push(pc + 1);<br>setPc(address); |
| CALLPCREL | 63 | | call procedure pc relative<br>int address = pop();<br>push(pc + 1);<br>setPc(address+pc); |
| EQ | 46 | | pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); |
| NEQ | 47 | | pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); |
| NEG | 48 | | pushIntStack(-popIntStack()); |
<br>
### Implemented Instructions Comparison Table
![alt text](https://github.com/pdsmart/ZPU/blob/master/docs/ImplInstructions.png)
### Hardware Variable Byte Write
In the original ZPU designs there was scope but not the implementation to allow the ZPU to perform byte/half-word/full-word writes. Either the CPU always had to perform 32bit Word aligned operations or it performed the operation in micro-code.
In the Evo, hardware was implemented (build time selectable) to allow Byte and Half-Word writes and also hardware Read-Update-Write operations. If the hardware Byte/Half-Word logic is not enabled then it falls back to the 32bit Word Read-Update-Write logic. Both methods have performance benefits, the latter taking 3 cycles longer.
### Hardware Debug Serializer
In order to debug the CPU or just provide low level internal operating information, a cached UART debug module is implemented. Currently this is only for output but has the intention to be tied into the IOCP for in-situ debugging when Simulation/Signal-Tap is not available.
Embedded within the CPU RTL are statements which issue snapshot information to the serialiser, if enabled in the configuration along with the information level. This is then serialized and output to a connected terminal. A snapshot of the output information can be seen below (with manual comments):
| ------------------------------------------------------------ |
| 000477 01ffec 00001ae4 00000000 70.17 04770484 046c047c 08f0046c 0b848015 17700500 05000500 05001188 11ef2004 <br/><br/><u>Break Point - Illegal instruction</u><br/>000478 01ffe8 00001ae4 00001ae4 00.05 04780484 046c0478 08f0046c 0b888094 05000500 05000500 118811ef 20041188 <br/><br/><u>L1 Cache Dump</u><br/>000478 (480)-> 11 e2 2a 51 11 a0 11 8f <-(483) (004)->11 ed 20 04 05 00 05 00 05 00 05 00 05 00 05 00 20 (46c)->04 11 b5 11 e4 17 70 <-(46f)<br/> (004)-> 11 ed 20 04 05 00 05 00 05 00 05 00 05 00 05 00 20 (46c)->04 11 b5 11 e4 17 70 11 b6 11 c4 2d 27 11 8b <-(473)<br/> 05 00 05 00 05 00 05 00 (46c)->20 04 11 b5 11 e4 17 70 11 b6 11 c4 2d 27 11 8b 1c 38 11 80 17 71 17 70 -<(477)<br/>(46c)->20 04 11 b5 11 e4 17 70 11 b6 11 c4 2d 27 11 8b 1c 38 11 80 17 71 17 70 -<(477) 05 00 05 00 05 00 05 00 <br/>(470)->11 b6 11 c4 2d 27 11 8b 1c 38 11 80 17 71 17 70 <-(477) -> 05 00 05 00 05 00 05 00 (47c)->11 88 11 ef 20 04 11 88 <-(47f)<br/>(474)->1c 38 11 80 17 71 17 70 05 00 05 00 05 00 05 00 11 88 11 ef 20 04 11 88 11 e2 2a 51 11 a0 11 8f <br/> 05 00 05 00 05 00 05 00 11 88 11 ef 20 04 11 88 11 e2 2a 51 11 a0 11 8f 11 ed 20 04 05 00 05 00 <br/> 11 88 11 ef 20 04 11 88 11 e2 2a 51 11 a0 11 8f 11 ed 20 04 05 00 05 00 05 00 05 00 05 00 05 00 <br/><u>L2 Cache Dump</u><br/>000000 88 08 8c 08 ed 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <br/>000020 88 08 8c 08 90 08 0b 0b 0b 88 80 08 2d 90 0c 8c 0c 88 0c 04 00 00 00 00 00 00 00 00 00 00 00 00 <br/>000040 71 fd 06 08 72 83 06 09 81 05 82 05 83 2b 2a 83 ff ff 06 52 04 00 00 00 00 00 00 00 00 00 00 00 |
All critical information such as current instruction being executed (or not if stalled), Signals/Flags, L1/L2 Cache contents and Memory contents can be output.
# System On a Chip
In order to provide a working framework in which the ZPU Evo could be used, a System On a Chip wrapper was created which allows for the instantiation of various devices (ie. UART/SD card).
As part of the development, the ZPU Small/Medium/Flex models were incorporated into the framework allowing the choice of CPU when fabric space is at a premium or comparing CPU's, albeit features such as Wishbone are not available on the original ZPU models. I didn't include the ZPUino as this design already has a very good eco system or the ZY2000.
The SoC currently implements (in the build tree):
| Component | Selectable (ie not hardwired) |
| ------------------------- | ------------------------------------------------------------ |
| CPU | Choice of ZPU Small, Medium, Flex, Evo or Evo Minimal. |
| Wishbone Bus | Yes, 32 bit bus. |
| (SB) BRAM | Yes, implement a configurable block of BRAM as the boot loader and stack. |
| Instruction Bus BRAM | Yes, enable a separate bus (or Dual-Port) to the boot code implemented in BRAM. This is generally a dual-port BRAM shared with the Sysbus BRAM but can be independent. |
| (SB) RAM | Implement a block of BRAM as RAM, seperate from the BRAM used for the boot loader/stack. |
| (WB) SDRAM | Yes, implement an SDRAM controller over the Wishbone bus. |
| (WB) RAM | Implement a block of BRAM as RAM over the Wishbone bus. |
| (WB) I2C | Yes, implements an I2C Controller over the Wishbone bus. |
| (SB) Timer 0 | No, implements a hardware 12bit Second, 18bit milliSec and 24bit uSec down counter with interrupt, a 32bit milliSec up counter with interrupt and a YMD HMS Real Time Clock. The down counters are ideal for scheduling. |
| (SB) Timer 1 | Yes, a selectable number of pre-scaled 32bit down counters. |
| (SB) UART 0 | No, a cached UART used for monitor output and command input/program load. |
| (SB) UART 1 | No, a cached UART used for software (C program)/hardware (ZPU debug serializer) output. |
| (SB) Interrupt Controller | Yes, a prioritized configurable (# of inputs) interrupt controller. |
| (SB) PS2 | Yes, a PS2 Keyboard and Mouse controller. |
| (SB) SPI | Yes, a configurable number of Serial Peripheral Interface controllers. |
| (SB) SD | Yes, a configurable number of hardware based SPI SD controllers. |
| (SB) SOCCFG | Yes, a set of registers to indicate configuration of the ZPU and SoC to the controlling program. |
Within the SoC configuration, items such as starting Stack Address, Reset Vector, IO Start/End (SB) and (WB) can be specified. Given the wishbone bus, it is very easy to add further opencore IP devices, for the system bus some work may be needed as the opencore IP devices use differing signals.
# Software
The software provided includes:
1. A bootloader, I/O Control Program (IOCP). This is more than a bootloader, in its basic form it can bootstrap an application from an SD card or it can include command line monitor tools and a serial upload function.
2. An application, ZPUTA (ZPU Test Application). This is a test suite and can be organised as a single application or split into a Disk Operating System where all functionality is stored on the SD card. ZPUTA can be bootstrapped by IOCP or standalone as the only program in the ROM/BRAM.
3. A disk operating system, zOS (ZPU Operating System). A version of ZPUTA but aimed at production code where all functionality resides as disk applications.
4. Library functions in C to aid in building applications, including 3rd party libs ie. FatFS from El. Chan
### IOCP
The I/O Control Program (IOCP) is basically a bootloader, it can operate standalone or as the first stage in booting an application. At the time of writing the following functionality and memory maps have been defined in the build.sh and within the parameterisation of the IOCP/ZPUTA/RTL but any other is possible by adjusting the parameters.
- Tiny - IOCP is the smallest size possible to boot from SD Card. It is useful for a SoC configuration where there is limited BRAM and the applications loaded from the SD card would potentially run in external RAM.
- Minimum - As per tiny but adds: print IOCP version, interrupt handler, boot message and SD error messages.
- Medium - As per small but adds: command line processor to add commands below, timer on auto boot so it can be disabled by pressing a key
| Command | Description |
| ------- | ------------------------------------------ |
| 1 | Boot Application in Application area BRAM |
| 4 | Dump out BRAM (boot) memory |
| 5 | Dump out Stack memory |
| 6 | Dump out application RAM |
| C | Clear Application area of BRAM |
| c | Clear Application RAM |
| d | List the SD Cards directory |
| R | Reset the system and boot as per power on |
| h | Print out help on enabled commands |
| i | Prints version information |
- Full - As medium but adds additional commands below.
| Command | Description |
| ------- | ------------------------------------------ |
| 2 | Upload to BRAM application area, in binary format, from serial port |
| 3 | Upload to RAM, in binary format, from serial port |
| i | Print detailed SoC configuration |
### ZPUTA
ZPUTA started life as a basic test application to verify ZPU Evo and SoC operations. As it evolved and different FPGA's were included in the ZPU Evo scope, it became clear that it had to be more advanced due to limited resources.
ZPUTA has two primary methods of exection, a) as an application booted by IOCP, b) standalone booted as the ZPU Evo startup firmware. The mode is chosen in the configuration and functionality is identical.
In order to cater for limited FPGA BRAM resources, all functionality of ZPUTA can be enabled/disabled within the loaded image. If an SD Card is present then some/all functionality can be shifted from the loaded image into applets (1 applet per function, ie. memory clear) and stored on the SD card - this mode is like DOS where typing a command retrieves the applet from SD card and executes it.
The functionality currently provided by ZPUTA can be summarised as follows.
| Category | Command | Parameters | Description |
| -------- | ------- | ---------- | ----------------------------------------------- |
| Disk IO Commands | ddump | \[<pd#> \<sect>] | Dump a sector |
| | dinit | \<pd#> \[\<card type>] | Initialize disk |
| | dstat | \<pd#> | Show disk status |
| | dioctl | \<pd#> | ioctl(CTRL_SYNC) |
| Disk Buffer Commands | bdump | \<ofs> | Dump buffer |
| | bedit | \<ofs> \[\<data>] ... | Edit buffer |
| | bread | \<pd#> \<sect> \[\<num>] | Read into buffer |
| | bwrite | \<pd#> \<sect> \[\<num>] | Write buffer to disk |
| | bfill | \<val> | Fill buffer |
| | blen | \<len> | Set read/write length for fread/fwrite command |
| Filesystem Commands | finit | \<ld#> \[\<mount>] | Force init the volume |
| | fopen | \<mode> \<file> | Open a file |
| | fclose | | Close the open file |
| | fseek | \<ofs> | Move fp in normal seek |
| | fread | \<len> | Read part of file into buffer |
| | finspect | \<len> | Read part of file and examine |
| | fwrite | \<len> \<val> | Write part of buffer into file |
| | ftrunc | | Truncate the file at current fp |
| | falloc | \<fsz> \<opt> | Allocate ctg blks to file |
| | fattr | \<atrr> \<mask> \<name> | Change object attribute |
| | ftime | <y> <m> <d> <h> <M> <s> <fn> | Change object timestamp |
| | frename | \<org name> \<new name> | Rename an object |
| | fdel | \<obj name> | Delete an object |
| | fmkdir | \<dir name> | Create a directory |
| | fstat | \[\<path>] | Show volume status |
| | fdir | \[\<path>] | Show a directory |
| | fcat | \<name> | Output file contents |
| | fcp | \<src file> \<dst file> | Copy a file |
| | fconcat | \<src fn1> \<src fn2> \<dst fn> | Concatenate 2 files |
| | fxtract | \<src> \<dst> \<start pos> \<len> | Extract a portion of file |
| | fload | \<name> \[\<addr>] | Load a file into memory |
| | fexec | \<name> \<ldAddr> \<xAddr> \<mode> | Load and execute file |
| | fsave | \<name> \<addr> \<len> | Save memory range to a file |
| | fdump | \<name> \[\<width>] | Dump a file contents as hex |
| | fcd | \<path> | Change current directory |
| | fdrive | \<path> | Change current drive |
| | fshowdir | | Show current directory |
| | flabel | \<label> | Set volume label |
| | fmkfs | \<ld#> \<type> \<au> | Create FAT volume |
| Memory Commands | mclear | \<start> \<end> \[\<word>] | Clear memory |
| | mcopy | \<start> \<end> \<dst addr> | Copy memory |
| | mdiff | \<start> \<end> \<cmp addr> | Compare memory |
| | mdump | \[\<start> \[\<end>] \[\<size>]] | Dump memory |
| | mtest | \[\<start> \[\<end>] \[iter] | Test memory |
| | meb | \<addr> \<byte> \[...] | Edit memory (Bytes) |
| | meh | \<addr> \<h-word> \[...] | Edit memory (H-Word) |
| | mew | \<addr> \<word> \[...] | Edit memory (Word) |
| Hardware Commands | hid | | Disable Interrupts |
| | hie | | Enable Interrupts |
| | hr | | Display Register Information |
| | ht | | Test uS Timer |
| | hfd | | Disable UART FIFO |
| | hfe | | Enable UART FIFO |
| Performance Testing Commands | dhry | | Dhrystone Test v2.1 |
| | coremark | | CoreMark Test v1.0 |
| Program Execution Commands | call | \<addr> | Call function \@ \<addr> |
| | jmp | \<addr> | Execute code \@ \<addr> |
| Miscellaneous Commands | restart | | Restart application |
| | reset | | Reset system |
| | help | \[\<cmd %>|\<group %>] | Show this screen |
| | info | | Config info |
| | time | \[\<y> \<m> \<d> \<h> \<M> \<s>] | Set/Show current time |
| | test | | Test Screen |
All of the above commands can be disabled, built-in or created as an SD based applet.
### zOS
zOS is under development but is basically an optimised version of ZPUTA stripping out unnecessary logic and targetting it as the primary operating system for ZPU Evo use in my FPGA applications such as the SharpMZ emulator.
### Memory Maps
The currently defined memory maps for IOCP/ZPUTA/Applications are as follows:-
![IOCP Memory Map](https://github.com/pdsmart/ZPU/blob/master/docs/IOCPMemoryMap.png)
For ZPUTA, it can either be configured to be the boot application (ie. no IOCP) or it can be configured as an App booted by IOCP. Depending upon how ZPUTA is built. it can have applets (portions of its functionality created as dedicated executables on the SD card) or standalone with all functionality inbuilt. The former is used when there is limited memory or a set of loadable programs is desired.
![ZPUTA Memory Map](https://github.com/pdsmart/ZPU/blob/master/docs/ZPUTAMemoryMap.png)
<br>
# Build
This section shows how to make a basic build and assumes the target development board is the [QMTECH Cyclone V board](https://github.com/ChinaQMTECH/QM_CYCLONE_V). There are many configuration options but these will be covered seperately.
### Software build
Jenkins can be used to automate the build but for simple get up and go compilation use the build.sh and hierarchical Makefile system following the basic instructions here.
1. Download and install the [ZPU GCC ToolChain](https://github.com/zylin/zpugcc). Install into /opt or similar common area.
2. Setup the environment variable path.
```shell
export PATH=$PATH:/opt/zpu/bin
```
3. Clone the [ZPU Evo](https://github.com/pdsmart/zpu) repository
4. Edit the \<zpu evo dir>/software/zputa/zputa.h file and select which functions you want building into the zputa core image (by default, all functions are built as applets but these will be ignored if they are built into the zputa core image). You select a function by setting the BUILTIN_<utility> to '1', set to '0' if you dont want it built in.
5. Decide which memory map you want and wether ZPUTA will be an application or bootloader (for your own applications, it is they same kind of choice), see build.sh in the table below for options. Once decided, issue the build command.
```shell
cd <zpu evo dir>/software
# For this build we have chosen a Tiny IOCP Bootloader, building ZPUTA as an
# application with a Tiny IOCP bootloader, the ZPUTA Base Address is 0x1000
# and the address where Applets are loaded and executed is at 0xC000
./build.sh -I 3 -O zputa -o 2 -B 0x1000 -A 0xC000
# The build command automatically creates the VHDL BRAM images with the IOCP
# Bootloader installed, thus you will need to build the ZPU Evo SOF bit stream
# and upload it to the FPGA in order for the new Bootloader to be active.
```
6. Place an SD Card into your system and format it for exFAT format then copy the files onto it.
```shell
cd build/SD
cp -r * <abs path to SD card, ie. /media/psmart/ZPU>
# eject the SD card and install it into the SD card reader on your FPGA dev board.
```
### FPGA Bit Stream SOF build
1. Install [Intel Quartus Prime 17.1](http://fpgasoftware.intel.com/17.1/?edition=lite) or later.
2. Open Quartus Prime and load project (File -> Open Project) and select \<zpu evo dir>/build/QMV_zpu.qpf
3. Compile (Processing -> Start)
&nbsp;&nbsp;&nbsp;&nbsp;*alternatively*:-
1. Install [Intel Quartus Prime 17.1](http://fpgasoftware.intel.com/17.1/?edition=lite) or later.
2. Use the Makefile build system by issuing the commands.
```shell
cd <zpu evo dir>/build
make QMV_EVO
```
### Connecting te Development board
1. In order to run the ZPU Evo iand it's software in basic form on the QMTECH board you need 2 USB to Serial (ie. [USB to Serial](https://www.amazon.co.uk/Laqiya-FT232RL-Converter-Adapter-Breakout/dp/B07H6XMC2X)) adapters and you wire them up according to the pinout as is defined in the \<zpu evo dir>/build/QMV_zpu.qsf file. Ensure the adapters are set to 3.3V. See Images section for colour coded wiring.
```shell
##============================================================
# UART
#============================================================
set_location_assignment PIN_AA14 -to UART_RX_0
set_location_assignment PIN_AA15 -to UART_TX_0
set_location_assignment PIN_Y15 -to UART_RX_1
set_location_assignment PIN_AB18 -to UART_TX_1
```
2. Open two Minicom/MobaXterm or equivalent serial consoles, setting the Serial port to one of the USB adapters in each. Setup the Baud Rate to 115200, with 8N1 formatting. Ensure auto line feed is enabled with Carriage Return.
3. Connect the USB Blaster between the QMTECH board and the PC.
4. Connect an SD Card Reader (ie. [SD Card Reader](https://www.amazon.co.uk/s?k=Micro+SD+Card+Reader+Module&i=computers&ref=nb_sb_noss)) to the QMTECH board according to the pinout as is defined in the \<zpu evo dir>/build/QMV_zpu.qsf file. See Images section for colour coded wiring.
```shell
##============================================================
# SD CARD
#============================================================
set_location_assignment PIN_Y17 -to SDCARD_MISO[0]
set_location_assignment PIN_AA18 -to SDCARD_MOSI[0]
set_location_assignment PIN_AA20 -to SDCARD_CLK[0]
set_location_assignment PIN_Y20 -to SDCARD_CS[0]
```
5. Insert the SD card created in the Software build above.
6. Open the Quartus Programmer (ie. Quartus Prime -> Tools -> Programmer), select the sof file via 'Add File' which will be in the directory \<zpu evo dir>/build/QMV_zpu.sof (QMV_EVO.sof if build was via Makefile) and setup the hardware via 'Hardware Setup'.
7. Program the FPGA via 'Start' and on success, in the serial terminal window you will see the ZPUTA sign on message.
<br>
# Repository Structure
The GIT Repository is organised as per the build environment shown in the tables below.
### RTL
| Folder | RTL File | Description |
| ---------------- | -------------------- | ------------------------------------------------------------ |
| \<root> | zpu_soc_pkg.tmpl.vhd | A templated version of zpu_soc_pkg.vhd used by the build/Makefile to configure and make a/all versions of the SoC. |
| | zpu_soc_pkg.vhd | The SoC configuration file, this enables/disables components within the SoC. |
| | zpu_soc.vhd | The SoC definition and glue logic between enabled components. |
| cpu/ | zpu_core_evo.vhd | The ZPU Evo CPU. |
| | zpu_core_flex.vhd | The ZPU Flex CPU re-factored to keep the same style as the Evo and additional hardware debug output added. |
| | zpu_core_medium.vhd | The ZPU Medium (4) CPU re-factored to keep the same style as the Evo and additional hardware debug output added. |
| | zpu_core_small.vhd | The ZPU Small CPU re-factored to keep the same style as the Evo and additional hardware debug output added. |
| | zpu_pkg.vhd | The CPU configuration, bus address width etc. |
| | zpu_uart_debug.vhd | A hardware debug serializer to output runtime data to a connected serial port. |
| devices/sysbus | BRAM | Block RAM RTL |
| | intr | Interrupt Controller |
| | ps2 | PS2 Keyboard/Mouse Controller |
| | RAM | Dual Port RAM |
| | SDMMC | SD Controller |
| | spi | Serial Peripheral Interface Controller |
| | timer | Timer |
| | uart | Full duplex cached UART Controller |
| devices/WishBone | I2C | I2C Controller |
| | SRAM | Encapsulated Byte Addressable BRAM |
| | SDRAM | Byte Addressable 32Bit SDRAM Controller |
| build | CYC1000 | Quartus definition files and Top Level VHDL for the Trenz Electronic CYC1000 Cyclone 10LP development board. |
| | E115 | Quartus definition files and Top Level VHDL for the Cyclone IV EP4CE115 DDR2 64BIT development board. |
| | QMV | Quartus definition files and Top Level VHDL for the QMTech Cyclone V development board. |
| | DE10 | Quartus definition files and Top Level VHDL for the Altera DE10 development board as used in the MiSTer project. |
| | DE0 | Quartus definition files and Top Level VHDL for the Altera DE0 development board. |
| | Clock_* | Refactored Altera PLL definitions for various development board source clocks. These need to be made more generic for eventual inclusion of Xilinx fabric. |
### Software
| Folder | Src File | Description |
| ------- | -------- | ------------------------------------------------------------ |
| apps | | The ZPUTA application can either have a feature embedded or as a separate standalone disk based applet in addition to extended applets. The purpose is to allow control of the ZPUTA application size according to available BRAM and SD card availability.<br/>All applets for ZPUTA are stored in this folder. |
| build | | Build tree output suitable for direct copy to an SD card.<br/> The initial bootloader and/or application as selected are compiled directly into a VHDL file for preloading in BRAM in the devices/sysbus/BRAM folder. |
| common | | Common C modules such as Elm Chan's excellent Fat FileSystem. |
| include | | C Include header files. |
| iocp | | A small bootloader/monitor application for initialization of the ZPU. Depending upon configuration this program can either boot an application from SD card or via the Serial Line and also provide basic tools such as memory examination. |
| startup | | Assembler and Linker files for generating ZPU applications. These files are critical for defining how GCC creates and links binary images as well as providing the micro-code for ZPU instructions not implemented in hardware. |
| utils | | Some small tools for converting binary images into VHDL initialization data. |
| zputa | | The ZPU Test Application. This is an application for testing the ZPU and the SoC components. It can either be built as a single image for pre-loading into a BRAM via VHDL or as a standalone application loaded by the IOCP bootloader from an SD card. The services it provides can either be embedded or available on the SD card as applets depending on memory restrictions. |
| | build.sh | Unix shell script to build IOCP, ZPUTA and Apps for a given design.<br/>NAME<br/> build.sh - Shell script to build a ZPU program or OS.<br/><br/>SYNOPSIS<br/> build.sh [-dOBAh]<br/><br/>DESCRIPTION<br/><br/>OPTIONS<br/> -I < iocp ver > = 0 - Full, 1 - Medium, 2 - Minimum, 3 - Tiny (bootstrap only)<br/> -O < os > = zputa, zos<br/> -o < os ver > = 0 - Standalone, 1 - As app with IOCP Bootloader,<br/> 2 - As app with tiny IOCP Bootloader, 3 - As app in RAM<br/> -B < addr > = Base address of < os >, default 0x01000<br/> -A < addr > = App address of < os >, default 0x0C000<br/> -d = Debug mode.<br/> -h = This help screen.<br/><br/>EXAMPLES<br/> build.sh -I 3 -O zputa -o 2 -B 0x00000 -A 0x50000<br/><br/>EXIT STATUS<br/> 0 The command ran successfully<br/> >0 An error ocurred. |
<br>
# Images
### Images of QMTECH Cyclone V wiring
![SD Card Wiring](https://github.com/pdsmart/ZPU/blob/master/docs/IMG_9837.jpg)
![UART 1 Wiring](https://github.com/pdsmart/ZPU/blob/master/docs/IMG_9838.jpg)
![UART 2 Wiring](https://github.com/pdsmart/ZPU/blob/master/docs/IMG_9839.jpg)
![QMTECH Cyclone V Board](https://github.com/pdsmart/ZPU/blob/master/docs/IMG_9840.jpg)
![Wiring on QMTECH Cyclone V Board](https://github.com/pdsmart/ZPU/blob/master/docs/IMG_9841.jpg)
Above are the wiring connections for the QMTECH Cyclone V board as used in the Build section, colour co-ordinated for reference.
<br>
### Images of ZPUTA on a ZPU EVO CPU
![ZPUTA Performance Test](https://github.com/pdsmart/ZPU/blob/master/docs/ScreenZPU1.png)
Dhrystone and CoreMark performance tests of the ZPU Evo CPU. Depending on Fabric there are slight variations, these tests are on a Cyclone V CEFA chip, on a Cyclone IV CE I7 the results are 11.2DMIPS for Dhrystone and 19.1 for CoreMark.
![ZPUTA Help Screen Test](https://github.com/pdsmart/ZPU/blob/master/docs/ScreenZPU2.png)
Help screen for ZPUTA, help in this instance is an applet on the SD Card. A * before the description indicates the command is on SD, a - indicates the command is built-in.
![ZPUTA SD Directory](https://github.com/pdsmart/ZPU/blob/master/docs/ScreenZPU3.png)
SD Directory listings of all the compiled applets.
<br>
# Links
| Recommended Site |
| ---------------------------------------------------------------------------------------------- |
| [Original Zylin ZPU repository](https://github.com/zylin/zpu) |
| [Original Zylin GCC v3.4.2 toolchain](https://github.com/zylin/zpugcc) |
| [Flex ZPU repository](https://github.com/robinsonb5/ZPUFlex) |
| [ZPUino and Eco System](http://papilio.cc/index.php?n=Papilio.ZPUinoIntroduction) |
| [Wikipedia ZPU Reference](https://en.wikipedia.org/wiki/ZPU_\(microprocessor\)) |
<br>
# Credits
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. All 3rd party software, to my knowledge and research, is open source and freely useable, if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.
<br>
# Licenses
The original ZPU uses the Free BSD license and such the Evo is also released under FreeBSD. SoC components and other developments written by me are currently licensed using the GPL. 3rd party components maintain their original copyright notices.
### The FreeBSD license
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted as representing official policies, either expressed or implied, of the this project.
### The Gnu Public License v3
The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.

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software/apps/mtest/mtest.c
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@@ -65,19 +65,24 @@ void test8bit(uint32_t start, uint32_t end)
unsigned char* memPtr;
unsigned long count;
uint8_t data;
uint32_t errCnt = 0;
xprintf( "\rR/W 8bit ascending test pattern... " );
memPtr = (unsigned char*)( start );
data = 0x00;
count = end - start;
while ( count-- )
while( count-- && errCnt <= 20)
{
*memPtr = data;
if ( *memPtr != data )
if( *memPtr != data )
{
xprintf( "\rError (8bit rwap) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
*memPtr++;
data++;
if ( data >= 0xFF )
if(errCnt++ == 20)
xprintf( "\rError count (8bit rwap) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
data++;
if( data >= 0xFF )
data = 0x00;
}
@@ -85,26 +90,31 @@ void test8bit(uint32_t start, uint32_t end)
memPtr = (unsigned char*)( start );
data = 0x55;
count = end - start;
while ( count-- )
errCnt = 0;
while( count-- && errCnt <= 20)
{
*memPtr = data;
if ( *memPtr != data )
if( *memPtr != data )
{
xprintf( "\rError (8bit rwwp) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
*memPtr++;
if ( data == 0x55 )
data = 0xAA;
else
data = 0x55;
if(errCnt++ == 20)
xprintf( "\rError count (8bit rwwp) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
if( data == 0x55 )
data = 0xAA;
else
data = 0x55;
}
xprintf( "\rWrite 8bit ascending test pattern... " );
memPtr = (unsigned char*)( start );
data = 0x00;
count = end - start;
while ( count-- )
while( count-- )
{
*memPtr++ = data++;
if ( data >= 0xFF )
if( data >= 0xFF )
data = 0x00;
}
@@ -112,18 +122,18 @@ void test8bit(uint32_t start, uint32_t end)
memPtr = (unsigned char*)( start );
data = 0x00;
count = end - start;
while ( count-- )
errCnt = 0;
while( count-- && errCnt <= 20)
{
if ( *memPtr != data )
{
if ( *memPtr != data )
xprintf( "\rError (8bit ap2) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
else
xprintf( "\rError (8bit ap) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
}
if( *memPtr != data )
{
xprintf( "\rError (8bit ap) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
if(errCnt++ == 20)
xprintf( "\rError count (8bit ap) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
data++;
if ( data >= 0xFF )
if( data >= 0xFF )
data = 0x00;
}
@@ -131,12 +141,12 @@ void test8bit(uint32_t start, uint32_t end)
memPtr = (unsigned char*)( start );
data = 0x55;
count = end - start;
while ( count-- )
while( count-- )
{
*memPtr++ = data;
if ( data == 0x55 )
if( data == 0x55 )
data = 0xAA;
else
else
data = 0x55;
}
@@ -144,19 +154,19 @@ void test8bit(uint32_t start, uint32_t end)
memPtr = (unsigned char*)( start );
data = 0x55;
count = end - start;
while ( count-- )
errCnt = 0;
while( count-- && errCnt <= 20)
{
if ( *memPtr != data )
{
if ( *memPtr != data )
xprintf( "\rError (8bit wp2) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
else
xprintf( "\rError (8bit wp) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
}
if( *memPtr != data )
{
xprintf( "\rError (8bit wp) at 0x%08lX (%02x:%02x)\n", memPtr, *memPtr, data );
if(errCnt++ == 20)
xprintf( "\rError count (8bit wp) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
if ( data == 0x55 )
if( data == 0x55 )
data = 0xAA;
else
else
data = 0x55;
}
}
@@ -165,18 +175,19 @@ void test8bit(uint32_t start, uint32_t end)
void test16bit(uint32_t start, uint32_t end)
{
// Locals.
uint16_t *memPtr;
uint32_t count;
uint16_t data;
uint16_t *memPtr;
uint32_t count;
uint16_t data;
uint32_t errCnt = 0;
xprintf( "\rWrite 16bit ascending test pattern... " );
memPtr = (uint16_t*)( start );
data = 0x00;
count = end - start;
while ( count > 0 )
while( count > 0 )
{
*memPtr++ = data++;
if ( data >= 0xFFFF )
if( data >= 0xFFFF )
data = 0x00;
count = count > 2 ? count -= 2 : 0;
}
@@ -185,13 +196,17 @@ void test16bit(uint32_t start, uint32_t end)
memPtr = (uint16_t*)( start );
data = 0x00;
count = end - start;
while ( count > 0 )
while( count > 0 && errCnt <= 20)
{
if ( *memPtr != data )
if( *memPtr != data )
{
xprintf( "\rError (16bit ap) at 0x%08lX (%04x:%04x)\n", memPtr, *memPtr, data );
if(errCnt++ == 20)
xprintf( "\rError count (8bit wp) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
data++;
if ( data >= 0xFFFF )
if( data >= 0xFFFF )
data = 0x00;
count = count > 2 ? count -= 2 : 0;
}
@@ -200,12 +215,12 @@ void test16bit(uint32_t start, uint32_t end)
memPtr = (uint16_t*)( start );
data = 0xAA55;
count = end - start;
while ( count > 0 )
while( count > 0 )
{
*memPtr++ = data;
if ( data == 0xAA55 )
if( data == 0xAA55 )
data = 0x55AA;
else
else
data = 0xAA55;
count = count > 2 ? count -= 2 : 0;
}
@@ -214,14 +229,19 @@ void test16bit(uint32_t start, uint32_t end)
memPtr = (uint16_t*)( start );
data = 0xAA55;
count = end - start;
while ( count > 0 )
errCnt = 0;
while( count > 0 && errCnt <= 20)
{
if ( *memPtr != data )
if( *memPtr != data )
{
xprintf( "\rError (16bit wp) at 0x%08lX (%04x:%04x)\n", memPtr, *memPtr, data );
if(errCnt++ == 20)
xprintf( "\rError count (8bit wp) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
if ( data == 0xAA55 )
if( data == 0xAA55 )
data = 0x55AA;
else
else
data = 0xAA55;
count = count > 2 ? count -= 2 : 0;
}
@@ -231,18 +251,19 @@ void test16bit(uint32_t start, uint32_t end)
void test32bit(uint32_t start, uint32_t end)
{
// Locals.
uint32_t *memPtr;
uint32_t count;
uint32_t data;
uint32_t *memPtr;
uint32_t count;
uint32_t data;
uint32_t errCnt = 0;
xprintf( "\rWrite 32bit ascending test pattern... " );
memPtr = (uint32_t*)( start );
data = 0x00;
count = end - start;
while ( count > 0 )
while( count > 0 )
{
*memPtr++ = data++;
if ( data >= 0xFFFFFFFE )
if( data >= 0xFFFFFFFE )
data = 0x00;
count = count > 4 ? count -= 4 : 0;
}
@@ -251,13 +272,17 @@ void test32bit(uint32_t start, uint32_t end)
memPtr = (uint32_t*)( start );
data = 0x00;
count = end - start;
while ( count > 0 )
while( count > 0 && errCnt <= 20)
{
if ( *memPtr != data )
if( *memPtr != data )
{
xprintf( "\rError (32bit ap) at 0x%08lX (%08lx:%08lx)\n", memPtr, *memPtr, data );
if(errCnt++ == 20)
xprintf( "\rError count (8bit wp) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
data++;
if ( data >= 0xFFFFFFFE )
if( data >= 0xFFFFFFFE )
data = 0;
count = count > 4 ? count -= 4 : 0;
}
@@ -266,12 +291,12 @@ void test32bit(uint32_t start, uint32_t end)
memPtr = (uint32_t*)( start );
data = 0xAA55AA55;
count = end - start;
while ( count > 0 )
while( count > 0 )
{
*memPtr++ = data;
if ( data == 0xAA55AA55 )
if( data == 0xAA55AA55 )
data = 0x55AA55AA;
else
else
data = 0xAA55AA55;
count = count > 4 ? count -= 4 : 0;
}
@@ -281,14 +306,19 @@ void test32bit(uint32_t start, uint32_t end)
data = 0x00;
data = 0xAA55AA55;
count = end - start;
while ( count > 0 )
errCnt = 0;
while( count > 0 && errCnt <= 20)
{
if ( *memPtr != data )
if( *memPtr != data )
{
xprintf( "\rError (32bit wp) at 0x%08lX (%08lx:%08lx)\n", memPtr, *memPtr, data );
if(errCnt++ == 20)
xprintf( "\rError count (8bit wp) > 20, stopping test.\n", memPtr, *memPtr, data );
}
*memPtr++;
if ( data == 0xAA55AA55 )
if( data == 0xAA55AA55 )
data = 0x55AA55AA;
else
else
data = 0xAA55AA55;
count = count > 4 ? count -= 4 : 0;
}
@@ -310,21 +340,21 @@ uint32_t app(uint32_t param1, uint32_t param2)
uint32_t idx;
// Get parameters or use defaults if not provided.
if (!xatoi(&ptr, &startAddr))
if(!xatoi(&ptr, &startAddr))
{
if(cfgSoC->implInsnBRAM) { startAddr = cfgSoC->addrInsnBRAM; }
else if(cfgSoC->implBRAM) { startAddr = cfgSoC->addrBRAM; }
else if(cfgSoC->implRAM || cfgSoC->implDRAM) { startAddr = cfgSoC->addrRAM; }
else { startAddr = cfgSoC->stackStartAddr - 512; }
}
if (!xatoi(&ptr, &endAddr))
if(!xatoi(&ptr, &endAddr))
{
if(cfgSoC->implInsnBRAM) { endAddr = cfgSoC->sizeInsnBRAM; }
else if(cfgSoC->implBRAM) { endAddr = cfgSoC->sizeBRAM; }
else if(cfgSoC->implRAM || cfgSoC->implDRAM) { endAddr = cfgSoC->sizeRAM; }
else { endAddr = cfgSoC->stackStartAddr + 8; }
}
if (!xatoi(&ptr, &iterations))
if(!xatoi(&ptr, &iterations))
{
iterations = 1;
}

2
zpu_soc_pkg.tmpl.vhd
View File

@@ -53,6 +53,8 @@ package zpu_soc_pkg is
-- Frequencies for the various boards.
--
constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board
constant SYSCLK_QMV_FREQ : integer := 100000000; -- QMTECH Cyclone V FPGA Board
constant SYSCLK_DE0_FREQ : integer := 100000000; -- DE0-Nano FPGA Board
constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board
constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board

189
zpu_soc_pkg.vhd
View File

@@ -1,31 +1,37 @@
---------------------------------------------------------------------------------------------------------
-- ZPU
--
-- Name: zpu_soc_pkg.vhd
-- Created: January 2019
-- Author(s): Philip Smart
-- Description: ZPU System On a Chip Configuration
--
-- This module contains the System on a Chip configuration for the ZPU.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: January 2019 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
-- Copyright 2004-2008 oharboe - <20>yvind Harboe - oyvind.harboe@zylin.com
-- Copyright 2018-2019 psmart - Philip Smart
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
library pkgs;
@@ -47,7 +53,8 @@ package zpu_soc_pkg is
-- Frequencies for the various boards.
--
constant SYSCLK_E115_FREQ : integer := 100000000; -- E115 FPGA Board
constant SYSCLK_QMV_FREQ : integer := 100000000; -- QM CycloneV FPGA Board
constant SYSCLK_QMV_FREQ : integer := 100000000; -- QMTECH Cyclone V FPGA Board
constant SYSCLK_DE0_FREQ : integer := 100000000; -- DE0-Nano FPGA Board
constant SYSCLK_DE10_FREQ : integer := 100000000; -- DE10-Nano FPGA Board
constant SYSCLK_CYC1000_FREQ : integer := 100000000; -- Trenz CYC1000 FPGA Board
@@ -98,8 +105,8 @@ package zpu_soc_pkg is
constant SOC_MAX_ADDR_BRAM_BIT : integer := 16; -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same.
constant SOC_ADDR_BRAM_START : integer := 0; -- Start address of BRAM.
constant SOC_ADDR_BRAM_END : integer := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT); -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_MAX_ADDR_RAM_BIT : integer := 24; -- Max address bit of the System RAM.
constant SOC_ADDR_RAM_START : integer := (2**(maxAddrBit-WB_ACTIVE)); -- Start address of RAM.
constant SOC_MAX_ADDR_RAM_BIT : integer := 23; -- Max address bit of the System RAM.
constant SOC_ADDR_RAM_START : integer := 16777216; -- Start address of RAM.
constant SOC_ADDR_RAM_END : integer := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT); -- End address of RAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
constant SOC_MAX_ADDR_INSN_BRAM_BIT: integer := SOC_MAX_ADDR_BRAM_BIT; -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words.
constant SOC_ADDR_INSN_BRAM_START : integer := 0; -- Start address of dedicated instrution BRAM.
@@ -109,8 +116,8 @@ package zpu_soc_pkg is
constant SOC_STACK_ADDR : integer := SOC_ADDR_BRAM_END - 8; -- Stack start address (BRAM/RAM).
constant SOC_ADDR_IO_START : integer := (2**(maxAddrBit-WB_ACTIVE)) - (2**maxIOBit); -- Start address of the Evo Direct Memory Mapped IO region.
constant SOC_ADDR_IO_END : integer := (2**(maxAddrBit-WB_ACTIVE)) - 1; -- End address of the Evo Direct Memory Mapped IO region.
constant SOC_WB_IO_START : integer := (2**(maxAddrBit)) - (2**maxIOBit); -- Start address of IO range.
constant SOC_WB_IO_END : integer := (2**(maxAddrBit)) - 1; -- End address of IO range.
constant SOC_WB_IO_START : integer := 32505856; -- Start address of IO range.
constant SOC_WB_IO_END : integer := 33554431; -- End address of IO range.
-- Ranges used throughout the SOC source.
subtype ADDR_BIT_BRAM_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0; -- Address range of the onboard B(lock)RAM - 1 byte aligned
@@ -124,12 +131,16 @@ package zpu_soc_pkg is
subtype IO_DECODE_RANGE is natural range maxAddrBit-WB_ACTIVE-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
-- subtype WB_IO_DECODE_RANGE is natural range maxAddrBit-1 downto maxIOBit; -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
-- Start byte address of stack for non-EVO CPU. Point to top of BRAM or a dedicated blcck of RAM - 2*words. Once booted the stack frame can be shifted to any memory location.
-- constant spStart : std_logic_vector(maxAddrBit-1 downto 0) := std_logic_vector(to_unsigned((2**(SOC_MAX_ADDR_BRAM_BIT))-8, maxAddrBit));
-- Device options
type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards.
------------------------------------------------------------
-- Constants
-- constants
------------------------------------------------------------
constant YES : std_logic := '1';
@@ -141,17 +152,17 @@ package zpu_soc_pkg is
constant HIZ : std_logic := 'Z';
------------------------------------------------------------
-- Function prototypes
-- functions
------------------------------------------------------------
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
------------------------------------------------------------
-- Records
-- records
------------------------------------------------------------
------------------------------------------------------------
-- Components
-- components
------------------------------------------------------------
component dualport_ram is
port (
@@ -167,6 +178,24 @@ package zpu_soc_pkg is
);
end component;
component cacheL2 is
generic (
MAX_CACHE_BITS : integer := 12
);
port (
clk : in std_logic;
areset : in std_logic := '0';
memAWriteEnable : in std_logic;
memAAddr : in std_logic_vector(MAX_CACHE_BITS-3 downto 0);
memAWrite : in std_logic_vector(55 downto 0);
memBWriteEnable : in std_logic;
memBAddr : in std_logic_vector(MAX_CACHE_BITS-3 downto 0);
memBWrite : in std_logic_vector(55 downto 0);
memARead : out std_logic_vector(55 downto 0);
memBRead : out std_logic_vector(55 downto 0)
);
end component;
component dpram
generic (
init_file : string;
@@ -194,6 +223,41 @@ package zpu_soc_pkg is
);
end component;
component signed_divider is
port (
clk : in std_logic;
ena : in std_logic;
z : in unsigned(63 downto 0);
d : in unsigned(WORD_32BIT_RANGE);
q : out signed(63 downto 0);
s : out signed(63 downto 0)
);
end component;
component unsigned_divider is
port (
clk : in std_logic;
ena : in std_logic;
z : in unsigned(63 downto 0);
d : in unsigned(WORD_32BIT_RANGE);
q : out unsigned(WORD_32BIT_RANGE);
s : out unsigned(WORD_32BIT_RANGE);
div0 : out std_logic;
ovf : out std_logic
);
end component;
component qdiv is
port (
dividend : in signed(WORD_32BIT_RANGE);
divisor : in signed(WORD_32BIT_RANGE);
start : in std_logic;
clk : in std_logic;
quotient_out : out signed(WORD_32BIT_RANGE);
complete : out std_logic
);
end component;
component SDCard is
generic (
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
@@ -224,22 +288,49 @@ package zpu_soc_pkg is
);
end component;
component sdram_v is
port (
-- interface to the MT48LC16M16 chip
sd_clk : in std_logic; -- sdram is accessed at 128MHz
sd_rst : in std_logic; -- reset the sdram controller.
sd_cke : out std_logic; -- clock enable.
sd_dq : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
sd_addr : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
sd_dqm : out std_logic_vector(1 downto 0); -- two byte masks
sd_ba : out std_logic_vector(1 downto 0); -- two banks
sd_cs_n : out std_logic; -- a single chip select
sd_we_n : out std_logic; -- write enable
sd_ras_n : out std_logic; -- row address select
sd_cas_n : out std_logic; -- columns address select
sd_ready : out std_logic; -- sd ready.
-- cpu/chipset interface
wb_clk : in std_logic; -- 32MHz chipset clock to which sdram state machine is synchonized
wb_dat_i : in std_logic_vector(31 downto 0); -- data input from chipset/cpu
wb_dat_o : out std_logic_vector(31 downto 0); -- data output to chipset/cpu
wb_ack : out std_logic;
wb_adr : in std_logic_vector(23 downto 0); -- lower 2 bits are ignored.
wb_sel : in std_logic_vector(3 downto 0);
wb_cti : in std_logic_vector(2 downto 0); -- cycle type.
wb_stb : in std_logic;
wb_cyc : in std_logic; -- cpu/chipset requests cycle
wb_we : in std_logic -- cpu/chipset requests write
);
end component;
end zpu_soc_pkg;
------------------------------------------------------------
-- Function definitions.
------------------------------------------------------------
package body zpu_soc_pkg is
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
end package body;