178 lines
7.5 KiB
VHDL
178 lines
7.5 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.zpu_soc_pkg.all;
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entity E115_zpu is
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port (
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-- Clock
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CLOCK_25 : in std_logic;
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-- LED
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LED : out std_logic_vector(7 downto 0);
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-- Debounced keys
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KEY : in std_logic_vector(1 downto 0);
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-- DIP switches
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SW : in std_logic_vector(3 downto 0);
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-- TDI : in std_logic;
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-- TCK : in std_logic;
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-- TCS : in std_logic;
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-- TDO : out std_logic;
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-- I2C_SDAT : inout std_logic;
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-- I2C_SCLK : out std_logic;
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-- GPIO_0 : inout std_logic_vector(33 downto 0);
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-- GPIO_1 : inout std_logic_vector(33 downto 0);
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-- SD Card 1
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SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
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-- UART Serial channels.
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UART_RX_0 : in std_logic;
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UART_TX_0 : out std_logic;
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UART_RX_1 : in std_logic;
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UART_TX_1 : out std_logic
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-- DDR2 DRAM
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--DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus
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--DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus
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--DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus
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--DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks
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--DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus
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--DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks
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--DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects.
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--DDR2_WE : out std_logic; -- write enable
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--DDR2_RAS : out std_logic; -- row address select
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--DDR2_CAS : out std_logic; -- columns address select
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--DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable.
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--DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks.
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);
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END entity;
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architecture rtl of E115_zpu is
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signal reset : std_logic;
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signal sysclk : std_logic;
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signal memclk : std_logic;
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signal pll_locked : std_logic;
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--signal ps2m_clk_in : std_logic;
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--signal ps2m_clk_out : std_logic;
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--signal ps2m_dat_in : std_logic;
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--signal ps2m_dat_out : std_logic;
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--signal ps2k_clk_in : std_logic;
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--signal ps2k_clk_out : std_logic;
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--signal ps2k_dat_in : std_logic;
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--signal ps2k_dat_out : std_logic;
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--alias PS2_MDAT : std_logic is GPIO_1(19);
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--alias PS2_MCLK : std_logic is GPIO_1(18);
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begin
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--I2C_SDAT <= 'Z';
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--GPIO_0(33 downto 2) <= (others => 'Z');
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--GPIO_1 <= (others => 'Z');
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--LED <= "101010" & reset & UART_RX_0;
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LED <= "00000000";
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mypll : entity work.Clock_25to100
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port map
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(
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inclk0 => CLOCK_25,
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c0 => sysclk,
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c1 => memclk,
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locked => pll_locked
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);
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reset<=(not SW(0) xor KEY(0)) and pll_locked;
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myVirtualToplevel : entity work.zpu_soc
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generic map
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(
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SYSCLK_FREQUENCY => SYSCLK_E115_FREQ
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)
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port map
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(
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SYSCLK => sysclk,
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MEMCLK => memclk,
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RESET_IN => reset,
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-- RS232
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UART_RX_0 => UART_RX_0,
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UART_TX_0 => UART_TX_0,
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UART_RX_1 => UART_RX_1,
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UART_TX_1 => UART_TX_1,
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-- SPI signals
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SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
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SPI_MOSI => open,
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SPI_CLK => open,
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SPI_CS => open,
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-- SD Card (SPI) signals
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SDCARD_MISO => SDCARD_MISO,
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SDCARD_MOSI => SDCARD_MOSI,
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SDCARD_CLK => SDCARD_CLK,
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SDCARD_CS => SDCARD_CS,
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-- PS/2 signals
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PS2K_CLK_IN => '1',
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PS2K_DAT_IN => '1',
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PS2K_CLK_OUT => open,
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PS2K_DAT_OUT => open,
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PS2M_CLK_IN => '1',
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PS2M_DAT_IN => '1',
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PS2M_CLK_OUT => open,
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PS2M_DAT_OUT => open,
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-- I²C signals
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I2C_SCL_IO => open,
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I2C_SDA_IO => open,
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-- IOCTL Bus --
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IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
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IOCTL_UPLOAD => open, -- Uploading from FPGA.
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IOCTL_CLK => open, -- I/O Clock.
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IOCTL_WR => open, -- Write Enable to FPGA.
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IOCTL_RD => open, -- Read Enable from FPGA.
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IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
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IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
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IOCTL_ADDR => open, -- Address in FPGA to write into.
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IOCTL_DOUT => open, -- Data to be written into FPGA.
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IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
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-- SDRAM signals which do not exist on the E115
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SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
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SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
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SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
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SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
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SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
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SDRAM_BA => open, --SDRAM_BA, -- two banks
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SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
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SDRAM_WE_n => open, --SDRAM_WE, -- write enable
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SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
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SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
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SDRAM_READY => open -- sd ready.
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-- DDR2 DRAM
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--DDR2_ADDR => DDR2_ADDR, -- 14 bit multiplexed address bus
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--DDR2_DQ => DDR2_DQ, -- 64 bit bidirectional data bus
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--DDR2_DQS => DDR2_DQS, -- 8 bit bidirectional data bus
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--DDR2_DQM => DDR2_DQM, -- eight byte masks
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--DDR2_ODT => DDR2_ODT, -- 14 bit multiplexed address bus
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--DDR2_BA => DDR2_BA, -- 8 banks
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--DDR2_CS => DDR2_CS, -- 2 chip selects.
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--DDR2_WE => DDR2_WE, -- write enable
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--DDR2_RAS => DDR2_RAS, -- row address select
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--DDR2_CAS => DDR2_CAS, -- columns address select
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--DDR2_CKE => DDR2_CKE, -- 2 clock enable.
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--DDR2_CLK => DDR2_CLK -- 2 clocks.
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);
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end architecture;
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