Fix FPGA build failures for CYC1000 and DE0_nano, add STcache to all boards

- Add zpu_core_evo_STcache.vhd to QSF files for DE10_nano, QMV, CYC1000,
  and DE0_nano (was only in E115). Required by the stack cache feature
  in zpu_core_evo.vhd.
- Enable WishBone SDRAM QIP (W9864G6) for CYC1000 - fixes missing
  WBSDRAM entity error.
- Enable sysbus SDRAM QIP (W9864G6) for DE0_nano - fixes missing
  SDRAM entity error.

Quartus needs all referenced entities in the library even when inside
inactive generate blocks (BOARD_E115=true for all pipeline builds).

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

README.md

@@ -1,20 +1,26 @@
+# ZPU
+
+**Website:** [engineers@work](https://eaw.app) | **Repository:** [git.eaw.app/eaw/ZPU](https://git.eaw.app/eaw/ZPU)
+
+---
+
 <br>
 The ZPU is a 32bit Stack based microprocessor and was originally designed by Øyvind Harboe from [Zylin AS](https://opensource.zylin.com/) and original documentation can be found on the [Zylin/OpenCore website or Wikipedia](https://en.wikipedia.org/wiki/ZPU_\(microprocessor\)). It is a microprocessor intended for FPGA embedded applications with minimal logic element and BRAM usage with the sacrifice of speed of execution. 
 
 Zylin produced two designs which it made open source, namely the Small and Medium ZPU versions. Additional designs were produced by external developers such as the Flex and ZPUino variations, each offering enhancements to the original design such as Wishbone interface, performance etc.
 
-This document describes another design which I like to deem as the ZPU Evo(lution) model whose focus is on *performance*, *connectivity* and *instruction expansion*. This came about as I needed a CPU for an emulator of a vintage computer i am writing which would act as the IO processor to provide Menu, Peripheral and SD services.
+This document describes another design which I like to deem as the ZPU Evo(lution) model whose focus is on *performance*, *connectivity* and *instruction expansion*. This came about as I needed a CPU for an emulator of a vintage computer I am writing which would act as the IO processor to provide Menu, Peripheral and SD services.
 
-An example of the *performance* of the ZPU Evo can be seen using CoreMark which returns a value of 22.2 @ 100MHz on Altera fabric using BRAM and for Dhrystone 13.2DMIPS. Comparisons can be made with the original ZPU designs in the gallery below paying attention to the CoreMark score which seems to be the defacto standard now. *Connectivity* can be seen via implementation of both System and Wishbone buses, allowing for connection of many opensource IP devices. *Instruction expansion* can be seen by the inclusion of a close coupled L1 cache where multiple instruction bytes are sourced and made available to the CPU which in turn can be used for optimization (ie. upto 5 IM instructions executed in 1 cycle) or for extended multi-byte instructions (ie. implementation of a LoaD Increment Repeat instruction). There is room for a lot more improvements such as stack cache, SDRAM to L2 burst mode, parallel instruction execution (ie. and + neqbranch) which are on my list.
+An example of the *performance* of the ZPU Evo can be seen using CoreMark which returns a value of 22.2 @ 100MHz on Altera fabric using BRAM and for Dhrystone 13.2DMIPS. Comparisons can be made with the original ZPU designs in the gallery below paying attention to the CoreMark score which seems to be the defacto standard now. *Connectivity* can be seen via implementation of both System and Wishbone buses, allowing for connection of many opensource IP devices. *Instruction expansion* can be seen by the inclusion of a close coupled L1 cache where multiple instruction bytes are sourced and made available to the CPU which in turn can be used for optimization (ie. up to 5 IM instructions executed in 1 cycle) or for extended multi-byte instructions (ie. implementation of a LoaD Increment Repeat instruction). There is room for a lot more improvements such as stack cache, SDRAM to L2 burst mode, parallel instruction execution (ie. and + neqbranch) which are on my list.
 
 
-## The CPU
+## <font style="color: yellow;" size="6">The CPU</font>
 
-The ZPU Evo follows on from the ZPU Medium and Flex and areas of the code are similar, for example the instruction decoding. The design differs though due to caching and implementation of a Memory Transaction Processor where all Memory/IO operations (except for direct Instruction reads if dual-port instruction bus is enabled) are routed. The original CPU's all handled their memory requirements in-situ or part of the state machine whereas the Evo submits a request to the MXP whenever a memory operation is required.
+The ZPU Evo follows on from the ZPU Medium and Flex and areas of the code are similar, for example the instruction decoding. The design differs though due to caching and implementation of a Memory Transaction Processor where all Memory/IO operations (except for direct Instruction reads if dual-port instruction bus is enabled) are routed. The original CPUs all handled their memory requirements in-situ or part of the state machine whereas the Evo submits a request to the MXP whenever a memory operation is required.
 
 The following sections indicate some of the features and changes to original ZPU designs.
 
-### Bus structure
+### <font style="color: yellow;" size="5">Bus structure</font>
 
 The ZPU has a linear address space with all memory and IO devices directly addressable within this space. Existing ZPU designs either provide a system bus or a wishbone bus whereas the Evo provides both. The ZPU Evo creates up to two distinct regions within the address space depending on configuration, to provide a *system bus* and a *wishbone bus*.
 
@@ -24,17 +30,17 @@ If configured, a wishbone bus can be instantiated and this extends the maximum a
 
 A third bus can be configured, which is for instruction reads only. This bus typically shadows the system bus in memory region but is deemed to be connected to fast access memory for reading of instructions without the need for L2 Cache. This would typically be the 2nd port of a dual-port BRAM block with the 1st port connected to the system bus. 
 
-### L1 Cache
+### <font style="color: yellow;" size="5">L1 Cache</font>
 
 In order to gain performance but more especially for instruction optimisations and extended instructions, an L1 cache is implemented using registers. Using registers consumes fabric space so should be very small but it allows random access in a single cycle which is needed for example if compacting a 32bit IM load (which can be 5 instructions) into a single cycle. Also for extended instructions, the first byte indicates an extended instruction and the following 1-5 bytes defines the instruction which is then executed in a single cycle.
 
-### L2 Cache
+### <font style="color: yellow;" size="5">L2 Cache</font>
 
-Internal BRAM (on-board Block RAM within the FPGA) doesn't need an L2 Cache as it's access time is 1-2 cycles. As BRAM is a limited resource it is assumed external RAM or SDRAM will be used which is much slower and this needs to be cached to increase throughput. The L2 Cache is used for this purpose, to read ahead a block of external RAM and feed the L1 Cache as needed. On analysis, the C programs generated by GCC are typically loops and calls within a local area (unless using large libraries), so implementing a simple direct mapping cache between external RAM and BRAM (used for the L2 Cache) indexed relative to the Program Counter is sufficient to keep the CPU from stalling most of the time.
+Internal BRAM (on-board Block RAM within the FPGA) doesn't need an L2 Cache as its access time is 1-2 cycles. As BRAM is a limited resource it is assumed external RAM or SDRAM will be used which is much slower and this needs to be cached to increase throughput. The L2 Cache is used for this purpose, to read ahead a block of external RAM and feed the L1 Cache as needed. On analysis, the C programs generated by GCC are typically loops and calls within a local area (unless using large libraries), so implementing a simple direct mapping cache between external RAM and BRAM (used for the L2 Cache) indexed relative to the Program Counter is sufficient to keep the CPU from stalling most of the time.
 
-### Instruction Set
+### <font style="color: yellow;" size="5">Instruction Set</font>
 
-A feature of the ZPU is it's use of a minimal fixed set of hardware implemented instructions and a soft set of additional instructions which are implemented in pseudo micro-code (ie. the fixed set of instructions). This is achieved by 32byte vectors in the region 0x0000 - 0x0400 and each soft instruction branches to the vector if it is not implemented in hardware. The benefit is reduced FPGA resources but the penalty is performance.
+A feature of the ZPU is its use of a minimal fixed set of hardware implemented instructions and a soft set of additional instructions which are implemented in pseudo micro-code (ie. the fixed set of instructions). This is achieved by 32byte vectors in the region 0x0000 - 0x0400 and each soft instruction branches to the vector if it is not implemented in hardware. The benefit is reduced FPGA resources but the penalty is performance.
 
 The ZPU Evo implements all instructions in hardware but this can be adjusted in the configuration to use soft instructions if required in order to conserve FPGA resources. This allows for a balance of resources versus performance. Ultimately though, if resources are tight then the use of the Small/Flex ZPU models may be a better choice.
 
@@ -51,7 +57,7 @@ Where ParamSize =
 Some extended instructions are under development (ie. LDIR) an exact opcode value and extended instruction set has not yet been fully defined. The GNU AS assembler will be updated with these instructions so they can be invoked within a C program and eventually if they have benefit to C will be migrated into the GCC compiler (ie. ADD32/DIV32/MULT32/LDIR/LDDR as from what I have seen, these will have a big impact on CoreMark/Dhrystone tests).
 
 
-### Implemented Instruction Set
+### <font style="color: yellow;" size="5">Implemented Instruction Set</font>
 
 | Name              |  Opcode     | Description                                                                                                                                                                                                                                                            |
 | ----------------  |  ---------  | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
@@ -109,17 +115,17 @@ Some extended instructions are under development (ie. LDIR) an exact opcode valu
 *\** = Emulated instruction if not implemented in hardware.
 <br>
 
-### Implemented Instructions Comparison Table
+### <font style="color: yellow;" size="5">Implemented Instructions Comparison Table</font>
 
 ![alt text](../images/ImplInstructions.png)
 
-### Hardware Variable Byte Write
+### <font style="color: yellow;" size="5">Hardware Variable Byte Write</font>
 
 In the original ZPU designs there was scope but not the implementation to allow the ZPU to perform byte/half-word/full-word writes. Either the CPU always had to perform 32bit Word aligned operations or it performed the operation in micro-code.
 
 In the Evo, hardware was implemented (build time selectable) to allow Byte and Half-Word writes and also hardware Read-Update-Write operations. If the hardware Byte/Half-Word logic is not enabled then it falls back to the 32bit Word Read-Update-Write logic. Both methods have performance benefits, the latter taking 3 cycles longer.
 
-### Hardware Debug Serializer
+### <font style="color: yellow;" size="5">Hardware Debug Serializer</font>
 
 In order to debug the CPU or just provide low level internal operating information, a cached UART debug module is implemented. Currently this is only for output but has the intention to be tied into the IOCP for in-situ debugging when Simulation/Signal-Tap is not available.
 
@@ -131,16 +137,16 @@ Embedded within the CPU RTL are selectable level triggered statements which issu
 
 All critical information such as current instruction being executed (or not if stalled), Signals/Flags, L1/L2 Cache contents and Memory contents can be output.
 
-### Timing Constraints
+### <font style="color: yellow;" size="5">Timing Constraints</font>
 
 This is a work in progress, I am slowly updating the design and/or adding constraints such that timing is fully met. Currently there is negative slack at 100MHz albeit the design fully works, this will in the future be corrected so timing as analyzed by TimeQuest will be met.
 
 
-## System On a Chip
+## <font style="color: yellow;" size="6">System On a Chip</font>
 
 In order to provide a working framework in which the ZPU Evo could be used, a System On a Chip wrapper was created which allows for the instantiation of various devices (ie. UART/SD card). 
 
-As part of the development, the ZPU Small/Medium/Flex models were incorporated into the framework allowing the choice of CPU when fabric space is at a premium or comparing CPU's, albeit features such as Wishbone are not available on the original ZPU models. I didn't include the ZPUino as this design already has a very good eco system or the ZY2000.
+As part of the development, the ZPU Small/Medium/Flex models were incorporated into the framework allowing the choice of CPU when fabric space is at a premium or comparing CPUs, albeit features such as Wishbone are not available on the original ZPU models. I didn't include the ZPUino as this design already has a very good eco system or the ZY2000.
 
 The SoC currently implements (in the build tree):
 
@@ -150,7 +156,8 @@ The SoC currently implements (in the build tree):
 | Wishbone Bus                  | Yes    | 32 bit Wishbone bus.                                         |
 | (SB) BRAM                     | Yes    | Implement a configurable block of BRAM as the boot loader and stack. |
 | Instruction Bus BRAM          | Yes    | Enable a separate bus (or Dual-Port) to the boot code implemented in BRAM. This is generally a dual-port BRAM shared with the Sysbus BRAM but can be independent. |
-| (SB) RAM                      | Yes    | Implement a block of BRAM as RAM, seperate from the BRAM used for the boot loader/stack. |
+| (SB) RAM                      | Yes    | Implement a block of BRAM as RAM, separate from the BRAM used for the boot loader/stack. |
+| (SB) SDRAM                    | Yes    | Implement an SDRAM controller on the system bus.        |
 | (WB) SDRAM                    | Yes    | Implement an SDRAM controller over the Wishbone bus.    |
 | (WB) RAM                      | Yes    | Implement a block of BRAM as RAM over the Wishbone bus.      |
 | (WB) I2C                      | Yes    | Implements an I2C Controller over the Wishbone bus.     |
@@ -162,15 +169,16 @@ The SoC currently implements (in the build tree):
 | (SB) PS2                      | Yes    | A PS2 Keyboard and Mouse controller.                    |
 | (SB) SPI                      | Yes    | A configurable number of Serial Peripheral Interface controllers. |
 | (SB) SD                       | Yes    | A configurable number of hardware based SPI SD controllers. |
+| (SB) IOCTL                    | Yes    | An IOCTL bus controller for MiSTer HPS-to-FPGA communication (download/upload of data between the ARM HPS and the FPGA fabric). |
 | (SB) SOCCFG                   | Yes    | A set of registers to indicate configuration of the ZPU and SoC to the controlling program. |
 
 Within the SoC configuration, items such as starting Stack Address, Reset Vector, IO Start/End (SB) and (WB) can be specified. With the addition of the wishbone bus, it is very easy to add further opencore IP devices, for the system bus some work may be needed as the opencore IP devices use differing signals.
 
-### SDRAM
+### <font style="color: yellow;" size="5">SDRAM</font>
 
+The SoC supports SDRAM via two independent paths: a system bus (SB) controller (`SOC_IMPL_SDRAM`) and a Wishbone bus (WB) controller (`SOC_IMPL_WB_SDRAM`). Both are disabled by default and can be enabled independently. The SDRAM timing parameters (tRCD, tRP, tRFC, tREF) and geometry (rows, columns, banks, data width) are all configurable in `zpu_soc_pkg.vhd`. The WB SDRAM controller is a cached variant supporting burst access and is the recommended choice when both buses are active and external RAM bandwidth is critical.
 
-
-## Software
+## <font style="color: yellow;" size="6">Software</font>
 
 
 The software provided includes:
@@ -183,24 +191,24 @@ The software provided includes:
 21/04/2020: Software for the ZPU has now been merged with the tranZPUter and is kept and maintained in the [zSoft](/zsoft) repository.
 
 
-## Configuration
+## <font style="color: yellow;" size="6">Configuration</font>
 
-This section shows how to configure the ZPU and the SoC, either to use the ZPU seperately or as part of the included SoC.
+This section shows how to configure the ZPU and the SoC, either to use the ZPU separately or as part of the included SoC.
 
 
-### Configure the CPU
+### <font style="color: yellow;" size="5">Configure the CPU</font>
 
 <br>The CPU is configurable using the configuration file 'cpu/zpu_pkg.vhd'. It generally specifies the size of the address bus and what hardware features should be enabled. The following table outlines the configurable options.
 
 &nbsp;&nbsp;| Configuration Variable   | Model   | Values       | Description                                                                |
 | ------------------------ | -----   | ------------ | ---------------------------------------------------------------------------|
-| EVO_USE_INSN_BUS         | Evo     | true/false   | Use a seperate instruction bus to connect to the BRAM memory. All other Memory and I/O operations will go over the normal bus. This option is primarily used with Dual Port BRAM, one side connected to the Instruction Bus the other side to the standard bus and will give a significant performance boost when the executed code is in this memory. |
+| EVO_USE_INSN_BUS         | Evo     | true/false   | Use a separate instruction bus to connect to the BRAM memory. All other Memory and I/O operations will go over the normal bus. This option is primarily used with Dual Port BRAM, one side connected to the Instruction Bus the other side to the standard bus and will give a significant performance boost when the executed code is in this memory. |
 | EVO_USE_HW_BYTE_WRITE    | Evo     | true/false   | This option implements hardware writing of bytes, reads are always 32bit and aligned. |
 | EVO_USE_HW_WORD_WRITE    | Evo     | true/false   | This option implements hardware writing of 16bit words,  reads are always 32bit and aligned. |
 | EVO_USE_WB_BUS           | Evo     | true/false   | Implement the wishbone interface in addition to the system bus.  |
 | DEBUG_CPU                | All     | true/false   | Enable CPU debugging output. This generally consists of core data being serialised and output via the UART1 TX. There are pre-defined blocks of debug data (debug level) for output but it is easy to add in another if your targetting a specific CPU area/instruction. |
 | DEBUG_LEVEL              | All     | 0 to 5       | Level of debugging output. 0 = Basic, such as Breakpoint, 1 =+ Executing Instructions, 2 =+ L1 Cache contents, 3 =+ L2 Cache contents, 4 =+ Memory contents, 5=+ Everything else. |
-| DEBUG_MAX_TX_FIFO_BITS   | All     | 2 .. ~16     | Size of UART TX Fifo for debug output. One point to note, if too much data is output and the output Baud rate too low, the CPU will wait so cache size is irrelevant. Cache is only useful if outputting small amounts of data (ie. a targetted instruction) where the cache never becomes full and the CPU doesnt need to wait. |
+| DEBUG_MAX_TX_FIFO_BITS   | All     | 2 .. ~16     | Size of UART TX Fifo for debug output. One point to note, if too much data is output and the output Baud rate too low, the CPU will wait so cache size is irrelevant. Cache is only useful if outputting small amounts of data (ie. a targeted instruction) where the cache never becomes full and the CPU doesn't need to wait. |
 | DEBUG_MAX_FIFO_BITS      | All     | 2 .. ~16     | Size of debug output data records fifo. Each request to output data via the serialiser is made via debug records which consume memory, the more records available the less chance of the CPU stalling. |
 | DEBUG_TX_BAUD_RATE       | All     | Any Baud integer value | This option sets the output Baud rate of the debug serializer transmitter, ie. 115200 |
 | maxAddrBit               | All     | \<16..31n> + WB_ACTIVE | This option sets the width of the address bus. WB_ACTIVE adds 1 to the width of the bus if the WishBone bus is enabled as the wishbone bus operates in the top half of the addressable memory area. |
@@ -241,7 +249,7 @@ This section shows how to configure the ZPU and the SoC, either to use the ZPU s
 
 <br>
 
-### Configure the SoC
+### <font style="color: yellow;" size="5">Configure the SoC</font>
 
 <br>The System on a Chip is configurable using the configuration file 'zpu_soc_pkg.vhd'. The following table outlines the options which can be configured to adapt the SoC to a specific application.
 
@@ -257,19 +265,19 @@ This section shows how to configure the ZPU and the SoC, either to use the ZPU s
 | ZPU_EVO_MINIMAL          | \<0 or 1\>        | Select the Minimalist EVOLUTION CPU, which is the EVO CPU with all configurable options disabled using less fabric. |
 
 <br>
-  : The following options set the frequencies for the various boards. Normally these dont need changing, add additional constants if using a different board to those defined and add in your <board>_Topleavel.vhd file. NB. This option only changes logic dependent on frequency, it doesnt change the PLL which needs to be done seperately in HDL.
+  : The following options set the frequencies for the various boards. Normally these don't need changing, add additional constants if using a different board to those defined and add in your <board>_Topleavel.vhd file. NB. This option only changes logic dependent on frequency, it doesn't change the PLL which needs to be done separately in HDL.
 
 &nbsp;&nbsp;| Configuration Variable   | Values            | Description                                                                 |
 | ------------------------ | ------------      | --------------------------------------------------------------------------- |
-| SYSCLK_E115_FREQ         | \<Freq in Hz\>    | Set the frequency for the E115 FPGA Board. |
-| SYSCLK_QMV_FREQ          | \<Freq in Hz\>    | Set the frequency for the QMTECH Cyclone V FPGA Board. |
-| SYSCLK_DE0_FREQ          | \<Freq in Hz\>    | Set the frequency for the DE0-Nano FPGA Board. |
-| SYSCLK_DE10_FREQ         | \<Freq in Hz\>    | Set the frequency for the DE10-Nano FPGA Board. |
-| SYSCLK_CYC1000_FREQ      | \<Freq in Hz\>    | Set the frequency for the Trenz CYC1000 FPGA Board. |
-| SYSTEM_FREQUENCY         | 100000000         | Default system clock frequency if not overriden by the above values in the top level. |
+| SYSCLK_E115_FREQ         | 75000000 (default) | Set the frequency for the E115 FPGA Board. |
+| SYSCLK_QMV_FREQ          | 75000000 (default) | Set the frequency for the QMTECH Cyclone V FPGA Board. |
+| SYSCLK_DE0_FREQ          | 100000000 (default) | Set the frequency for the DE0-Nano FPGA Board. |
+| SYSCLK_DE10_FREQ         | 100000000 (default) | Set the frequency for the DE10-Nano FPGA Board. |
+| SYSCLK_CYC1000_FREQ      | 100000000 (default) | Set the frequency for the Trenz CYC1000 FPGA Board. |
+| SYSTEM_FREQUENCY         | 75000000          | Default system clock frequency if not overridden by the above values in the top level. |
 
 <br>
-  : Set the ID's for the various ZPU models. The format is 2 bytes, MSB=\<Model\>, LSB=\<Revision\>. This is only necessary if your making a different version and you need to detect in your software.
+  : Set the ID's for the various ZPU models. The format is 2 bytes, MSB=\<Model\>, LSB=\<Revision\>. This is only necessary if you're making a different version and you need to detect in your software.
 
 &nbsp;&nbsp;| Configuration Variable   | Values            | Description                                                                 |
 | ------------------------ | ------------      | --------------------------------------------------------------------------- |
@@ -329,7 +337,7 @@ This section shows how to configure the ZPU and the SoC, either to use the ZPU s
 
 &nbsp;&nbsp;| Configuration Variable   | Values            | Description                                                                 |
 | ------------------------ | ------------      | --------------------------------------------------------------------------- |
-| SOC_IMPL_RAM             | true/false        | Implement RAM using BRAM, typically for Application programs seperate to BIOS. |
+| SOC_IMPL_RAM             | true/false        | Implement RAM using BRAM, typically for Application programs separate to BIOS. |
 | SOC_MAX_ADDR_RAM_BIT     | \<n\>, ie.14      | Max address bit of the System RAM. |
 | SOC_ADDR_RAM_START       | \<n\>, ie.32768   | Start address of RAM. |
 
@@ -366,7 +374,7 @@ This section shows how to configure the ZPU and the SoC, either to use the ZPU s
 | SOC_RESET_ADDR_CPU       | \<n\>             | Initial address to start execution from after reset. This is normally set as the start of BRAM, ie. SOC_ADDR_BRAM_START |
 | SOC_START_ADDR_MEM       | \<n\>             | Start location of program memory (BRAM/ROM/RAM). This is normally set as the start of BRAM, ie. SOC_ADDR_BRAM_START |
 | SOC_STACK_ADDR           | \<n\>             | Stack start address (BRAM/RAM). This is normally set as the top of the BRAM less 2 words, ie. SOC_ADDR_BRAM_END - 8 |
-| SOC_ADDR_IO_START        | \<n\>             | Start address of the Evo system bus IO region. This is normally via the forumula: '2^(maxAddrBit-WB_ACTIVE)) - (2^maxIOBit)' which sets the address space based on the address bus width and wether the wishbone bus is implemented. ||
+| SOC_ADDR_IO_START        | \<n\>             | Start address of the Evo system bus IO region. This is normally via the forumula: '2^(maxAddrBit-WB_ACTIVE)) - (2^maxIOBit)' which sets the address space based on the address bus width and whether the wishbone bus is implemented. ||
 | SOC_ADDR_IO_END          | \<n\>             | End address of the Evo system bus IO region. This is normally via the formula: (2^(maxAddrBit-WB_ACTIVE)) - 1 |
 | SOC_WB_IO_START          | \<n\>, ie. 32505856 | Start address of the Wishbone bus IO range. |
 | SOC_WB_IO_END            | \<n\>, ie. 33554431 | End address of the Wishbone bus IO range. |
@@ -411,13 +419,13 @@ This section shows how to configure the ZPU and the SoC, either to use the ZPU s
 
 <br>
 
-## Build
+## <font style="color: yellow;" size="6">Build</font>
 
-This section shows how to make a basic build and assumes the target development board is the [QMTECH Cyclone V board](https://github.com/ChinaQMTECH/QM_CYCLONE_V). There are many configuration options but these will be covered seperately.
+This section shows how to make a basic build and assumes the target development board is the [QMTECH Cyclone V board](https://github.com/ChinaQMTECH/QM_CYCLONE_V). There are many configuration options but these will be covered separately.
 
 <br>
 
-### Software build
+### <font style="color: yellow;" size="5">Software build</font>
 
 Jenkins can be used to automate the build but for simple get up and go compilation use the build.sh and hierarchical Makefile system following the basic instructions here.
 
@@ -426,9 +434,9 @@ Jenkins can be used to automate the build but for simple get up and go compilati
 ```shell
     export PATH=$PATH:/opt/zpu/bin
 ```
-3. Clone the [ZPU Evo](https://github.com/pdsmart/zpu) repository
-4. Edit the \<zpu evo dir>/software/zputa/zputa.h file and select which functions you want building into the zputa core image (by default, all functions are built as applets but these will be ignored if they are built into the zputa core image). You select a function by setting the BUILTIN_<utility>  to '1', set to '0' if you dont want it built in.
-5. Decide which memory map you want and wether ZPUTA will be an application or bootloader (for your own applications, it is they same kind of choice), see build.sh in the table below for options. Once decided, issue the build command.
+3. Clone the [ZPU Evo](https://git.eaw.app/eaw/zpu) repository
+4. Edit the \<zpu evo dir>/software/zputa/zputa.h file and select which functions you want building into the zputa core image (by default, all functions are built as applets but these will be ignored if they are built into the zputa core image). You select a function by setting the BUILTIN_<utility>  to '1', set to '0' if you don't want it built in.
+5. Decide which memory map you want and whether ZPUTA will be an application or bootloader (for your own applications, it is they same kind of choice), see build.sh in the table below for options. Once decided, issue the build command.
 ```shell
     cd <zpu evo dir>/software
     # For this build we have chosen a Tiny IOCP Bootloader, building ZPUTA as an
@@ -448,7 +456,7 @@ Jenkins can be used to automate the build but for simple get up and go compilati
 
 <br>
 
-### RTL Bit Stream build
+### <font style="color: yellow;" size="5">RTL Bit Stream build</font>
 
 To build the FPGA bit stream (conversion of HDL into a configuration map for the FPGA), there are two methods:
 
@@ -467,7 +475,7 @@ To build the FPGA bit stream (conversion of HDL into a configuration map for the
 
 <br>
 
-### ZPU Small Build
+### <font style="color: yellow;" size="5">ZPU Small Build</font>
 
 The ZPU Small CPU can be built by changing the configuration as follows:
 
@@ -484,13 +492,13 @@ Edit: zpu_soc_pkg.vhd
     constant ZPU_EVO                  :     integer    := 0;                                                -- Use the EVOLUTION CPU.
     constant ZPU_EVO_MINIMAL          :     integer    := 0;                                                -- Use the Minimalist EVOLUTION CPU.
 
-2. Disable WishBone devices as the ZPU Small doesnt support the wishbone interface:
+2. Disable WishBone devices as the ZPU Small doesn't support the wishbone interface:
     constant SOC_IMPL_WB_I2C          :     boolean    := false;                                            -- Implement I2C over wishbone interface.
     constant SOC_IMPL_WB_SDRAM        :     boolean    := false;                                            -- Implement SDRAM over wishbone interface.
 
-3. Disable any other devices you dont need, such as PS2 by setting the flag to false.
+3. Disable any other devices you don't need, such as PS2 by setting the flag to false.
 
-4. If your using a frequency other than 100MHz as your main clock, enter it in the table
+4. If you're using a frequency other than 100MHz as your main clock, enter it in the table
    below against your board. If you are using a different board, add a constant with
    suitable name and use this in your TopLevel (ie. as per E115_zpu_Toplevel.vhd).
    NB. If using your own board it is still imperative that you setup a PLL correctly to
@@ -499,8 +507,8 @@ Edit: zpu_soc_pkg.vhd
 
     -- Frequencies for the various boards.
     --
-    constant SYSCLK_E115_FREQ         :     integer    := 100000000;                                        -- E115 FPGA Board
-    constant SYSCLK_QMV_FREQ          :     integer    := 100000000;                                        -- QMTECH Cyclone V FPGA Board
+    constant SYSCLK_E115_FREQ         :     integer    := 75000000;                                         -- E115 FPGA Board
+    constant SYSCLK_QMV_FREQ          :     integer    := 75000000;                                         -- QMTECH Cyclone V FPGA Board
     constant SYSCLK_DE0_FREQ          :     integer    := 100000000;                                        -- DE0-Nano FPGA Board
     constant SYSCLK_DE10_FREQ         :     integer    := 100000000;                                        -- DE10-Nano FPGA Board
     constant SYSCLK_CYC1000_FREQ      :     integer    := 100000000;                                        -- Trenz CYC1000 FPGA Board
@@ -520,11 +528,16 @@ Edit: cpu/zpu_pkg.vhd
     constant DEBUG_TX_BAUD_RATE       :     integer          := 115200; --230400;                    -- Baud rate for the debug transmitter
 ````
 
-Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. You cannot use the Makefile build as it will entail Makefile changes so just use the Quartus Prime GUI at this time.<br><br>The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
+Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. Alternatively, use the Makefile build system, for example to build the Small CPU for the QMV board:
+```shell
+    cd <zpu evo dir>/build
+    make QMV_SMALL
+```
+The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
 
 <br>
 
-### ZPU Medium Build
+### <font style="color: yellow;" size="5">ZPU Medium Build</font>
 
 The ZPU Medium CPU can be built by changing the configuration as follows:
 
@@ -541,13 +554,13 @@ Edit: zpu_soc_pkg.vhd
     constant ZPU_EVO                  :     integer    := 0;                                                -- Use the EVOLUTION CPU.
     constant ZPU_EVO_MINIMAL          :     integer    := 0;                                                -- Use the Minimalist EVOLUTION CPU.
 
-2. Disable WishBone devices as the ZPU Medium doesnt support the wishbone interface:
+2. Disable WishBone devices as the ZPU Medium doesn't support the wishbone interface:
     constant SOC_IMPL_WB_I2C          :     boolean    := false;                                            -- Implement I2C over wishbone interface.
     constant SOC_IMPL_WB_SDRAM        :     boolean    := false;                                            -- Implement SDRAM over wishbone interface.
 
-3. Disable any other devices you dont need, such as PS2 by setting the flag to false.
+3. Disable any other devices you don't need, such as PS2 by setting the flag to false.
 
-4. If your using a frequency other than 100MHz as your main clock, enter it in the table
+4. If you're using a frequency other than 100MHz as your main clock, enter it in the table
    below against your board. If you are using a different board, add a constant with
    suitable name and use this in your TopLevel (ie. as per E115_zpu_Toplevel.vhd).
    NB. If using your own board it is still imperative that you setup a PLL correctly to
@@ -556,8 +569,8 @@ Edit: zpu_soc_pkg.vhd
 
     -- Frequencies for the various boards.
     --
-    constant SYSCLK_E115_FREQ         :     integer    := 100000000;                                        -- E115 FPGA Board
-    constant SYSCLK_QMV_FREQ          :     integer    := 100000000;                                        -- QMTECH Cyclone V FPGA Board
+    constant SYSCLK_E115_FREQ         :     integer    := 75000000;                                         -- E115 FPGA Board
+    constant SYSCLK_QMV_FREQ          :     integer    := 75000000;                                         -- QMTECH Cyclone V FPGA Board
     constant SYSCLK_DE0_FREQ          :     integer    := 100000000;                                        -- DE0-Nano FPGA Board
     constant SYSCLK_DE10_FREQ         :     integer    := 100000000;                                        -- DE10-Nano FPGA Board
     constant SYSCLK_CYC1000_FREQ      :     integer    := 100000000;                                        -- Trenz CYC1000 FPGA Board
@@ -577,11 +590,16 @@ Edit: cpu/zpu_pkg.vhd
     constant DEBUG_TX_BAUD_RATE       :     integer          := 115200; --230400;                    -- Baud rate for the debug transmitter
 ````
 
-Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. You cannot use the Makefile build as it will entail Makefile changes so just use the Quartus Prime GUI at this time.<br><br>The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
+Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. Alternatively, use the Makefile build system, for example to build the Medium CPU for the QMV board:
+```shell
+    cd <zpu evo dir>/build
+    make QMV_MEDIUM
+```
+The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
 
 <br>
 
-### ZPU Flex Build
+### <font style="color: yellow;" size="5">ZPU Flex Build</font>
 
 The ZPU Flex CPU can be built by changing the configuration as follows:
 
@@ -598,13 +616,13 @@ Edit: zpu_soc_pkg.vhd
     constant ZPU_EVO                  :     integer    := 0;                                                -- Use the EVOLUTION CPU.
     constant ZPU_EVO_MINIMAL          :     integer    := 0;                                                -- Use the Minimalist EVOLUTION CPU.
 
-2. Disable WishBone devices as the ZPU Flex doesnt support the wishbone interface:
+2. Disable WishBone devices as the ZPU Flex doesn't support the wishbone interface:
     constant SOC_IMPL_WB_I2C          :     boolean    := false;                                            -- Implement I2C over wishbone interface.
     constant SOC_IMPL_WB_SDRAM        :     boolean    := false;                                            -- Implement SDRAM over wishbone interface.
 
-3. Disable any other devices you dont need, such as PS2 by setting the flag to false.
+3. Disable any other devices you don't need, such as PS2 by setting the flag to false.
 
-4. If your using a frequency other than 100MHz as your main clock, enter it in the table
+4. If you're using a frequency other than 100MHz as your main clock, enter it in the table
    below against your board. If you are using a different board, add a constant with
    suitable name and use this in your TopLevel (ie. as per E115_zpu_Toplevel.vhd).
    NB. If using your own board it is still imperative that you setup a PLL correctly to
@@ -613,8 +631,8 @@ Edit: zpu_soc_pkg.vhd
 
     -- Frequencies for the various boards.
     --
-    constant SYSCLK_E115_FREQ         :     integer    := 100000000;                                        -- E115 FPGA Board
-    constant SYSCLK_QMV_FREQ          :     integer    := 100000000;                                        -- QMTECH Cyclone V FPGA Board
+    constant SYSCLK_E115_FREQ         :     integer    := 75000000;                                         -- E115 FPGA Board
+    constant SYSCLK_QMV_FREQ          :     integer    := 75000000;                                         -- QMTECH Cyclone V FPGA Board
     constant SYSCLK_DE0_FREQ          :     integer    := 100000000;                                        -- DE0-Nano FPGA Board
     constant SYSCLK_DE10_FREQ         :     integer    := 100000000;                                        -- DE10-Nano FPGA Board
     constant SYSCLK_CYC1000_FREQ      :     integer    := 100000000;                                        -- Trenz CYC1000 FPGA Board
@@ -634,11 +652,16 @@ Edit: cpu/zpu_pkg.vhd
     constant DEBUG_TX_BAUD_RATE       :     integer          := 115200; --230400;                    -- Baud rate for the debug transmitter
 ````
 
-Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. You cannot use the Makefile build as it will entail Makefile changes so just use the Quartus Prime GUI at this time.<br><br>The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
+Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. Alternatively, use the Makefile build system, for example to build the Flex CPU for the QMV board:
+```shell
+    cd <zpu evo dir>/build
+    make QMV_FLEX
+```
+The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
 
 <br>
 
-### ZPU Evo Build
+### <font style="color: yellow;" size="5">ZPU Evo Build</font>
 
 The ZPU Evo has 2 pre-defined versions, the same CPU using different settings. These are the EVO and 'EVO MINIMAL'. The latter implements most of its instructions in micro-code like the ZPU Small.
 Assuming we are building the EVO without the WishBone interface, change the configuration as follows:
@@ -656,13 +679,13 @@ Edit: zpu_soc_pkg.vhd
     constant ZPU_EVO                  :     integer    := 1;                                                -- Use the EVOLUTION CPU.
     constant ZPU_EVO_MINIMAL          :     integer    := 0;                                                -- Use the Minimalist EVOLUTION CPU.
 
-2. Disable WishBone devices as we arent using the wishbone interface:
+2. Disable WishBone devices as we aren't using the wishbone interface:
     constant SOC_IMPL_WB_I2C          :     boolean    := false;                                            -- Implement I2C over wishbone interface.
     constant SOC_IMPL_WB_SDRAM        :     boolean    := false;                                            -- Implement SDRAM over wishbone interface.
 
-3. Disable any other devices you dont need, such as PS2 by setting the flag to false.
+3. Disable any other devices you don't need, such as PS2 by setting the flag to false.
 
-4. If your using a frequency other than 100MHz as your main clock, enter it in the table
+4. If you're using a frequency other than 100MHz as your main clock, enter it in the table
    below against your board. If you are using a different board, add a constant with
    suitable name and use this in your TopLevel (ie. as per E115_zpu_Toplevel.vhd).
    NB. If using your own board it is still imperative that you setup a PLL correctly to
@@ -671,8 +694,8 @@ Edit: zpu_soc_pkg.vhd
 
     -- Frequencies for the various boards.
     --
-    constant SYSCLK_E115_FREQ         :     integer    := 100000000;                                        -- E115 FPGA Board
-    constant SYSCLK_QMV_FREQ          :     integer    := 100000000;                                        -- QMTECH Cyclone V FPGA Board
+    constant SYSCLK_E115_FREQ         :     integer    := 75000000;                                         -- E115 FPGA Board
+    constant SYSCLK_QMV_FREQ          :     integer    := 75000000;                                         -- QMTECH Cyclone V FPGA Board
     constant SYSCLK_DE0_FREQ          :     integer    := 100000000;                                        -- DE0-Nano FPGA Board
     constant SYSCLK_DE10_FREQ         :     integer    := 100000000;                                        -- DE10-Nano FPGA Board
     constant SYSCLK_CYC1000_FREQ      :     integer    := 100000000;                                        -- Trenz CYC1000 FPGA Board
@@ -692,12 +715,17 @@ Edit: cpu/zpu_pkg.vhd
     constant DEBUG_TX_BAUD_RATE       :     integer          := 115200; --230400;                    -- Baud rate for the debug transmitter
 ````
 
-Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. You cannot use the Makefile build as it will entail Makefile changes so just use the Quartus Prime GUI at this time.<br><br>The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
+Using Quartus Prime following the 'RTL Bit Stream build' above, build the RTL in the usual manner with this new configuration. Alternatively, use the Makefile build system, for example to build the Evo CPU for the QMV board:
+```shell
+    cd <zpu evo dir>/build
+    make QMV_EVO
+```
+The software is the same and unless you have less memory, no changes need to be made to the software build.<br>
 
 <br>
 
 
-### Notes on setting up a new development board 
+### <font style="color: yellow;" size="5">Notes on setting up a new development board</font>
 
 If you are using your own FPGA board (ie. not one in the list I've tested and created Quartus configuration files for), please ensure you create these necessary files:
 ````
@@ -895,9 +923,9 @@ In the build/NEW_zpu_Toplevel.vhd:
 
 
 
-### Connecting the Development board
+### <font style="color: yellow;" size="5">Connecting the Development board</font>
 
-1. In order to run the ZPU Evo iand it's software in basic form on the QMTECH board you need 2 USB to Serial (ie. [USB to Serial](https://www.amazon.co.uk/Laqiya-FT232RL-Converter-Adapter-Breakout/dp/B07H6XMC2X)) adapters and you wire them up according to the pinout as is defined in the \<zpu evo dir>/build/QMV_zpu.qsf file. Ensure the adapters are set to 3.3V. See Images section for colour coded wiring.
+1. In order to run the ZPU Evo and its software in basic form on the QMTECH board you need 2 USB to Serial (ie. [USB to Serial](https://www.amazon.co.uk/Laqiya-FT232RL-Converter-Adapter-Breakout/dp/B07H6XMC2X)) adapters and you wire them up according to the pinout as is defined in the \<zpu evo dir>/build/QMV_zpu.qsf file. Ensure the adapters are set to 3.3V. See Images section for colour coded wiring.
 ```shell
 ##============================================================
 # UART
@@ -925,11 +953,11 @@ set_location_assignment PIN_Y20  -to SDCARD_CS[0]
 
 <br>
 
-## Repository Structure
+## <font style="color: yellow;" size="6">Repository Structure</font>
 
 The GIT Repository is organised as per the build environment shown in the tables below.
 
-### RTL
+### <font style="color: yellow;" size="5">RTL</font>
 
 | Folder           | RTL File             | Description                                                  |
 | ---------------- | -------------------- | ------------------------------------------------------------ |
@@ -953,41 +981,28 @@ The GIT Repository is organised as per the build environment shown in the tables
 | devices/WishBone | I2C                  | I2C Controller                                               |
 |                  | SRAM                 | Encapsulated Byte Addressable BRAM                           |
 |                  | SDRAM                | Byte Addressable 32Bit SDRAM Controller                      |
-| build            | CYC1000              | Quartus definition files and Top Level VHDL for the Trenz Electronic CYC1000 Cyclone 10LP development board. |
-|                  | E115                 | Quartus definition files and Top Level VHDL for the Cyclone IV EP4CE115 DDR2 64BIT development board. |
-|                  | QMV                  | Quartus definition files and Top Level VHDL for the QMTech Cyclone V development board. |
-|                  | DE10                 | Quartus definition files and Top Level VHDL for the Altera DE10 development board as used in the MiSTer project. |
-|                  | DE0                  | Quartus definition files and Top Level VHDL for the Altera DE0 development board. |
+| build            | CYC1000              | Quartus definition files and Top Level VHDL for the Trenz Electronic CYC1000 (Cyclone 10LP 10CL025YU256C8G) development board. |
+|                  | E115                 | Quartus definition files and Top Level VHDL for the Cyclone IV E (EP4CE115F23I7) DDR2 64BIT development board. |
+|                  | QMV                  | Quartus definition files and Top Level VHDL for the QMTech Cyclone V (5CEFA2F23C8) development board. |
+|                  | DE10                 | Quartus definition files and Top Level VHDL for the Terasic DE10-Nano (Cyclone V 5CSEBA6U23I7) development board as used in the MiSTer project. |
+|                  | DE0                  | Quartus definition files and Top Level VHDL for the Terasic DE0-Nano (Cyclone V 5CSEMA4U23C6) development board. |
+|                  | ReVerSE-U16          | Top Level VHDL for the ReVerSE-U16 development board.    |
 |                  | Clock_*              | Refactored Altera PLL definitions for various development board source clocks. These need to be made more generic for eventual inclusion of Xilinx fabric. |
 
 
 <br>
 
-### Software
 
-| Folder  | Src File | Description                                                  |
-| ------- | -------- | ------------------------------------------------------------ |
-| apps    |          | The ZPUTA application can either have a feature embedded or as a separate standalone disk based applet in addition to extended applets. The purpose is to allow control of the ZPUTA application size according to available BRAM and SD card availability.<br/>All applets for ZPUTA are stored in this folder. |
-| build   |          | Build tree output suitable for direct copy to an SD card.<br/> The initial bootloader and/or application as selected are compiled directly into a VHDL file for preloading in BRAM in the devices/sysbus/BRAM folder. |
-| common  |          | Common C modules such as Elm Chan's excellent Fat FileSystem. |
-| include |          | C Include header files.                                      |
-| iocp    |          | A small bootloader/monitor application for initialization of the ZPU. Depending upon configuration this program can either boot an application from SD card or via the Serial Line and also provide basic tools such as memory examination. |
-| startup |          | Assembler and Linker files for generating ZPU applications. These files are critical for defining how GCC creates and links binary images as well as providing the micro-code for ZPU instructions not implemented in hardware. |
-| utils   |          | Some small tools for converting binary images into VHDL initialization data. |
-| zputa   |          | The ZPU Test Application. This is an application for testing the ZPU and the SoC components. It can either be built as a single image for pre-loading into a BRAM via VHDL or as a standalone application loaded by the IOCP bootloader from an SD card. The services it provides can either be embedded or available on the SD card as applets depending on memory restrictions. |
-|         | build.sh | Unix shell script to build IOCP, ZPUTA and Apps for a given design.<br/><br>NAME<br> &nbsp;&nbsp;&nbsp;&nbsp;build.sh&nbsp;-&nbsp;&nbsp;Shell&nbsp;script&nbsp;to&nbsp;build&nbsp;a&nbsp;ZPU&nbsp;program&nbsp;or&nbsp;OS.<br> <br> SYNOPSIS<br> &nbsp;&nbsp;&nbsp;&nbsp;build.sh&nbsp;[-dIOoMBsxAh]<br> <br> DESCRIPTION<br> <br> OPTIONS<br> &nbsp;&nbsp;&nbsp;&nbsp;-I&nbsp;<iocp&nbsp;ver>&nbsp;=&nbsp;0&nbsp;-&nbsp;Full,&nbsp;1&nbsp;-&nbsp;Medium,&nbsp;2&nbsp;-&nbsp;Minimum,&nbsp;3&nbsp;-&nbsp;Tiny&nbsp;(bootstrap&nbsp;only)<br> &nbsp;&nbsp;&nbsp;&nbsp;-O&nbsp;<os>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;zputa,&nbsp;zos<br> &nbsp;&nbsp;&nbsp;&nbsp;-o&nbsp;<os&nbsp;ver>&nbsp;&nbsp;&nbsp;=&nbsp;0&nbsp;-&nbsp;Standalone,&nbsp;1&nbsp;-&nbsp;As&nbsp;app&nbsp;with&nbsp;IOCP&nbsp;Bootloader,<br> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;2&nbsp;-&nbsp;As&nbsp;app&nbsp;with&nbsp;tiny&nbsp;IOCP&nbsp;Bootloader,&nbsp;3&nbsp;-&nbsp;As&nbsp;app&nbsp;in&nbsp;RAM&nbsp;<br> &nbsp;&nbsp;&nbsp;&nbsp;-M&nbsp;<size>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;Max&nbsp;size&nbsp;of&nbsp;the&nbsp;boot&nbsp;ROM/BRAM&nbsp;(needed&nbsp;for&nbsp;setting&nbsp;Stack).<br> &nbsp;&nbsp;&nbsp;&nbsp;-B&nbsp;<addr>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;Base&nbsp;address&nbsp;of&nbsp;<os>,&nbsp;default&nbsp;-o&nbsp;==&nbsp;0&nbsp;:&nbsp;0x00000&nbsp;else&nbsp;0x01000&nbsp;<br> &nbsp;&nbsp;&nbsp;&nbsp;-A&nbsp;<addr>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;App&nbsp;address&nbsp;of&nbsp;<os>,&nbsp;default&nbsp;0x0C000<br> &nbsp;&nbsp;&nbsp;&nbsp;-s&nbsp;<size>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;Maximum&nbsp;size&nbsp;of&nbsp;an&nbsp;app,&nbsp;defaults&nbsp;to&nbsp;(BRAM&nbsp;SIZE&nbsp;-&nbsp;App&nbsp;Start&nbsp;Address&nbsp;-&nbsp;Stack&nbsp;Size)&nbsp;<br> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;if&nbsp;the&nbsp;App&nbsp;Start&nbsp;is&nbsp;located&nbsp;within&nbsp;BRAM&nbsp;otherwise&nbsp;defaults&nbsp;to&nbsp;0x10000.<br> &nbsp;&nbsp;&nbsp;&nbsp;-d&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;Debug&nbsp;mode.<br> &nbsp;&nbsp;&nbsp;&nbsp;-x&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;Shell&nbsp;trace&nbsp;mode.<br> &nbsp;&nbsp;&nbsp;&nbsp;-h&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&nbsp;This&nbsp;help&nbsp;screen.<br> <br> EXAMPLES<br> &nbsp;&nbsp;&nbsp;&nbsp;build.sh&nbsp;-O&nbsp;zputa&nbsp;-B&nbsp;0x00000&nbsp;-A&nbsp;0x50000<br> <br> EXIT&nbsp;STATUS<br> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;0&nbsp;&nbsp;&nbsp;&nbsp;The&nbsp;command&nbsp;ran&nbsp;successfully<br> <br> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;>0&nbsp;&nbsp;&nbsp;&nbsp;An&nbsp;error&nbsp;ocurred. |
+## <font style="color: yellow;" size="6">Quartus Prime in Docker</font>
 
-<br>
-
-## Quartus Prime in Docker 
-
-Installing Quartus Prime can be tedious and time consuming, especially as the poorly documented linux installation can lead to a wrong mix or missing packages which results in a non-functioning installation. To ease the burden I have pieced together a Docker Image containing Ubuntu, the necessary packages and Quartus Prime 17.1.1.
+Installing Quartus Prime can be tedious and time consuming, especially as the poorly documented linux installation can lead to a wrong mix or missing packages which results in a non-functioning installation.
+To ease the burden I have pieced together a Docker Image containing Ubuntu, the necessary packages and Quartus Prime 13.0sp1, 13.1 and 17.1.1.
 
 1. Clone the repository:
 
     ````bash
     cd ~
-    git clone https://github.com/pdsmart/zpu.git
+    git clone https://git.eaw.app/eaw/zpu.git
     cd zpu/docker/QuartusPrime
     ````
 
@@ -1010,14 +1025,15 @@ Installing Quartus Prime can be tedious and time consuming, especially as the po
    Build the docker image:
 
     ````bash
-    docker build -f Dockerfile.17.1.1 -t quartus-ii-17.1.1 .
+    docker build -f Dockerfile.17.1.1 -t quartus-ii-17.1.1 --build-arg user_uid=`id -u`  --build-arg user_gid=`id -g` --build-arg user_name=`whoami` .
     ````
 
+    For Quartus Prime 13.0.1 and 13.1 replace 17.1.1 with the necessary version. Quartus Prime 13.0.1 supports the older Cyclone devices.
 
 2. Setup your X DISPLAY variable to point to your xserver:
 
     ````bash
-    export DISPLAY=<x server ip or hostname>:<screen number>
+    export DISPLAY=<x server ip or hostname>:<screen number or :<screen number>>
     # ie. export DISPLAY=192.168.1.1:0
     ````
 
@@ -1056,9 +1072,9 @@ Installing Quartus Prime can be tedious and time consuming, especially as the po
     ````
 <br>
 
-## Images
+## <font style="color: yellow;" size="6">Images</font>
 
-### Images of QMTECH Cyclone V wiring
+### <font style="color: yellow;" size="5">Images of QMTECH Cyclone V wiring</font>
 
 ![SD Card Wiring](../images/IMG_9837.jpg)
 ![UART 1 Wiring](../images/IMG_9838.jpg)
@@ -1068,9 +1084,9 @@ Installing Quartus Prime can be tedious and time consuming, especially as the po
 <br>Above are the wiring connections for the QMTECH Cyclone V board as used in the Build section, colour co-ordinated for reference.
 <br>
 
-### Images of ZPUTA on a ZPU EVO CPU
+### <font style="color: yellow;" size="5">Images of ZPUTA on a ZPU EVO CPU</font>
 
-#### ZPU Performance
+#### <font style="color: yellow;" size="4">ZPU Performance</font>
 ![ZPUTA Performance Test](../images/ScreenZPU1.png)
 Dhrystone and CoreMark performance tests of the ZPU Evo CPU. Depending on Fabric there are slight variations, these tests are on a Cyclone V CEFA chip, on a Cyclone IV CE I7 the results are 13.2DMIPS for Dhrystone and 22.2 for CoreMark.
 
@@ -1083,10 +1099,10 @@ Help screen for ZPUTA, help in this instance is an applet on the SD Card. A * be
 ![ZPUTA SD Directory](../images/ScreenZPU3.png)
 SD Directory listings of all the compiled applets.
 
-#### SDRAM Performance
+#### <font style="color: yellow;" size="4">SDRAM Performance</font>
 
 ![ZPUTA SDRAM Performance Sysbus No Cache](../images/ZPUSDRAMPerformance.png)
-SDRAM operating over the SYSBUS and with no cache. Not quite true memory performance as the ZPU makes several stack operations for a memory read/write, ie. IM <address>, IM <data>, STORE for a write which would entail upto 11 instruction reads (3 cycles on the Evo) and two stack writes.
+SDRAM operating over the SYSBUS and with no cache. Not quite true memory performance as the ZPU makes several stack operations for a memory read/write, ie. IM <address>, IM <data>, STORE for a write which would entail up to 11 instruction reads (3 cycles on the Evo) and two stack writes.
 
 ![ZPUTA SDRAM Performance Sysbus Cache](../images/ZPUSDRAMPerformanceCached.png)
 SDRAM operating over the SYSBUS with full page cache per bank for read and write-thru cache for write.
@@ -1098,7 +1114,7 @@ SDRAM operating over the WishBone Bus and with no cache.
 SDRAM operating over the WishBone Bus with full page cache per bank for read and write-thru cache for write.
 
 <br>
-## Links
+## <font style="color: yellow;" size="6">Links</font>
 
 | Recommended Site                                                                               |
 | ---------------------------------------------------------------------------------------------- |
@@ -1110,17 +1126,17 @@ SDRAM operating over the WishBone Bus with full page cache per bank for read and
 
 
 <br>
-## Credits
+## <font style="color: yellow;" size="6">Credits</font>
 
 Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. All 3rd party software, to my knowledge and research, is open source and freely useable, if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.
 
 
 <br>
-## Licenses
+## <font style="color: yellow;" size="6">Licenses</font>
 
 The original ZPU uses the Free BSD license and such the Evo is also released under FreeBSD. SoC components and other developments written by me are currently licensed using the GPL. 3rd party components maintain their original copyright notices.
 
-### The FreeBSD license
+### <font style="color: yellow;" size="5">The FreeBSD license</font>
  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
  
  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
@@ -1130,7 +1146,7 @@ The original ZPU uses the Free BSD license and such the Evo is also released und
  
  The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted as representing official policies, either expressed or implied, of the this project.
 
-### The Gnu Public License v3
+### <font style="color: yellow;" size="5">The Gnu Public License v3</font>
  The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
 
  The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.

VERSION

@@ -0,0 +1 @@
+1.10

build/CYC1000_zpu.qsf

@@ -1,41 +1,41 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Intel and sold by Intel or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-# Date created = 11:51:50  November 03, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		cyc1000_nios_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus Prime software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
+# Date created = 11:51:50  November 03, 2017
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		cyc1000_nios_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
 
 # Project-Wide Assignments
 # ========================
@@ -48,7 +48,7 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 # Analysis & Synthesis Assignments
 # ================================
 set_global_assignment -name FAMILY "Cyclone 10 LP"
-set_global_assignment -name TOP_LEVEL_ENTITY CYC1000_zpu
+set_global_assignment -name TOP_LEVEL_ENTITY CYC1000_zpu
 
 # Fitter Assignments
 # ==================
@@ -386,6 +386,7 @@ set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
+set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_STcache.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
@@ -398,6 +399,7 @@ set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
+set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_DualPort3264BootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
@@ -411,7 +413,7 @@ set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ct
 set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
 #set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
 #set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
+set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
 #set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
 set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
 

build/DE0_nano_zpu.qsf

@@ -1,19 +1,19 @@
-#============================================================
-# Build by Terasic System Builder
-#============================================================
-
+#============================================================
+# Build by Terasic System Builder
+#============================================================
+
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CSEMA4U23C6
-set_global_assignment -name TOP_LEVEL_ENTITY "DE0_nano_zpu"
+set_global_assignment -name TOP_LEVEL_ENTITY "DE0_nano_zpu"
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
 set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:58:03 DECEMBER 18,2014"
 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
-
-
-#============================================================
-# ADC
-#============================================================
+
+
+#============================================================
+# ADC
+#============================================================
 set_location_assignment PIN_U9 -to ADC_CONVST
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
 set_location_assignment PIN_V10 -to ADC_SCK
@@ -22,10 +22,10 @@ set_location_assignment PIN_AC4 -to ADC_SDI
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
 set_location_assignment PIN_AD4 -to ADC_SDO
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-#============================================================
-# ARDUINO
-#============================================================
+
+#============================================================
+# ARDUINO
+#============================================================
 set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
 set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
@@ -60,24 +60,24 @@ set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
 set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
-
-#============================================================
-# CLOCK
-#============================================================
-#set_location_assignment PIN_V11 -to FPGA_CLK1_50
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+
+#============================================================
+# CLOCK
+#============================================================
+#set_location_assignment PIN_V11 -to FPGA_CLK1_50
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
 set_location_assignment PIN_Y13 -to FPGA_CLK2_50
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
 set_location_assignment PIN_E11 -to FPGA_CLK3_50
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
-
-#set_location_assignment PIN_R8 -to CLOCK_50
+
+#set_location_assignment PIN_R8 -to CLOCK_50
 set_location_assignment PIN_V11 -to CLOCK_50
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# HPS
+
+#============================================================
+# HPS
+#============================================================
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
@@ -198,18 +198,18 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
-
-#============================================================
-# KEY
+
+#============================================================
+# KEY
+#============================================================
 set_location_assignment PIN_AH17 -to KEY[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
 set_location_assignment PIN_AH16 -to KEY[1]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-
-#============================================================
-# LED
+
+#============================================================
+# LED
+#============================================================
 set_location_assignment PIN_W15 -to LED[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
 set_location_assignment PIN_AA24 -to LED[1]
@@ -226,10 +226,10 @@ set_location_assignment PIN_Y16 -to LED[6]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
 set_location_assignment PIN_AA23 -to LED[7]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
-
-#============================================================
-# SW
+
+#============================================================
+# SW
+#============================================================
 set_location_assignment PIN_L10 -to SW[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
 set_location_assignment PIN_L9 -to SW[1]
@@ -238,10 +238,10 @@ set_location_assignment PIN_H6 -to SW[2]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
 set_location_assignment PIN_H5 -to SW[3]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-
-#============================================================
-# GPIO_0, GPIO connect to GPIO Default
+
+#============================================================
+# GPIO_0, GPIO connect to GPIO Default
+#============================================================
 set_location_assignment PIN_V12 -to GPIO_0[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
 set_location_assignment PIN_AF7 -to GPIO_0[1]
@@ -306,18 +306,18 @@ set_location_assignment PIN_AD11 -to GPIO_0[30]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
 set_location_assignment PIN_AF10 -to GPIO_0[31]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-#set_location_assignment PIN_AD12 -to GPIO_0[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
-#set_location_assignment PIN_AE11 -to GPIO_0[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
-#set_location_assignment PIN_AF11 -to GPIO_0[34]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
-#set_location_assignment PIN_AE12 -to GPIO_0[35]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
-
-#============================================================
-# GPIO_1, GPIO connect to GPIO Default
+#set_location_assignment PIN_AD12 -to GPIO_0[32]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
+#set_location_assignment PIN_AE11 -to GPIO_0[33]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
+#set_location_assignment PIN_AF11 -to GPIO_0[34]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
+#set_location_assignment PIN_AE12 -to GPIO_0[35]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
+
+#============================================================
+# GPIO_1, GPIO connect to GPIO Default
+#============================================================
 set_location_assignment PIN_Y15 -to GPIO_1[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
 set_location_assignment PIN_AG28 -to GPIO_1[1]
@@ -390,8 +390,8 @@ set_location_assignment PIN_AA18 -to GPIO_1[34]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
 set_location_assignment PIN_AC22 -to GPIO_1[35]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
-
+
+
 set_location_assignment PIN_AE12 -to UART_TX_0
 set_location_assignment PIN_AE11 -to UART_RX_0
 set_location_assignment PIN_AF11 -to UART_TX_1
@@ -402,13 +402,13 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# End of pin assignments by Terasic System Builder
-#============================================================
-
-
+
+#============================================================
+# End of pin assignments by Terasic System Builder
+#============================================================
+
+
+
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
@@ -423,9 +423,9 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
 set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
 set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
-set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
+
 set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
 set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
 
@@ -439,6 +439,7 @@ set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
+set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_STcache.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
@@ -451,6 +452,7 @@ set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
+set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_DualPort3264BootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
@@ -458,7 +460,7 @@ set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
 #set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
 #set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
 #set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
+set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
 #set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
 set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
 set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd

build/DE10_nano_zpu.qsf

@@ -1,10 +1,10 @@
-#============================================================
-# Build by Terasic System Builder
-#============================================================
-
+#============================================================
+# Build by Terasic System Builder
+#============================================================
+
 set_global_assignment -name DEVICE 5CSEBA6U23I7
 set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
+set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
 set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011"
@@ -16,15 +16,15 @@ set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO
 set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name GENERATE_RBF_FILE ON
-
-
+
+
 #============================================================
 # UART
 #============================================================
-#set_location_assignment PIN_AA13 -to UART_TX_0
-#set_location_assignment PIN_AA11 -to UART_RX_0
-#set_location_assignment PIN_Y11 -to UART_TX_1
-#set_location_assignment PIN_AA26 -to UART_RX_1
+#set_location_assignment PIN_AA13 -to UART_TX_0
+#set_location_assignment PIN_AA11 -to UART_RX_0
+#set_location_assignment PIN_Y11 -to UART_TX_1
+#set_location_assignment PIN_AA26 -to UART_RX_1
 set_location_assignment PIN_Y15 -to UART_TX_0
 set_location_assignment PIN_AA15 -to UART_RX_0
 set_location_assignment PIN_AG28 -to UART_TX_1
@@ -50,17 +50,17 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
-
-#============================================================
-# CLOCK
-#============================================================
-#set_location_assignment PIN_R8 -to CLOCK_50
+
+#============================================================
+# CLOCK
+#============================================================
+#set_location_assignment PIN_R8 -to CLOCK_50
 set_location_assignment PIN_V11 -to CLOCK_50
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# LED
-#============================================================
+
+#============================================================
+# LED
+#============================================================
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
@@ -77,18 +77,18 @@ set_location_assignment PIN_AF26 -to LED[4]
 set_location_assignment PIN_AE26 -to LED[5]
 set_location_assignment PIN_Y16 -to LED[6]
 set_location_assignment PIN_AA23 -to LED[7]
-
-#============================================================
-# KEY
-#============================================================
+
+#============================================================
+# KEY
+#============================================================
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
 set_location_assignment PIN_AH17 -to KEY[0]
 set_location_assignment PIN_AH16 -to KEY[1]
-
-#============================================================
-# SW
-#============================================================
+
+#============================================================
+# SW
+#============================================================
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
@@ -97,10 +97,10 @@ set_location_assignment PIN_Y24 -to SW[0]
 set_location_assignment PIN_W24 -to SW[1]
 set_location_assignment PIN_W21 -to SW[2]
 set_location_assignment PIN_W20 -to SW[3]
-
-#============================================================
-# SDIO
-#============================================================
+
+#============================================================
+# SDIO
+#============================================================
 #set_location_assignment PIN_AF25 -to SDIO_DAT[0]
 #set_location_assignment PIN_AF23 -to SDIO_DAT[1]
 #set_location_assignment PIN_AD26 -to SDIO_DAT[2]
@@ -112,9 +112,9 @@ set_location_assignment PIN_W20 -to SW[3]
 #set_location_assignment PIN_AF28 -to TCS
 #set_location_assignment PIN_AF27 -to TDI
 #set_location_assignment PIN_AH26 -to TCK
-
+
 #set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
-
+
 #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDO
 #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDI
 #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCK
@@ -123,9 +123,9 @@ set_location_assignment PIN_W20 -to SW[3]
 #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TCS
 #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TDI
 
-#============================================================
-# SDRAM
-#============================================================
+#============================================================
+# SDRAM
+#============================================================
 #set_location_assignment PIN_M7 -to SDRAM_BA[0]
 #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
 #set_location_assignment PIN_M6 -to SDRAM_BA[1]
@@ -204,236 +204,236 @@ set_location_assignment PIN_W20 -to SW[3]
 #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
 #set_location_assignment PIN_L4 -to SDRAM_ADDR[12]
 #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
-
-#============================================================
-# EPCS
-#============================================================
-#set_location_assignment PIN_H2 -to EPCS_DATA0
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
-#set_location_assignment PIN_H1 -to EPCS_DCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
-#set_location_assignment PIN_D2 -to EPCS_NCSO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
-#set_location_assignment PIN_C1 -to EPCS_ASDO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
-
-#============================================================
-# Accelerometer and EEPROM
-#============================================================
-#set_location_assignment PIN_F2 -to I2C_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
-#set_location_assignment PIN_F1 -to I2C_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
-#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
-#set_location_assignment PIN_M2 -to G_SENSOR_INT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
-
-#============================================================
-# ADC
-#============================================================
-#set_location_assignment PIN_A10 -to ADC_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
-#set_location_assignment PIN_B10 -to ADC_SADDR
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
-#set_location_assignment PIN_B14 -to ADC_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
-#set_location_assignment PIN_A9 -to ADC_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
-
-#============================================================
-# 2x13 GPIO Header
-#============================================================
-#set_location_assignment PIN_A14 -to GPIO_2[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
-#set_location_assignment PIN_B16 -to GPIO_2[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
-#set_location_assignment PIN_C14 -to GPIO_2[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
-#set_location_assignment PIN_C16 -to GPIO_2[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
-#set_location_assignment PIN_C15 -to GPIO_2[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
-#set_location_assignment PIN_D16 -to GPIO_2[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
-#set_location_assignment PIN_D15 -to GPIO_2[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
-#set_location_assignment PIN_D14 -to GPIO_2[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
-#set_location_assignment PIN_F15 -to GPIO_2[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
-#set_location_assignment PIN_F16 -to GPIO_2[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
-#set_location_assignment PIN_F14 -to GPIO_2[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
-#set_location_assignment PIN_G16 -to GPIO_2[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
-#set_location_assignment PIN_G15 -to GPIO_2[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
-#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
-#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
-#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
-
-#============================================================
-# GPIO_0, GPIO_0 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
-#set_location_assignment PIN_D3 -to GPIO_0[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
-#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
-#set_location_assignment PIN_C3 -to GPIO_0[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
-#set_location_assignment PIN_A2 -to GPIO_0[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
-#set_location_assignment PIN_A3 -to GPIO_0[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
-#set_location_assignment PIN_B3 -to GPIO_0[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
-#set_location_assignment PIN_B4 -to GPIO_0[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
-#set_location_assignment PIN_A4 -to GPIO_0[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
-#set_location_assignment PIN_B5 -to GPIO_0[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
-#set_location_assignment PIN_A5 -to GPIO_0[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
-#set_location_assignment PIN_D5 -to GPIO_0[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
-#set_location_assignment PIN_B6 -to GPIO_0[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
-#set_location_assignment PIN_A6 -to GPIO_0[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
-#set_location_assignment PIN_B7 -to GPIO_0[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
-#set_location_assignment PIN_D6 -to GPIO_0[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
-#set_location_assignment PIN_A7 -to GPIO_0[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
-#set_location_assignment PIN_C6 -to GPIO_0[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
-#set_location_assignment PIN_C8 -to GPIO_0[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
-#set_location_assignment PIN_E6 -to GPIO_0[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
-#set_location_assignment PIN_E7 -to GPIO_0[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
-#set_location_assignment PIN_D8 -to GPIO_0[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
-#set_location_assignment PIN_E8 -to GPIO_0[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
-#set_location_assignment PIN_F8 -to GPIO_0[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
-#set_location_assignment PIN_F9 -to GPIO_0[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
-#set_location_assignment PIN_E9 -to GPIO_0[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
-#set_location_assignment PIN_C9 -to GPIO_0[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
-#set_location_assignment PIN_D9 -to GPIO_0[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
-#set_location_assignment PIN_E11 -to GPIO_0[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
-#set_location_assignment PIN_E10 -to GPIO_0[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
-#set_location_assignment PIN_C11 -to GPIO_0[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
-#set_location_assignment PIN_B11 -to GPIO_0[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
-#set_location_assignment PIN_A12 -to GPIO_0[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
-#set_location_assignment PIN_D11 -to GPIO_0[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-#set_location_assignment PIN_D12 -to GPIO_0[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
-#set_location_assignment PIN_B12 -to GPIO_0[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
-
-#============================================================
-# GPIO_1, GPIO_1 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
-#set_location_assignment PIN_F13 -to GPIO_1[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
-#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
-#set_location_assignment PIN_T15 -to GPIO_1[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
-#set_location_assignment PIN_T14 -to GPIO_1[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
-#set_location_assignment PIN_T13 -to GPIO_1[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
-#set_location_assignment PIN_R13 -to GPIO_1[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
-#set_location_assignment PIN_T12 -to GPIO_1[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
-#set_location_assignment PIN_R12 -to GPIO_1[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
-#set_location_assignment PIN_T11 -to GPIO_1[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
-#set_location_assignment PIN_T10 -to GPIO_1[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
-#set_location_assignment PIN_R11 -to GPIO_1[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
-#set_location_assignment PIN_P11 -to GPIO_1[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
-#set_location_assignment PIN_R10 -to GPIO_1[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
-#set_location_assignment PIN_N12 -to GPIO_1[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
-#set_location_assignment PIN_P9 -to GPIO_1[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
-#set_location_assignment PIN_N9 -to GPIO_1[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
-#set_location_assignment PIN_N11 -to GPIO_1[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
-#set_location_assignment PIN_L16 -to GPIO_1[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
-#set_location_assignment PIN_K16 -to GPIO_1[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
-#set_location_assignment PIN_R16 -to GPIO_1[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
-#set_location_assignment PIN_L15 -to GPIO_1[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
-#set_location_assignment PIN_P15 -to GPIO_1[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
-#set_location_assignment PIN_P16 -to GPIO_1[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
-#set_location_assignment PIN_R14 -to GPIO_1[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
-#set_location_assignment PIN_N16 -to GPIO_1[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
-#set_location_assignment PIN_N15 -to GPIO_1[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
-#set_location_assignment PIN_P14 -to GPIO_1[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
-#set_location_assignment PIN_L14 -to GPIO_1[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
-#set_location_assignment PIN_N14 -to GPIO_1[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
-#set_location_assignment PIN_M10 -to GPIO_1[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
-#set_location_assignment PIN_L13 -to GPIO_1[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
-#set_location_assignment PIN_J16 -to GPIO_1[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
-#set_location_assignment PIN_K15 -to GPIO_1[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
-#set_location_assignment PIN_J13 -to GPIO_1[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
-#set_location_assignment PIN_J14 -to GPIO_1[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
-
-#============================================================
-# End of pin assignments by Terasic System Builder
-#============================================================
-
-
+
+#============================================================
+# EPCS
+#============================================================
+#set_location_assignment PIN_H2 -to EPCS_DATA0
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
+#set_location_assignment PIN_H1 -to EPCS_DCLK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
+#set_location_assignment PIN_D2 -to EPCS_NCSO
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
+#set_location_assignment PIN_C1 -to EPCS_ASDO
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
+
+#============================================================
+# Accelerometer and EEPROM
+#============================================================
+#set_location_assignment PIN_F2 -to I2C_SCLK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
+#set_location_assignment PIN_F1 -to I2C_SDAT
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
+#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
+#set_location_assignment PIN_M2 -to G_SENSOR_INT
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
+
+#============================================================
+# ADC
+#============================================================
+#set_location_assignment PIN_A10 -to ADC_CS_N
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
+#set_location_assignment PIN_B10 -to ADC_SADDR
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
+#set_location_assignment PIN_B14 -to ADC_SCLK
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
+#set_location_assignment PIN_A9 -to ADC_SDAT
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
+
+#============================================================
+# 2x13 GPIO Header
+#============================================================
+#set_location_assignment PIN_A14 -to GPIO_2[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
+#set_location_assignment PIN_B16 -to GPIO_2[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
+#set_location_assignment PIN_C14 -to GPIO_2[2]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
+#set_location_assignment PIN_C16 -to GPIO_2[3]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
+#set_location_assignment PIN_C15 -to GPIO_2[4]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
+#set_location_assignment PIN_D16 -to GPIO_2[5]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
+#set_location_assignment PIN_D15 -to GPIO_2[6]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
+#set_location_assignment PIN_D14 -to GPIO_2[7]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
+#set_location_assignment PIN_F15 -to GPIO_2[8]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
+#set_location_assignment PIN_F16 -to GPIO_2[9]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
+#set_location_assignment PIN_F14 -to GPIO_2[10]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
+#set_location_assignment PIN_G16 -to GPIO_2[11]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
+#set_location_assignment PIN_G15 -to GPIO_2[12]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
+#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
+#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
+#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
+
+#============================================================
+# GPIO_0, GPIO_0 connect to GPIO Default
+#============================================================
+#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
+#set_location_assignment PIN_D3 -to GPIO_0[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
+#set_location_assignment PIN_C3 -to GPIO_0[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+#set_location_assignment PIN_A2 -to GPIO_0[2]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+#set_location_assignment PIN_A3 -to GPIO_0[3]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+#set_location_assignment PIN_B3 -to GPIO_0[4]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+#set_location_assignment PIN_B4 -to GPIO_0[5]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+#set_location_assignment PIN_A4 -to GPIO_0[6]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+#set_location_assignment PIN_B5 -to GPIO_0[7]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+#set_location_assignment PIN_A5 -to GPIO_0[8]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+#set_location_assignment PIN_D5 -to GPIO_0[9]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+#set_location_assignment PIN_B6 -to GPIO_0[10]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+#set_location_assignment PIN_A6 -to GPIO_0[11]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+#set_location_assignment PIN_B7 -to GPIO_0[12]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+#set_location_assignment PIN_D6 -to GPIO_0[13]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+#set_location_assignment PIN_A7 -to GPIO_0[14]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+#set_location_assignment PIN_C6 -to GPIO_0[15]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+#set_location_assignment PIN_C8 -to GPIO_0[16]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+#set_location_assignment PIN_E6 -to GPIO_0[17]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+#set_location_assignment PIN_E7 -to GPIO_0[18]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+#set_location_assignment PIN_D8 -to GPIO_0[19]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+#set_location_assignment PIN_E8 -to GPIO_0[20]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+#set_location_assignment PIN_F8 -to GPIO_0[21]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+#set_location_assignment PIN_F9 -to GPIO_0[22]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+#set_location_assignment PIN_E9 -to GPIO_0[23]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+#set_location_assignment PIN_C9 -to GPIO_0[24]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+#set_location_assignment PIN_D9 -to GPIO_0[25]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+#set_location_assignment PIN_E11 -to GPIO_0[26]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+#set_location_assignment PIN_E10 -to GPIO_0[27]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+#set_location_assignment PIN_C11 -to GPIO_0[28]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+#set_location_assignment PIN_B11 -to GPIO_0[29]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+#set_location_assignment PIN_A12 -to GPIO_0[30]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+#set_location_assignment PIN_D11 -to GPIO_0[31]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+#set_location_assignment PIN_D12 -to GPIO_0[32]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
+#set_location_assignment PIN_B12 -to GPIO_0[33]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
+
+#============================================================
+# GPIO_1, GPIO_1 connect to GPIO Default
+#============================================================
+#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
+#set_location_assignment PIN_F13 -to GPIO_1[0]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
+#set_location_assignment PIN_T15 -to GPIO_1[1]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+#set_location_assignment PIN_T14 -to GPIO_1[2]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+#set_location_assignment PIN_T13 -to GPIO_1[3]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+#set_location_assignment PIN_R13 -to GPIO_1[4]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+#set_location_assignment PIN_T12 -to GPIO_1[5]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+#set_location_assignment PIN_R12 -to GPIO_1[6]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+#set_location_assignment PIN_T11 -to GPIO_1[7]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+#set_location_assignment PIN_T10 -to GPIO_1[8]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+#set_location_assignment PIN_R11 -to GPIO_1[9]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+#set_location_assignment PIN_P11 -to GPIO_1[10]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+#set_location_assignment PIN_R10 -to GPIO_1[11]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+#set_location_assignment PIN_N12 -to GPIO_1[12]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+#set_location_assignment PIN_P9 -to GPIO_1[13]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+#set_location_assignment PIN_N9 -to GPIO_1[14]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+#set_location_assignment PIN_N11 -to GPIO_1[15]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+#set_location_assignment PIN_L16 -to GPIO_1[16]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+#set_location_assignment PIN_K16 -to GPIO_1[17]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+#set_location_assignment PIN_R16 -to GPIO_1[18]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+#set_location_assignment PIN_L15 -to GPIO_1[19]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+#set_location_assignment PIN_P15 -to GPIO_1[20]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+#set_location_assignment PIN_P16 -to GPIO_1[21]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+#set_location_assignment PIN_R14 -to GPIO_1[22]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+#set_location_assignment PIN_N16 -to GPIO_1[23]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+#set_location_assignment PIN_N15 -to GPIO_1[24]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+#set_location_assignment PIN_P14 -to GPIO_1[25]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+#set_location_assignment PIN_L14 -to GPIO_1[26]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+#set_location_assignment PIN_N14 -to GPIO_1[27]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+#set_location_assignment PIN_M10 -to GPIO_1[28]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+#set_location_assignment PIN_L13 -to GPIO_1[29]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+#set_location_assignment PIN_J16 -to GPIO_1[30]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+#set_location_assignment PIN_K15 -to GPIO_1[31]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+#set_location_assignment PIN_J13 -to GPIO_1[32]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
+#set_location_assignment PIN_J14 -to GPIO_1[33]
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
+
+#============================================================
+# End of pin assignments by Terasic System Builder
+#============================================================
+
+
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
@@ -449,13 +449,13 @@ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*]
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
-
+
 set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
-
+
 set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
 set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-
-
+
+
 set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd
 set_global_assignment -name QIP_FILE Clock_50to100.qip
 set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc
@@ -465,6 +465,7 @@ set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
+set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_STcache.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
@@ -477,6 +478,7 @@ set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
+set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_DualPort3264BootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd

build/QMV_zpu.qsf

@@ -425,6 +425,7 @@ set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
+set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_STcache.vhd
 set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
 set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
@@ -437,6 +438,7 @@ set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_BootROM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_DualPortBootBRAM.vhd
+set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_DualPort3264BootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_SinglePortBootBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/zOS_SinglePortBRAM.vhd
 set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd

docker/QuartusPrime/files/13.0

@@ -0,0 +1 @@
+/srv/dvlp/Projects/dev/github/docker/QuartusPrime/files/13.0

docker/QuartusPrime/files/13.1

@@ -0,0 +1 @@
+/srv/dvlp/Projects/dev/github/docker/QuartusPrime/files/13.1

docker/QuartusPrime/files/17.1

@@ -0,0 +1 @@
+/srv/dvlp/Projects/dev/github/docker/QuartusPrime/files/17.1

zpu_soc_pkg.tmpl.vhd

@@ -31,9 +31,25 @@ library ieee;
 library pkgs;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use ieee.math_real.all;
 use work.zpu_pkg.all;
 
 package zpu_soc_pkg is
+    ------------------------------------------------------------ 
+    -- Function prototypes
+    ------------------------------------------------------------ 
+    -- Find the maximum of two integers.
+    function IntMax(a : in integer; b : in integer) return integer;
+
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer;
+
+    ------------------------------------------------------------ 
+    -- Constants
+    ------------------------------------------------------------ 
 
     -- Choose which CPU to instantiate depending on requirements. Warning, keep the below 5 lines exactly the same
     -- or ensure you update the Makefile as they are set by the Makefile to generate zpu_soc_pkg.vhd
@@ -44,10 +60,18 @@ package zpu_soc_pkg is
     constant ZPU_EVO                  :     integer    := 0;                                                -- Use the EVOLUTION CPU.
     constant ZPU_EVO_MINIMAL          :     integer    := 0;                                                -- Use the Minimalist EVOLUTION CPU.
 
+    -- Target board declaration.
+    --
+    constant BOARD_E115               :     boolean    := true;                                             -- E115 FPGA Board
+    constant BOARD_QMV                :     boolean    := false;                                            -- QMTECH Cyclone V FPGA Board
+    constant BOARD_DE0                :     boolean    := false;                                            -- DE0-Nano FPGA Board
+    constant BOARD_DE10               :     boolean    := false;                                            -- DE10-Nano FPGA Board
+    constant BOARD_CYC1000            :     boolean    := false;                                            -- Trenz CYC1000 FPGA Board
+
     -- Frequencies for the various boards.
     --
-    constant SYSCLK_E115_FREQ         :     integer    := 100000000;                                        -- E115 FPGA Board
-    constant SYSCLK_QMV_FREQ          :     integer    := 100000000;                                        -- QMTECH Cyclone V FPGA Board
+    constant SYSCLK_E115_FREQ         :     integer    := 75000000;                                         -- E115 FPGA Board
+    constant SYSCLK_QMV_FREQ          :     integer    := 75000000;                                         -- QMTECH Cyclone V FPGA Board
     constant SYSCLK_DE0_FREQ          :     integer    := 100000000;                                        -- DE0-Nano FPGA Board
     constant SYSCLK_DE10_FREQ         :     integer    := 100000000;                                        -- DE10-Nano FPGA Board
     constant SYSCLK_CYC1000_FREQ      :     integer    := 100000000;                                        -- Trenz CYC1000 FPGA Board
@@ -56,15 +80,17 @@ package zpu_soc_pkg is
     constant ZPU_ID_SMALL             :     integer    := 16#0101#;                                         -- ID for the ZPU Small in this package.
     constant ZPU_ID_MEDIUM            :     integer    := 16#0201#;                                         -- ID for the ZPU Medium in this package.
     constant ZPU_ID_FLEX              :     integer    := 16#0301#;                                         -- ID for the ZPU Flex in this package.
-    constant ZPU_ID_EVO               :     integer    := 16#0401#;                                         -- ID for the ZPU Evo in this package.
-    constant ZPU_ID_EVO_MINIMAL       :     integer    := 16#0501#;                                         -- ID for the ZPU Evo Minimal in this package.
+    constant ZPU_ID_EVO               :     integer    := 16#0402#;                                         -- ID for the ZPU Evo in this package.
+    constant ZPU_ID_EVO_MINIMAL       :     integer    := 16#0502#;                                         -- ID for the ZPU Evo Minimal in this package.
 
     -- EVO CPU specific configuration.
     constant MAX_EVO_L1CACHE_BITS     :     integer    := 5;                                                -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
     constant MAX_EVO_L2CACHE_BITS     :     integer    := 12;                                               -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
+    constant MAX_EVO_STCACHE_BITS     :     integer    := 8;                                                -- Maximum size in 32bit words of the stack cache, governed by the number of bits, ie. 8 - 256 x 32bit cache.
     constant MAX_EVO_MXCACHE_BITS     :     integer    := 3;                                                -- Maximum size of the memory transaction cache governed by the number of bits.
     constant MAX_EVO_MIN_L1CACHE_BITS :     integer    := 4;                                                -- Maximum size in instructions of the Level 0 instruction cache governed by the number of bits, ie. 8 = 256 instruction cache.
     constant MAX_EVO_MIN_L2CACHE_BITS :     integer    := 12;                                               -- Maximum bit size in bytes of the Level 2 instruction cache governed by the number of bits, ie. 8 = 256 byte cache.
+    constant MAX_EVO_MIN_STCACHE_BITS :     integer    := 8;                                                -- Maximum size in 32bit words of the stack cache, governed by the number of bits, ie. 8 - 256 x 32bit cache.
     constant MAX_EVO_MIN_MXCACHE_BITS :     integer    := 3;                                                -- Maximum size of the memory transaction cache governed by the number of bits.
 
     -- Settings for various IO devices.
@@ -72,39 +98,68 @@ package zpu_soc_pkg is
     constant MAX_RX_FIFO_BITS         :     integer    := 8;                                                -- Size of UART RX Fifo.
     constant MAX_TX_FIFO_BITS         :     integer    := 8;                                                -- Size of UART TX Fifo.
     constant MAX_UART_DIVISOR_BITS    :     integer    := 16;                                               -- Maximum number of bits for the UART clock rate generator divisor.
-    constant INTR_MAX                 :     integer    := 16;                                               -- Maximum number of interrupt inputs.
-    constant SYSTEM_FREQUENCY         :     integer    := 100000000;                                        -- Default system clock frequency if not overriden by top level.
---    constant SYSCLK_FREQUENCY         :     integer    := 1000;                                             -- System clock in MHz x 10
---    constant SYSCLK_HZ                :     integer    := SYSCLK_FREQUENCY*100000;                          -- System clock in Hertz
---    constant UART_RESET_COUNT         :     integer    := ((SYSCLK_FREQUENCY*100000)/300)*8;                -- Count of system clock ticks for a UART break to be recognised as a system reset.
+    constant SYSTEM_FREQUENCY         :     integer    := 75000000;                                        -- Default system clock frequency if not overriden in top level.
 
     -- SoC specific options.
     --
     constant SOC_IMPL_WB              :     boolean    := EVO_USE_WB_BUS;                                   -- Implement the Wishbone bus and all enabled devices.
-    constant SOC_IMPL_WB_I2C          :     boolean    := true;                                             -- Implement I2C over wishbone interface.
-    constant SOC_IMPL_WB_SDRAM        :     boolean    := true;                                             -- Implement SDRAM over wishbone interface.
+    constant SOC_IMPL_WB_I2C          :     boolean    := false;                                            -- Implement I2C over wishbone interface.
     constant SOC_IMPL_TIMER1          :     boolean    := true;                                             -- Implement Timer 1, an array of prescaled downcounter with enable.
     constant SOC_TIMER1_COUNTERS      :     integer    := 0;                                                -- Number of downcounters in Timer 1. Value is a 2^ array of counters, so 0 = 1 counter.
-    constant SOC_IMPL_PS2             :     boolean    := true;                                             -- Implement PS2 keyboard and mouse hardware.
-    constant SOC_IMPL_SPI             :     boolean    := true;                                             -- Implement Serial Peripheral Inteface(s).
+    constant SOC_IMPL_PS2             :     boolean    := false;                                            -- Implement PS2 keyboard and mouse hardware.
+    constant SOC_IMPL_SPI             :     boolean    := false;                                            -- Implement Serial Peripheral Inteface(s).
     constant SOC_IMPL_SD              :     boolean    := true;                                             -- Implement SD Card interface.
     constant SOC_SD_DEVICES           :     integer    := 1;                                                -- Number of SD card channels implemented.
     constant SOC_IMPL_INTRCTL         :     boolean    := true;                                             -- Implement the prioritised interrupt controller.
+    constant SOC_INTR_MAX             :     integer    := 16;                                               -- Maximum number of interrupt inputs.
     constant SOC_IMPL_IOCTL           :     boolean    := false;                                            -- Implement the IOCTL controller (specific to the MiSTer project).
     constant SOC_IMPL_SOCCFG          :     boolean    := true;                                             -- Implement the SoC Configuration information registers.
+    -- Main Boot BRAM on sysbus, contains startup firmware.
     constant SOC_IMPL_BRAM            :     boolean    := true;                                             -- Implement BRAM for the BIOS and initial Stack.
-    constant SOC_IMPL_RAM             :     boolean    := false;                                            -- Implement RAM using BRAM, typically for Application programs seperate to BIOS.
-    constant SOC_IMPL_DRAM            :     boolean    := false;                                            -- Implement Dynamic RAM and controller.
-    constant SOC_IMPL_INSN_BRAM       :     boolean    := true;                                             -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory.
-    constant SOC_MAX_ADDR_BRAM_BIT    :     integer    := 16;                                               -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same.
+    constant SOC_IMPL_INSN_BRAM       :     boolean    := EVO_USE_INSN_BUS;                                 -- Implement dedicated instruction BRAM for the EVO CPU. Any addr access beyond the BRAM size goes to normal memory.
+    constant SOC_MAX_ADDR_BRAM_BIT    :     integer    := 17;                                               -- Max address bit of the System BRAM ROM/Stack in bytes, ie. 15 = 32KB or 8K 32bit words. NB. For non evo CPUS you must adjust the maxMemBit parameter in zpu_pkg.vhd to be the same.
     constant SOC_ADDR_BRAM_START      :     integer    := 0;                                                -- Start address of BRAM.
     constant SOC_ADDR_BRAM_END        :     integer    := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_BRAM_BIT);   -- End address of BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
-    constant SOC_MAX_ADDR_RAM_BIT     :     integer    := 23;                                               -- Max address bit of the System RAM.
-    constant SOC_ADDR_RAM_START       :     integer    := 16777216;                                         -- Start address of RAM.
+    -- Secondary block of sysbus RAM, typically implemented in BRAM.
+    constant SOC_IMPL_RAM             :     boolean    := false;                                            -- Implement RAM using BRAM, typically for Application programs seperate to BIOS.
+    constant SOC_MAX_ADDR_RAM_BIT     :     integer    := 16;                                               -- Max address bit of the System RAM.
+    constant SOC_ADDR_RAM_START       :     integer    := 65536;                                            -- Start address of RAM.
     constant SOC_ADDR_RAM_END         :     integer    := SOC_ADDR_RAM_START+(2**SOC_MAX_ADDR_RAM_BIT);     -- End address of RAM =  START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
+    -- SDRAM on sysbus.
+    constant SOC_IMPL_SDRAM           :     boolean    := false;                                            -- Implement Dynamic RAM and controller.
+    constant SOC_SDRAM_ROWS           :     integer    := 4096;                                             -- Number of Rows within the SDRAM.
+    constant SOC_SDRAM_COLUMNS        :     integer    := 256;                                              -- Number of Columns within the SDRAM.
+    constant SOC_SDRAM_BANKS          :     integer    := 4;                                                -- Number of Banks within the SDRAM.
+    constant SOC_SDRAM_DATAWIDTH      :     integer    := 16;                                               -- Data width of SDRAM (ie. 16, 32bit).
+    constant SOC_SDRAM_CLK_FREQ       :     integer    := 100000000;                                        -- Frequency of the SDRAM clock.
+    constant SOC_SDRAM_tRCD           :     integer    := 20;                                               -- tRCD - RAS to CAS minimum period (in ns).
+    constant SOC_SDRAM_tRP            :     integer    := 20;                                               -- tRP  - Precharge delay, min time for a precharge command to complete (in ns).
+    constant SOC_SDRAM_tRFC           :     integer    := 70;                                               -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns
+    constant SOC_SDRAM_tREF           :     integer    := 64;                                               -- tREF - period of time a complete refresh of all rows is made within (in ms).
+    constant SOC_MAX_ADDR_SDRAM_BIT   :     integer    := log2ceil(SOC_SDRAM_ROWS * SOC_SDRAM_COLUMNS * SOC_SDRAM_BANKS)+1; -- Max address bit of the System SDRAM.
+    constant SOC_ADDR_SDRAM_START     :     integer    := 65536;                                            -- Start address of RAM.
+    constant SOC_ADDR_SDRAM_END       :     integer    := SOC_ADDR_SDRAM_START+(2**SOC_MAX_ADDR_SDRAM_BIT); -- End address of RAM =  START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
+    -- SDRAM on Wishbone bus.
+    constant SOC_IMPL_WB_SDRAM        :     boolean    := false;                                            -- Implement SDRAM over wishbone interface.
+    constant SOC_WB_SDRAM_ROWS        :     integer    := 4096;                                             -- Number of Rows within the SDRAM.
+    constant SOC_WB_SDRAM_COLUMNS     :     integer    := 256;                                              -- Number of Columns within the SDRAM.
+    constant SOC_WB_SDRAM_BANKS       :     integer    := 4;                                                -- Number of Banks within the SDRAM.
+    constant SOC_WB_SDRAM_DATAWIDTH   :     integer    := 16;                                               -- Data width of SDRAM (ie. 16, 32bit).
+    constant SOC_WB_SDRAM_CLK_FREQ    :     integer    := 100000000;                                        -- Frequency of the SDRAM clock.
+    constant SOC_WB_SDRAM_tRCD        :     integer    := 20;                                               -- tRCD - RAS to CAS minimum period (in ns).
+    constant SOC_WB_SDRAM_tRP         :     integer    := 20;                                               -- tRP  - Precharge delay, min time for a precharge command to complete (in ns).
+    constant SOC_WB_SDRAM_tRFC        :     integer    := 70;                                               -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns
+    constant SOC_WB_SDRAM_tREF        :     integer    := 64;                                               -- tREF - period of time a complete refresh of all rows is made within (in ms).
+    constant SOC_MAX_ADDR_WB_SDRAM_BIT:     integer    := log2ceil(SOC_WB_SDRAM_ROWS * SOC_WB_SDRAM_COLUMNS * SOC_WB_SDRAM_BANKS)+1; -- Max address bit of the System SDRAM.
+    constant SOC_ADDR_WB_SDRAM_START  :     integer    := 16777216;                                         -- Start address of RAM.
+    constant SOC_ADDR_WB_SDRAM_END    :     integer    := SOC_ADDR_WB_SDRAM_START+(2**SOC_MAX_ADDR_WB_SDRAM_BIT); -- End address of RAM =  START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
+    -- Instruction BRAM on sysbus, typically as a 2nd port on the main Boot BRAM (ie. dualport).
     constant SOC_MAX_ADDR_INSN_BRAM_BIT:    integer    := SOC_MAX_ADDR_BRAM_BIT;                            -- Max address bit of the dedicated instruction BRAM in bytes, ie. 15 = 32KB or 8K 32bit words.
     constant SOC_ADDR_INSN_BRAM_START :     integer    := 0;                                                -- Start address of dedicated instrution BRAM.
     constant SOC_ADDR_INSN_BRAM_END   :     integer    := SOC_ADDR_BRAM_START+(2**SOC_MAX_ADDR_INSN_BRAM_BIT); -- End address of dedicated instruction BRAM = START + 2^SOC_MAX_ADDR_INSN_BRAM_BIT.
+
+    -- CPU specific settings.
+    -- Define the address which is first executed upon reset, stack address, Sysbus I/O Region, Wishbone I/O Region.
     constant SOC_RESET_ADDR_CPU       :     integer    := SOC_ADDR_BRAM_START;                              -- Initial address to start execution from after reset.
     constant SOC_START_ADDR_MEM       :     integer    := SOC_ADDR_BRAM_START;                              -- Start location of program memory (BRAM/ROM/RAM).
     constant SOC_STACK_ADDR           :     integer    := SOC_ADDR_BRAM_END - 8;                            -- Stack start address (BRAM/RAM).
@@ -113,39 +168,95 @@ package zpu_soc_pkg is
     constant SOC_WB_IO_START          :     integer    := 32505856;                                         -- Start address of IO range.
     constant SOC_WB_IO_END            :     integer    := 33554431;                                         -- End address of IO range.
 
+    -- ZPU Evo configuration
+    --
+    -- Optional Evo CPU hardware features to be implemented.
+    constant IMPL_EVO_OPTIMIZE_IM     :     boolean    := true;                                             -- If the instruction cache is enabled, optimise Im instructions to gain speed.
+    -- Optional Evo CPU instructions to be implemented in hardware:
+    constant IMPL_EVO_ASHIFTLEFT      :     boolean    := true;                                             -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT).
+    constant IMPL_EVO_ASHIFTRIGHT     :     boolean    := true;                                             -- Arithmetic Shift Right.
+    constant IMPL_EVO_CALL            :     boolean    := true;                                             -- Call to direct address.
+    constant IMPL_EVO_CALLPCREL       :     boolean    := true;                                             -- Call to indirect address (add offset to program counter).
+    constant IMPL_EVO_DIV             :     boolean    := true;                                             -- 32bit signed division.
+    constant IMPL_EVO_EQ              :     boolean    := true;                                             -- Equality test.
+    constant IMPL_EVO_EXTENDED_INSN   :     boolean    := true;                                             -- Extended multibyte instruction set.
+    constant IMPL_EVO_FIADD32         :     boolean    := false;                                            -- Fixed point Q17.15 addition.
+    constant IMPL_EVO_FIDIV32         :     boolean    := false;                                            -- Fixed point Q17.15 division.
+    constant IMPL_EVO_FIMULT32        :     boolean    := false;                                            -- Fixed point Q17.15 multiplication.
+    constant IMPL_EVO_LOADB           :     boolean    := true;                                             -- Load single byte from memory.
+    constant IMPL_EVO_LOADH           :     boolean    := true;                                             -- Load half word (16bit) from memory.
+    constant IMPL_EVO_LSHIFTRIGHT     :     boolean    := true;                                             -- Logical shift right.
+    constant IMPL_EVO_MOD             :     boolean    := true;                                             -- 32bit modulo (remainder after division).
+    constant IMPL_EVO_MULT            :     boolean    := true;                                             -- 32bit signed multiplication.
+    constant IMPL_EVO_NEG             :     boolean    := true;                                             -- Negate value in TOS.
+    constant IMPL_EVO_NEQ             :     boolean    := true;                                             -- Not equal test.
+    constant IMPL_EVO_POPPCREL        :     boolean    := true;                                             -- Pop a value into the Program Counter from a location relative to the Stack Pointer.
+    constant IMPL_EVO_PUSHSPADD       :     boolean    := true;                                             -- Add a value to the Stack pointer and push it onto the stack.
+    constant IMPL_EVO_STOREB          :     boolean    := true;                                             -- Store/Write a single byte to memory/IO.
+    constant IMPL_EVO_STOREH          :     boolean    := true;                                             -- Store/Write a half word (16bit) to memory/IO.
+    constant IMPL_EVO_SUB             :     boolean    := true;                                             -- 32bit signed subtract.
+    constant IMPL_EVO_XOR             :     boolean    := true;                                             -- Exclusive or of value in TOS.
+
+    -- ZPU Evo Minimal configuration
+    --
+    -- Optional Evo Minimal CPU hardware features to be implemented.
+    constant IMPL_EVOM_OPTIMIZE_IM    :     boolean    := true;                                             -- If the instruction cache is enabled, optimise Im instructions to gain speed.
+    -- Optional Evo Minimal CPU instructions to be implemented in hardware:
+    constant IMPL_EVOM_ASHIFTLEFT     :     boolean    := false;                                             -- Arithmetic Shift Left (uses same logic so normally combined with ASHIFTRIGHT and LSHIFTRIGHT).
+    constant IMPL_EVOM_ASHIFTRIGHT    :     boolean    := false;                                             -- Arithmetic Shift Right.
+    constant IMPL_EVOM_CALL           :     boolean    := false;                                             -- Call to direct address.
+    constant IMPL_EVOM_CALLPCREL      :     boolean    := false;                                             -- Call to indirect address (add offset to program counter).
+    constant IMPL_EVOM_DIV            :     boolean    := false;                                             -- 32bit signed division.
+    constant IMPL_EVOM_EQ             :     boolean    := false;                                             -- Equality test.
+    constant IMPL_EVOM_EXTENDED_INSN  :     boolean    := false;                                             -- Extended multibyte instruction set.
+    constant IMPL_EVOM_FIADD32        :     boolean    := false;                                             -- Fixed point Q17.15 addition.
+    constant IMPL_EVOM_FIDIV32        :     boolean    := false;                                             -- Fixed point Q17.15 division.
+    constant IMPL_EVOM_FIMULT32       :     boolean    := false;                                             -- Fixed point Q17.15 multiplication.
+    constant IMPL_EVOM_LOADB          :     boolean    := false;                                             -- Load single byte from memory.
+    constant IMPL_EVOM_LOADH          :     boolean    := false;                                             -- Load half word (16bit) from memory.
+    constant IMPL_EVOM_LSHIFTRIGHT    :     boolean    := false;                                             -- Logical shift right.
+    constant IMPL_EVOM_MOD            :     boolean    := false;                                             -- 32bit modulo (remainder after division).
+    constant IMPL_EVOM_MULT           :     boolean    := false;                                             -- 32bit signed multiplication.
+    constant IMPL_EVOM_NEG            :     boolean    := false;                                             -- Negate value in TOS.
+    constant IMPL_EVOM_NEQ            :     boolean    := false;                                             -- Not equal test.
+    constant IMPL_EVOM_POPPCREL       :     boolean    := false;                                             -- Pop a value into the Program Counter from a location relative to the Stack Pointer.
+    constant IMPL_EVOM_PUSHSPADD      :     boolean    := false;                                             -- Add a value to the Stack pointer and push it onto the stack.
+    constant IMPL_EVOM_STOREB         :     boolean    := false;                                             -- Store/Write a single byte to memory/IO.
+    constant IMPL_EVOM_STOREH         :     boolean    := false;                                             -- Store/Write a half word (16bit) to memory/IO.
+    constant IMPL_EVOM_SUB            :     boolean    := false;                                             -- 32bit signed subtract.
+    constant IMPL_EVOM_XOR            :     boolean    := false;                                             -- Exclusive or of value in TOS.
+
     -- Ranges used throughout the SOC source.
-    subtype ADDR_BIT_BRAM_RANGE       is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 0;                    -- Address range of the onboard B(lock)RAM - 1 byte aligned
-    subtype ADDR_BIT_BRAM_16BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto 1;                    -- Address range of the onboard B(lock)RAM - 2 bytes aligned
-    subtype ADDR_BIT_BRAM_32BIT_RANGE is natural range SOC_MAX_ADDR_BRAM_BIT-1 downto minAddrBit;           -- Address range of the onboard B(lock)RAM - 4 bytes aligned
-    subtype ADDR_BIT_RAM_RANGE        is natural range SOC_MAX_ADDR_RAM_BIT-1  downto 0;                    -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
-    subtype ADDR_BIT_RAM_16BIT_RANGE  is natural range SOC_MAX_ADDR_RAM_BIT-1  downto 1;                    -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
-    subtype ADDR_BIT_RAM_32BIT_RANGE  is natural range SOC_MAX_ADDR_RAM_BIT-1  downto minAddrBit;           -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
---  subtype ADDR_DECODE_BRAM_RANGE    is natural range maxAddrBit-1            downto SOC_MAX_ADDR_BRAM_BIT;-- Decode range for selection of the BRAM within the address space.
---  subtype ADDR_DECODE_RAM_RANGE     is natural range maxAddrBit-1            downto SOC_MAX_ADDR_RAM_BIT; -- Decode range for selection of the RAM within the address space.
-    subtype IO_DECODE_RANGE           is natural range maxAddrBit-WB_ACTIVE-1  downto maxIOBit;             -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
---    subtype WB_IO_DECODE_RANGE        is natural range maxAddrBit-1            downto maxIOBit;             -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
+    subtype ADDR_BIT_BRAM_RANGE           is natural range SOC_MAX_ADDR_BRAM_BIT-1   downto 0;              -- Address range of the onboard B(lock)RAM - 1 byte aligned
+    subtype ADDR_16BIT_BRAM_RANGE         is natural range SOC_MAX_ADDR_BRAM_BIT-1   downto 1;              -- Address range of the onboard B(lock)RAM - 2 bytes aligned
+    subtype ADDR_32BIT_BRAM_RANGE         is natural range SOC_MAX_ADDR_BRAM_BIT-1   downto minAddrBit;     -- Address range of the onboard B(lock)RAM - 4 bytes aligned
+    subtype ADDR_64BIT_BRAM_RANGE         is natural range SOC_MAX_ADDR_BRAM_BIT-1   downto minAddrBit+1;   -- Address range of the onboard B(lock)RAM - 8 bytes aligned
+    subtype ADDR_BIT_RAM_RANGE            is natural range SOC_MAX_ADDR_RAM_BIT-1    downto 0;              -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
+    subtype ADDR_16BIT_RAM_RANGE          is natural range SOC_MAX_ADDR_RAM_BIT-1    downto 1;              -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
+    subtype ADDR_32BIT_RAM_RANGE          is natural range SOC_MAX_ADDR_RAM_BIT-1    downto minAddrBit;     -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
+    subtype ADDR_BIT_SDRAM_RANGE          is natural range SOC_MAX_ADDR_SDRAM_BIT-1  downto 0;              -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
+    subtype ADDR_16BIT_SDRAM_RANGE        is natural range SOC_MAX_ADDR_SDRAM_BIT-1  downto 1;              -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
+    subtype ADDR_32BIT_SDRAM_RANGE        is natural range SOC_MAX_ADDR_SDRAM_BIT-1  downto minAddrBit;     -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
+    subtype ADDR_BIT_WB_SDRAM_RANGE       is natural range SOC_MAX_ADDR_WB_SDRAM_BIT-1  downto 0;           -- Address range of external RAM (BRAM, Dynamic, Static etc) - 1 byte aligned
+    subtype ADDR_16BIT_WB_SDRAM_RANGE     is natural range SOC_MAX_ADDR_WB_SDRAM_BIT-1  downto 1;           -- Address range of external RAM (BRAM, Dynamic, Static etc) - 2 bytes aligned
+    subtype ADDR_32BIT_WB_SDRAM_RANGE     is natural range SOC_MAX_ADDR_WB_SDRAM_BIT-1  downto minAddrBit;  -- Address range of external RAM (BRAM, Dynamic, Static etc) - 4 bytes aligned
+--  subtype ADDR_DECODE_BRAM_RANGE        is natural range maxAddrBit-1 downto SOC_MAX_ADDR_BRAM_BIT;       -- Decode range for selection of the BRAM within the address space.
+--  subtype ADDR_DECODE_RAM_RANGE         is natural range maxAddrBit-1 downto SOC_MAX_ADDR_RAM_BIT;        -- Decode range for selection of the RAM within the address space.
+    subtype IO_DECODE_RANGE               is natural range maxAddrBit-WB_ACTIVE-1    downto maxIOBit;       -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
+--    subtype WB_IO_DECODE_RANGE          is natural range maxAddrBit-1              downto maxIOBit;       -- Upper bits in memory defining the IO block within the address space for the EVO cpu IO. All other models use ioBit.
  
     -- Device options
-    type CardType_t is (SD_CARD_E, SDHC_CARD_E);                                                     -- Define the different types of SD cards.
+    type CardType_t is (SD_CARD_E, SDHC_CARD_E);                                                            -- Define the different types of SD cards.
 
+    -- Potential logic state constants.
+    constant YES                      : std_logic := '1';
+    constant NO                       : std_logic := '0';
+    constant HI                       : std_logic := '1';
+    constant LO                       : std_logic := '0';
+    constant ONE                      : std_logic := '1';
+    constant ZERO                     : std_logic := '0';
+    constant HIZ                      : std_logic := 'Z';
 
-    ------------------------------------------------------------ 
-    -- Constants
-    ------------------------------------------------------------ 
-    
-    constant YES  : std_logic := '1';
-    constant NO   : std_logic := '0';
-    constant HI   : std_logic := '1';
-    constant LO   : std_logic := '0';
-    constant ONE  : std_logic := '1';
-    constant ZERO : std_logic := '0';
-    constant HIZ  : std_logic := 'Z';
-
-    ------------------------------------------------------------ 
-    -- Function prototypes
-    ------------------------------------------------------------ 
-    -- Find the maximum of two integers.
-    function IntMax(a : in integer; b : in integer) return integer;
 
     ------------------------------------------------------------ 
     -- Records
@@ -156,7 +267,7 @@ package zpu_soc_pkg is
     ------------------------------------------------------------
     component dualport_ram is
         port (
-            clk : in std_logic;
+            clk                       : in    std_logic;
             memAWriteEnable           : in    std_logic;
             memAAddr                  : in    std_logic_vector(ADDR_32BIT_RANGE);
             memAWrite                 : in    std_logic_vector(WORD_32BIT_RANGE);
@@ -201,27 +312,27 @@ package zpu_soc_pkg is
           INIT_SPI_FREQ_G             : real              := 0.4;         -- Slow SPI clock freq. during initialization (MHz).
           SPI_FREQ_G                  : real              := 25.0;        -- Operational SPI freq. to the SD card (MHz).
           BLOCK_SIZE_G                : natural           := 512;         -- Number of bytes in an SD card block or sector.
-          CARD_TYPE_G                 : CardType_t      := SD_CARD_E    -- Type of SD card connected to this controller.
+          CARD_TYPE_G                 : CardType_t        := SD_CARD_E    -- Type of SD card connected to this controller.
           );
         port (
           -- Host-side interface signals.
-          clk_i                       : in    std_logic;                -- Master clock.
-          reset_i                     : in    std_logic   := NO;        -- active-high, synchronous  reset.
-          rd_i                        : in    std_logic   := NO;        -- active-high read block request.
-          wr_i                        : in    std_logic   := NO;        -- active-high write block request.
-          continue_i                  : in    std_logic   := NO;        -- If true, inc address and continue R/W.
+          clk_i                       : in    std_logic;                  -- Master clock.
+          reset_i                     : in    std_logic   := NO;          -- active-high, synchronous  reset.
+          rd_i                        : in    std_logic   := NO;          -- active-high read block request.
+          wr_i                        : in    std_logic   := NO;          -- active-high write block request.
+          continue_i                  : in    std_logic   := NO;          -- If true, inc address and continue R/W.
           addr_i                      : in    std_logic_vector(31 downto 0) := x"00000000";  -- Block address.
           data_i                      : in    std_logic_vector(7 downto 0)  := x"00";        -- Data to write to block.
           data_o                      : out   std_logic_vector(7 downto 0)  := x"00";        -- Data read from block.
-          busy_o                      : out   std_logic;                -- High when controller is busy performing some operation.
-          hndShk_i                    : in    std_logic;                -- High when host has data to give or has taken data.
-          hndShk_o                    : out   std_logic;                -- High when controller has taken data or has data to give.
+          busy_o                      : out   std_logic;                  -- High when controller is busy performing some operation.
+          hndShk_i                    : in    std_logic;                  -- High when host has data to give or has taken data.
+          hndShk_o                    : out   std_logic;                  -- High when controller has taken data or has data to give.
           error_o                     : out   std_logic_vector(15 downto 0) := (others => NO);
           -- I/O signals to the external SD card.
-          cs_bo                       : out   std_logic   := HI;        -- Active-low chip-select.
-          sclk_o                      : out   std_logic   := LO;        -- Serial clock to SD card.
-          mosi_o                      : out   std_logic   := HI;        -- Serial data output to SD card.
-          miso_i                      : in    std_logic   := ZERO       -- Serial data input from SD card.
+          cs_bo                       : out   std_logic   := HI;          -- Active-low chip-select.
+          sclk_o                      : out   std_logic   := LO;          -- Serial clock to SD card.
+          mosi_o                      : out   std_logic   := HI;          -- Serial data output to SD card.
+          miso_i                      : in    std_logic   := ZERO         -- Serial data input from SD card.
         );
     end component;
 
@@ -243,4 +354,34 @@ package body zpu_soc_pkg is
         return a;
     end function IntMax;
 
+    -- Find the number of bits required to represent an integer.
+    function log2ceil(arg : positive) return natural is
+        variable tmp : positive     := 1;
+        variable log : natural      := 0;
+    begin
+        if arg = 1 then
+            return 0;
+        end if;
+
+        while arg > tmp loop
+            tmp := tmp * 2;
+            log := log + 1;
+        end loop;
+        return log;
+    end function;
+
+    -- Function to calculate the number of whole 'clock' cycles in a given time period, the period being in ns.
+    function clockTicks(period : in integer; clock : in integer) return integer is
+        variable ticks         : real;
+        variable fracTicks     : real;
+    begin
+        ticks         := (Real(period) * Real(clock)) / 1000000000.0;
+        fracTicks     := ticks - CEIL(ticks);
+        if fracTicks > 0.0001 then
+            return Integer(CEIL(ticks + 1.0));
+        else
+            return Integer(CEIL(ticks));
+        end if;
+    end function;
+
 end package body;