wip updates

This commit is contained in:
Philip Smart
2020-03-02 18:05:43 +00:00
parent c74a8f7ffb
commit ad3e470755
62 changed files with 1045 additions and 11 deletions

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@@ -42,7 +42,6 @@ set_global_assignment -name TOP_LEVEL_ENTITY QMV_zpu
# ==================
set_global_assignment -name DEVICE 5CEFA2F23C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
# Assembler Assignments
# =====================
@@ -468,4 +467,7 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

23
build/ReVerSE_U16.qpf Normal file
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@@ -0,0 +1,23 @@
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "5.0"
DATE = "23:35:58 September 01, 2005"
# Revisions
PROJECT_REVISION = "ReVerSE_U16"

211
build/ReVerSE_U16.qsf Normal file
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@@ -0,0 +1,211 @@
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# ledwater_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
#set_global_assignment -name VERILOG_FILE ledwater.v
set_global_assignment -name CDF_FILE E115.cdf
# Pin & Location Assignments
# ==========================
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY ReVerSE_U16
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP4CE22E22C7
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
# Assembler Assignments
# =====================
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
#============================================================
# UART
#============================================================
set_location_assignment PIN_72 -to UART_RX_0
set_location_assignment PIN_71 -to UART_TX_0
#set_location_assignment PIN_C6 -to UART_RX_1
#set_location_assignment PIN_D7 -to UART_TX_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
#============================================================
# SD CARD
#============================================================
#set_location_assignment PIN_C8 -to SDCARD_MISO[0]
#set_location_assignment PIN_C7 -to SDCARD_MOSI[0]
#set_location_assignment PIN_B8 -to SDCARD_CLK[0]
#set_location_assignment PIN_A8 -to SDCARD_CS[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_25 -to REVERSEU16_CLOCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to REVERSEU16_CLOCK
#set_location_assignment PIN_AB11 -to clk_25M
#============================================================
# LED
#============================================================
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
#set_location_assignment PIN_A5 -to LED[0]
#set_location_assignment PIN_B5 -to LED[1]
#set_location_assignment PIN_C4 -to LED[2]
#set_location_assignment PIN_C3 -to LED[3]
set_location_assignment PIN_32 -to reset_button
set_location_assignment PIN_98 -to SDRAM_ADDR[0]
set_location_assignment PIN_86 -to SDRAM_ADDR[1]
set_location_assignment PIN_87 -to SDRAM_ADDR[2]
set_location_assignment PIN_105 -to SDRAM_ADDR[3]
set_location_assignment PIN_76 -to SDRAM_ADDR[4]
set_location_assignment PIN_77 -to SDRAM_ADDR[5]
set_location_assignment PIN_80 -to SDRAM_ADDR[6]
set_location_assignment PIN_83 -to SDRAM_ADDR[7]
set_location_assignment PIN_85 -to SDRAM_ADDR[8]
set_location_assignment PIN_67 -to SDRAM_ADDR[9]
set_location_assignment PIN_99 -to SDRAM_ADDR[10]
set_location_assignment PIN_69 -to SDRAM_ADDR[11]
set_location_assignment PIN_68 -to SDRAM_ADDR[12]
set_location_assignment PIN_101 -to SDRAM_BA[0]
set_location_assignment PIN_100 -to SDRAM_BA[1]
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_119 -to SDRAM_DQM[0]
set_location_assignment PIN_66 -to SDRAM_DQM[1]
set_location_assignment PIN_142 -to SDRAM_DQ[0]
set_location_assignment PIN_141 -to SDRAM_DQ[1]
set_location_assignment PIN_137 -to SDRAM_DQ[2]
set_location_assignment PIN_136 -to SDRAM_DQ[3]
set_location_assignment PIN_135 -to SDRAM_DQ[4]
set_location_assignment PIN_125 -to SDRAM_DQ[5]
set_location_assignment PIN_121 -to SDRAM_DQ[6]
set_location_assignment PIN_120 -to SDRAM_DQ[7]
set_location_assignment PIN_65 -to SDRAM_DQ[8]
set_location_assignment PIN_64 -to SDRAM_DQ[9]
set_location_assignment PIN_60 -to SDRAM_DQ[10]
set_location_assignment PIN_46 -to SDRAM_DQ[11]
set_location_assignment PIN_44 -to SDRAM_DQ[12]
set_location_assignment PIN_59 -to SDRAM_DQ[13]
set_location_assignment PIN_42 -to SDRAM_DQ[14]
set_location_assignment PIN_58 -to SDRAM_DQ[15]
set_location_assignment PIN_106 -to SDRAM_nCAS
set_location_assignment PIN_103 -to SDRAM_nRAS
set_location_assignment PIN_104 -to SDRAM_nWE
#============================================================
# Modules and Files
#============================================================
set_global_assignment -name VHDL_FILE ../ReVerSE_U16_Toplevel.vhd
set_global_assignment -name QIP_FILE Clock_25to100.qip
set_global_assignment -name SDC_FILE ReVerSE_U16_constraints.sdc
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/sdram.qip
#set_global_assignment -name VHDL_FILE ../devices/sysbus/SDRAM/sdram.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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@@ -0,0 +1,165 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.zpu_soc_pkg.all;
entity ReVerSE_U16 is
port (
-- Clock
REVERSEU16_CLOCK: in std_logic;
--
reset_button : in std_logic;
-- LED
--LED : out std_logic_vector(7 downto 0);
-- Debounced keys
--KEY : in std_logic_vector(1 downto 0);
-- DIP switches
--SW : in std_logic_vector(3 downto 0);
-- TDI : in std_logic;
-- TCK : in std_logic;
-- TCS : in std_logic;
-- TDO : out std_logic;
-- I2C_SDAT : inout std_logic;
-- I2C_SCLK : out std_logic;
-- GPIO_0 : inout std_logic_vector(33 downto 0);
-- GPIO_1 : inout std_logic_vector(33 downto 0);
-- SD Card 1
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-- UART Serial channels.
UART_RX_0 : in std_logic;
UART_TX_0 : out std_logic
--UART_RX_1 : in std_logic;
--UART_TX_1 : out std_logic
-- DDR2 DRAM
--DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus
--DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus
--DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus
--DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks
--DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus
--DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks
--DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects.
--DDR2_WE : out std_logic; -- write enable
--DDR2_RAS : out std_logic; -- row address select
--DDR2_CAS : out std_logic; -- columns address select
--DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable.
--DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks.
);
END entity;
architecture rtl of ReVerSE_U16 is
signal reset : std_logic;
signal sysclk : std_logic;
signal memclk : std_logic;
signal pll_locked : std_logic;
--signal ps2m_clk_in : std_logic;
--signal ps2m_clk_out : std_logic;
--signal ps2m_dat_in : std_logic;
--signal ps2m_dat_out : std_logic;
--signal ps2k_clk_in : std_logic;
--signal ps2k_clk_out : std_logic;
--signal ps2k_dat_in : std_logic;
--signal ps2k_dat_out : std_logic;
--alias PS2_MDAT : std_logic is GPIO_1(19);
--alias PS2_MCLK : std_logic is GPIO_1(18);
begin
--I2C_SDAT <= 'Z';
--GPIO_0(33 downto 2) <= (others => 'Z');
--GPIO_1 <= (others => 'Z');
--LED <= "101010" & reset & UART_RX_0;
--LED <= "00000000";
mypll : entity work.Clock_25to100
port map
(
inclk0 => REVERSEU16_CLOCK,
c0 => sysclk,
c1 => memclk,
locked => pll_locked
);
reset <= reset_button or pll_locked;
myVirtualToplevel : entity work.zpu_soc
generic map
(
SYSCLK_FREQUENCY => SYSCLK_E115_FREQ
)
port map
(
SYSCLK => sysclk,
MEMCLK => memclk,
RESET_IN => reset,
-- RS232
UART_RX_0 => UART_RX_0,
UART_TX_0 => UART_TX_0,
UART_RX_1 => '0',
UART_TX_1 => open,
-- SPI signals
SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
SPI_MOSI => open,
SPI_CLK => open,
SPI_CS => open,
-- SD Card (SPI) signals
SDCARD_MISO => SDCARD_MISO,
SDCARD_MOSI => SDCARD_MOSI,
SDCARD_CLK => SDCARD_CLK,
SDCARD_CS => SDCARD_CS,
-- PS/2 signals
PS2K_CLK_IN => '1',
PS2K_DAT_IN => '1',
PS2K_CLK_OUT => open,
PS2K_DAT_OUT => open,
PS2M_CLK_IN => '1',
PS2M_DAT_IN => '1',
PS2M_CLK_OUT => open,
PS2M_DAT_OUT => open,
-- I²C signals
I2C_SCL_IO => open,
I2C_SDA_IO => open,
-- IOCTL Bus --
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
IOCTL_UPLOAD => open, -- Uploading from FPGA.
IOCTL_CLK => open, -- I/O Clock.
IOCTL_WR => open, -- Write Enable to FPGA.
IOCTL_RD => open, -- Read Enable from FPGA.
IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
IOCTL_ADDR => open, -- Address in FPGA to write into.
IOCTL_DOUT => open, -- Data to be written into FPGA.
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-- SDRAM signals which do not exist on the E115
SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
SDRAM_BA => open, --SDRAM_BA, -- two banks
SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
SDRAM_WE_n => open, --SDRAM_WE, -- write enable
SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
SDRAM_READY => open -- sd ready.
);
end architecture;

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@@ -46,10 +46,10 @@ FS_SUBDIRS := falloc fattr fcat fcd fclose fconcat fcp fdel fdir fdrive fdump
FS_SUBDIRS += fmkfs fopen fread frename fsave fseek fshowdir fstat ftime ftrunc fwrite fxtract
DISK_SUBDIRS := ddump dstat
BUFFER_SUBDIRS:= bdump bedit bread bwrite bfill blen
MEM_SUBDIRS := mclear mcopy mdiff mdump meb meh mew mperf mtest
MEM_SUBDIRS := mclear mcopy mdiff mdump meb meh mew mperf msrch mtest
HW_SUBDIRS := hr ht
TST_SUBDIRS := dhry coremark
MISC_SUBDIRS := help time
MISC_SUBDIRS := help time test
SUBDIRS := $(FS_SUBDIRS) $(DISK_SUBDIRS) $(BUFFER_SUBDIRS) $(MEM_SUBDIRS) $(HW_SUBDIRS) $(TST_SUBDIRS) $(MISC_SUBDIRS)
BASEDIR = ../..
TARGETS := all clean install

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@@ -52,6 +52,7 @@
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0

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@@ -52,6 +52,7 @@
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0

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@@ -52,6 +52,7 @@
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0

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@@ -52,6 +52,7 @@
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0

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@@ -52,6 +52,7 @@
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0

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@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

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@@ -52,8 +52,9 @@
#define BUILTIN_MEM_COPY 0
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0

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@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

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@@ -52,6 +52,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

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@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -71,8 +71,10 @@ uint32_t app(uint32_t param1, uint32_t param2)
xputs("Testing RTC & Up/Down Timers\n");
TIMER_MILLISECONDS_UP = 60000;
xputs("Timer Set\n");
while(getserial_nonblocking() == -1)
{
xputs("While loop\n");
if(TIMER_MICROSECONDS_DOWN == 0)
{
TIMER_MICROSECONDS_DOWN = 10000000;

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 1
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 1
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 1
#define BUILTIN_MEM_EDIT_HWORD 0

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 1

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

45
software/apps/msrch/Makefile Executable file
View File

@@ -0,0 +1,45 @@
#########################################################################################################
##
## Name: Makefile
## Created: July 2019
## Author(s): Philip Smart
## Description: App Makefile - Build an App for the ZPU Test Application (zputa)
## This makefile builds an app which is stored on an SD card and called by the ZPUTA
## test application. The app generally is for testing some component where the code is
## not built into ZPUTA or memory restrictions prohibit it being built in.
##
## Credits:
## Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
##
## History: July 2019 - Initial Makefile created for template use.
##
## Notes: Optional component enables:
## USELOADB - The Byte write command is implemented in hw#sw so use it.
## USE_BOOT_ROM - The target is ROM so dont use initialised data.
## MINIMUM_FUNTIONALITY - Minimise functionality to limit code size.
## COREMARK_TEST - Add the CoreMark test suite.
## DHYRSTONE_TEST - Add the Dhrystone test suite.
## USE_SDCARD - Add the SDCard logic.
##
#########################################################################################################
## This source file is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This source file is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
APP_NAME = msrch
APP_DIR = ..
BASEDIR = ../../..
include $(APP_DIR)/Makefile.inc
# Ensure no optimisation is made by GCC as testing memory performance may seem redundant writing and reading the same location so can get optimised away.
CFLAGS = -I. -I$(COMMON_DIR) -I$(FATFS_DIR) -I$(ZPUTADIR) -I$(INCLUDE_DIR) -c -O0 -ffunction-sections -fdata-sections $(ZPUOPTS) -DZPU -DZPUTA_BASEADDR=$(ZPUTA_BASEADDR) -DZPUTA_APPADDR=$(ZPUTA_APPADDR)

98
software/apps/msrch/msrch.c Executable file
View File

@@ -0,0 +1,98 @@
/////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Name: msrch.c
// Created: July 2019
// Author(s): Philip Smart
// Description: Standalone App for the ZPU test application.
// This program implements a loadable appliation which can be loaded from SD card by
// the ZPUTA application. The idea is that commands or programs can be stored on the
// SD card and executed by ZPUTA just like an OS such as Linux. The primary purpose
// is to be able to minimise the size of ZPUTA for applications where minimal ram is
// available.
//
// Credits:
// Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
//
// History: July 2019 - Initial framework creation.
//
// Notes: See Makefile to enable/disable conditional components
//
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// This source file is free software: you can redistribute it and#or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
/////////////////////////////////////////////////////////////////////////////////////////////////////////
#include <zstdio.h>
//#include <stdlib.h>
//#include <string.h>
#include <zpu-types.h>
#include "zpu_soc.h"
//#include "uart.h"
#include "interrupts.h"
#include "ff.h" /* Declarations of FatFs API */
#include "diskio.h"
#include <zstdio.h>
#include <stdlib.h>
#include <string.h>
#include <fcntl.h>
#include <sys/stat.h>
#include "xprintf.h"
#include "utils.h"
#include "zputa_app.h"
#include "msrch.h"
// Utility functions.
#include "tools.c"
// Version info.
#define VERSION "v1.0"
#define VERSION_DATE "30/01/2020"
#define APP_NAME "MSRCH"
// Main entry and start point of a ZPUTA Application. Only 2 parameters are catered for and a 32bit return code, additional parameters can be added by changing the appcrt0.s
// startup code to add them to the stack prior to app() call.
//
// Return code is saved in _memreg by the C compiler, this is transferred to _memreg in ZPUTA in appcrt0.s prior to return.
//
uint32_t app(uint32_t param1, uint32_t param2)
{
// Initialisation.
//
char *ptr = (char *)param1;
long startAddr;
long endAddr;
long bitWidth;
long srchValue;
if (!xatoi(&ptr, &startAddr))
{
xprintf("Illegal <start addr> value.\n");
} else if (!xatoi(&ptr, &endAddr))
{
xprintf("Illegal <end addr> value.\n");
} else if (!xatoi(&ptr, &srchValue))
xprintf("Illegal <value> to search.\n");
else
{
// Optional width
xatoi(&ptr, &bitWidth);
if(bitWidth != 8 && bitWidth != 16 && bitWidth != 32)
{
bitWidth = 32;
}
xputs("Not implemented, please complete code!\n");
}
return(0);
}

108
software/apps/msrch/msrch.h Executable file
View File

@@ -0,0 +1,108 @@
/////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Name: msrch.h
// Created: July 2018
// Author(s): Philip Smart
// Description: Standalone App for the ZPU test application.
//
// Credits:
// Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
//
// History: December 2019 - Initial framework created.
//
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
/////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifndef MSRCH_H
#define MSRCH_H
// Constants.
// Application execution constants.
//
// Components to be embedded in the program.
//
#define BUILTIN_DEFAULT 1
// Disk low level components to be embedded in the program.
#define BUILTIN_DISK_DUMP 0
#define BUILTIN_DISK_STATUS 0
// Disk buffer components to be embedded in the program.
#define BUILTIN_BUFFER_DUMP 0
#define BUILTIN_BUFFER_EDIT 0
#define BUILTIN_BUFFER_READ 0
#define BUILTIN_BUFFER_WRITE 0
#define BUILTIN_BUFFER_FILL 0
#define BUILTIN_BUFFER_LEN 0
// Memory components to be embedded in the program.
#define BUILTIN_MEM_CLEAR 0
#define BUILTIN_MEM_COPY 0
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 1
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0
// Hardware components to be embedded in the program.
#define BUILTIN_HW_SHOW_REGISTER 0
#define BUILTIN_HW_TEST_TIMERS 0
// Filesystem components to be embedded in the program.
#define BUILTIN_FS_STATUS 0
#define BUILTIN_FS_DIRLIST 0
#define BUILTIN_FS_OPEN 0
#define BUILTIN_FS_CLOSE 0
#define BUILTIN_FS_SEEK 0
#define BUILTIN_FS_READ 0
#define BUILTIN_FS_CAT 0
#define BUILTIN_FS_INSPECT 0
#define BUILTIN_FS_WRITE 0
#define BUILTIN_FS_TRUNC 0
#define BUILTIN_FS_RENAME 0
#define BUILTIN_FS_DELETE 0
#define BUILTIN_FS_CREATEDIR 0
#define BUILTIN_FS_ALLOCBLOCK 0
#define BUILTIN_FS_CHANGEATTRIB 0
#define BUILTIN_FS_CHANGETIME 0
#define BUILTIN_FS_COPY 0
#define BUILTIN_FS_CHANGEDIR 0
#define BUILTIN_FS_CHANGEDRIVE 0
#define BUILTIN_FS_SHOWDIR 0
#define BUILTIN_FS_SETLABEL 0
#define BUILTIN_FS_CREATEFS 0
#define BUILTIN_FS_LOAD 0
#define BUILTIN_FS_DUMP 0
#define BUILTIN_FS_CONCAT 0
#define BUILTIN_FS_XTRACT 0
#define BUILTIN_FS_SAVE 0
#define BUILTIN_FS_EXEC 0
// Test components to be embedded in the program.
#define BUILTIN_TST_DHRYSTONE 0
#define BUILTIN_TST_COREMARK 0
// Miscellaneous components to be embedded in this program.
#define BUILTIN_MISC_HELP 0
#define BUILTIN_MISC_SETTIME 0
// Prototypes.
uint32_t app(uint32_t, uint32_t);
// Global scope variables within the ZPUTA memory space.
GLOBALS *G;
SOC_CONFIG *cfgSoC;
// Global scope variables in the app memory space.
volatile UINT Timer; /* Performance timer (100Hz increment) */
#endif // MSRCH_H

View File

@@ -51,6 +51,7 @@
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 1
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0

43
software/apps/test/Makefile Executable file
View File

@@ -0,0 +1,43 @@
#########################################################################################################
##
## Name: Makefile
## Created: July 2019
## Author(s): Philip Smart
## Description: App Makefile - Build an App for the ZPU Test Application (zputa)
## This makefile builds an app which is stored on an SD card and called by the ZPUTA
## test application. The app generally is for testing some component where the code is
## not built into ZPUTA or memory restrictions prohibit it being built in.
##
## Credits:
## Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
##
## History: July 2019 - Initial Makefile created for template use.
##
## Notes: Optional component enables:
## USELOADB - The Byte write command is implemented in hw#sw so use it.
## USE_BOOT_ROM - The target is ROM so dont use initialised data.
## MINIMUM_FUNTIONALITY - Minimise functionality to limit code size.
## COREMARK_TEST - Add the CoreMark test suite.
## DHYRSTONE_TEST - Add the Dhrystone test suite.
## USE_SDCARD - Add the SDCard logic.
##
#########################################################################################################
## This source file is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This source file is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
APP_NAME = test
APP_DIR = ..
BASEDIR = ../../..
CFLAGS = -I. -I$(COMMON_DIR) -I$(FATFS_DIR) -I$(ZPUTADIR) -I$(INCLUDE_DIR) -c -O0 -ffunction-sections -fdata-sections $(ZPUOPTS) -DZPU -DZPUTA_BASEADDR=$(ZPUTA_BASEADDR) -DZPUTA_APPADDR=$(ZPUTA_APPADDR)
include $(APP_DIR)/Makefile.inc

101
software/apps/test/test.c Executable file
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@@ -0,0 +1,101 @@
/////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Name: test.c
// Created: July 2019
// Author(s): Philip Smart
// Description: Standalone App for the ZPU test application.
// This program implements a loadable appliation which can be loaded from SD card by
// the ZPUTA application. The idea is that commands or programs can be stored on the
// SD card and executed by ZPUTA just like an OS such as Linux. The primary purpose
// is to be able to minimise the size of ZPUTA for applications where minimal ram is
// available.
//
// Credits:
// Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
//
// History: January 2020 - Initial framework creation.
//
// Notes: See Makefile to enable/disable conditional components
//
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// This source file is free software: you can redistribute it and#or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
/////////////////////////////////////////////////////////////////////////////////////////////////////////
#include <zstdio.h>
//#include <stdlib.h>
//#include <string.h>
#include <zpu-types.h>
#include "zpu_soc.h"
//#include "uart.h"
#include "interrupts.h"
#include "ff.h" /* Declarations of FatFs API */
#include "diskio.h"
#include <zstdio.h>
#include <stdlib.h>
#include <string.h>
#include <fcntl.h>
#include <sys/stat.h>
#include "xprintf.h"
#include "utils.h"
#include "zputa_app.h"
#include "test.h"
// Utility functions.
#include "tools.c"
// Version info.
#define VERSION "v1.0"
#define VERSION_DATE "23/01/2020"
#define APP_NAME "TEST"
// Main entry and start point of a ZPUTA Application. Only 2 parameters are catered for and a 32bit return code, additional parameters can be added by changing the appcrt0.s
// startup code to add them to the stack prior to app() call.
//
// Return code is saved in _memreg by the C compiler, this is transferred to _memreg in ZPUTA in appcrt0.s prior to return.
//
uint32_t app(uint32_t param1, uint32_t param2)
{
// Initialisation.
//
//uint32_t *pWordArray = malloc(2048);
//uint16_t *pHwordArray = malloc(2048);
//uint8_t *pByteArray = malloc(2048);
static uint32_t wordArray[2048];
static uint16_t hwordArray[2048];
static uint8_t byteArray[2048];
static uint idx;
static uint32_t sum;
xputs("This is a test.\n");
xputs("Print another line.\n");
xprintf("This is another test.\n");
xputs("All done\n");
// These are just memory tests, the main test is in premain where a closer knit write operation of BSS fails, thus trying to debug.
for(idx=0, sum=0; idx < 2048; idx++)
{
sum += wordArray[idx];
}
for(idx=0, sum=0; idx < 2048; idx++)
{
sum += hwordArray[idx];
}
for(idx=0, sum=0; idx < 2048; idx++)
{
sum += byteArray[idx];
}
return(0);
}

108
software/apps/test/test.h Executable file
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@@ -0,0 +1,108 @@
/////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Name: test.h
// Created: July 2018
// Author(s): Philip Smart
// Description: Standalone App for the ZPU test application.
//
// Credits:
// Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
//
// History: January 2020 - Initial framework created.
//
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
/////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifndef TEST_H
#define TEST_H
// Constants.
// Application execution constants.
//
// Components to be embedded in the program.
//
#define BUILTIN_DEFAULT 1
// Disk low level components to be embedded in the program.
#define BUILTIN_DISK_DUMP 0
#define BUILTIN_DISK_STATUS 0
// Disk buffer components to be embedded in the program.
#define BUILTIN_BUFFER_DUMP 0
#define BUILTIN_BUFFER_EDIT 0
#define BUILTIN_BUFFER_READ 0
#define BUILTIN_BUFFER_WRITE 0
#define BUILTIN_BUFFER_FILL 0
#define BUILTIN_BUFFER_LEN 0
// Memory components to be embedded in the program.
#define BUILTIN_MEM_CLEAR 0
#define BUILTIN_MEM_COPY 0
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 0
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 0
#define BUILTIN_MEM_TEST 0
#define BUILTIN_MEM_EDIT_BYTES 0
#define BUILTIN_MEM_EDIT_HWORD 0
#define BUILTIN_MEM_EDIT_WORD 0
// Hardware components to be embedded in the program.
#define BUILTIN_HW_SHOW_REGISTER 1
#define BUILTIN_HW_TEST_TIMERS 0
// Filesystem components to be embedded in the program.
#define BUILTIN_FS_STATUS 0
#define BUILTIN_FS_DIRLIST 0
#define BUILTIN_FS_OPEN 0
#define BUILTIN_FS_CLOSE 0
#define BUILTIN_FS_SEEK 0
#define BUILTIN_FS_READ 0
#define BUILTIN_FS_CAT 0
#define BUILTIN_FS_INSPECT 0
#define BUILTIN_FS_WRITE 0
#define BUILTIN_FS_TRUNC 0
#define BUILTIN_FS_RENAME 0
#define BUILTIN_FS_DELETE 0
#define BUILTIN_FS_CREATEDIR 0
#define BUILTIN_FS_ALLOCBLOCK 0
#define BUILTIN_FS_CHANGEATTRIB 0
#define BUILTIN_FS_CHANGETIME 0
#define BUILTIN_FS_COPY 0
#define BUILTIN_FS_CHANGEDIR 0
#define BUILTIN_FS_CHANGEDRIVE 0
#define BUILTIN_FS_SHOWDIR 0
#define BUILTIN_FS_SETLABEL 0
#define BUILTIN_FS_CREATEFS 0
#define BUILTIN_FS_LOAD 0
#define BUILTIN_FS_DUMP 0
#define BUILTIN_FS_CONCAT 0
#define BUILTIN_FS_XTRACT 0
#define BUILTIN_FS_SAVE 0
#define BUILTIN_FS_EXEC 0
// Test components to be embedded in the program.
#define BUILTIN_TST_DHRYSTONE 0
#define BUILTIN_TST_COREMARK 0
// Miscellaneous components to be embedded in this program.
#define BUILTIN_MISC_HELP 0
#define BUILTIN_MISC_SETTIME 0
// Prototypes.
uint32_t app(uint32_t, uint32_t);
// Global scope variables within the ZPUTA memory space.
GLOBALS *G;
SOC_CONFIG *cfgSoC;
// Global scope variables in the app memory space.
volatile UINT Timer; /* Performance timer (100Hz increment) */
#endif // HR_H

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@@ -80,7 +80,8 @@ extern "C" {
#define CMD_MEM_EDIT_HWORD 66
#define CMD_MEM_EDIT_WORD 67
#define CMD_MEM_PERF 68
#define CMD_MEM_TEST 69
#define CMD_MEM_SRCH 69
#define CMD_MEM_TEST 70
#define CMD_HW_INTR_DISABLE 80 // HW Commands Range 80 .. 99
#define CMD_HW_INTR_ENABLE 81
#define CMD_HW_SHOW_REGISTER 82
@@ -311,6 +312,9 @@ static t_cmdstruct cmdTable[] = {
#if (defined(BUILTIN_MEM_PERF) && BUILTIN_MEM_PERF == 1) || (defined(BUILTIN_MISC_HELP) == 1 && BUILTIN_MISC_HELP == 1)
{ "mperf", BUILTIN_MEM_PERF, CMD_MEM_PERF, CMD_GROUP_MEM },
#endif
#if (defined(BUILTIN_MEM_SRCH) && BUILTIN_MEM_SRCH == 1) || (defined(BUILTIN_MISC_HELP) == 1 && BUILTIN_MISC_HELP == 1)
{ "msrch", BUILTIN_MEM_SRCH, CMD_MEM_SRCH, CMD_GROUP_MEM },
#endif
#if (defined(BUILTIN_MEM_TEST) && BUILTIN_MEM_TEST == 1) || (defined(BUILTIN_MISC_HELP) == 1 && BUILTIN_MISC_HELP == 1)
{ "mtest", BUILTIN_MEM_TEST, CMD_MEM_TEST, CMD_GROUP_MEM },
#endif
@@ -427,6 +431,7 @@ static t_helpstruct helpTable[] = {
{ CMD_MEM_EDIT_HWORD, "<addr> <h-word> [...]", "Edit memory (H-Word)" },
{ CMD_MEM_EDIT_WORD, "<addr> <word> [...]", "Edit memory (Word)" },
{ CMD_MEM_PERF, "<start> <end> [<width>] [<xfersz>]", "Test performance" },
{ CMD_MEM_SRCH, "<start> <end> <value>", "Search memory for value" },
{ CMD_MEM_TEST, "[<start> [<end>] [iter] [tests]]", "Test memory" },
// Hardware commands.
{ CMD_HW_INTR_DISABLE, "", "Disable Interrupts" },

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@@ -233,6 +233,7 @@ int cmdProcessor(void)
char line[120];
uint8_t diskInitialised = 0;
uint8_t fsInitialised = 0;
uint8_t trying = 0;
long p1;
long p2;
long p3;
@@ -923,6 +924,43 @@ int cmdProcessor(void)
break;
#endif
#if defined(BUILTIN_MEM_SRCH) && BUILTIN_MEM_SRCH == 1
// Search memory for first occurrence of a word.
case CMD_MEM_SRCH:
if (!xatoi(&ptr, &p1))
{
if(cfgSoC.implInsnBRAM) { p1 = cfgSoC.addrInsnBRAM; }
else if(cfgSoC.implBRAM) { p1 = cfgSoC.addrBRAM; }
else if(cfgSoC.implRAM) { p1 = cfgSoC.addrRAM; }
else if(cfgSoC.implSDRAM) { p1 = cfgSoC.addrSDRAM; }
else if(cfgSoC.implWBSDRAM) { p1 = cfgSoC.addrWBSDRAM; }
else { p1 = cfgSoC.stackStartAddr - 512; }
}
if (!xatoi(&ptr, &p2))
{
if(cfgSoC.implInsnBRAM) { p2 = cfgSoC.sizeInsnBRAM; }
else if(cfgSoC.implBRAM) { p2 = cfgSoC.sizeBRAM; }
else if(cfgSoC.implRAM) { p2 = cfgSoC.sizeRAM; }
else if(cfgSoC.implSDRAM) { p2 = cfgSoC.sizeSDRAM; }
else if(cfgSoC.implWBSDRAM) { p2 = cfgSoC.sizeWBSDRAM; }
else { p2 = cfgSoC.stackStartAddr + 8; }
}
if (!xatoi(&ptr, &p3))
{
p3 = 0;
}
xputs("Searching..\n");
for(memAddr=p1; memAddr < p2; memAddr+=4)
{
if(*(uint32_t *)(memAddr) == p3)
{
xprintf("%08lx->%08lx\n", memAddr, *(uint32_t *)(memAddr));
}
}
xputs("\n");
break;
#endif
#if defined(BUILTIN_MEM_TEST) && BUILTIN_MEM_TEST == 1
// Test memory, [<start addr> [<end addr>] [<iter>] [<test bitmap>]]
case CMD_MEM_TEST:
@@ -1065,8 +1103,8 @@ int cmdProcessor(void)
#endif
// Test screen
case CMD_MISC_TEST:
break;
//case CMD_MISC_TEST:
// break;
// Configuration information
case CMD_MISC_INFO:
@@ -1084,8 +1122,45 @@ int cmdProcessor(void)
{
// Append the app extension to the command and try to execute.
src1FileName=getStrParam(&ptr);
xsprintf(&line[40], "%d:\\%s\\%s.%s", APP_CMD_BIN_DRIVE, APP_CMD_BIN_DIR, src1FileName, APP_CMD_EXTENSION);
retCode = fileExec(&line[40], APP_CMD_LOAD_ADDR, APP_CMD_EXEC_ADDR, EXEC_MODE_CALL, (uint32_t) ++ptr, 0, (uint32_t)&G, (uint32_t)&cfgSoC);
// The user normally just types the command, but it is possible to type the drive and or path and or extension, so cater
// for these possibilities by trial. An alternate way is to disect the entered command but I think this would take more code space.
trying = 1;
while(trying)
{
switch(trying)
{
// Try formatting with all the required drive and path fields.
case 1:
xsprintf(&line[40], "%d:\\%s\\%s.%s", APP_CMD_BIN_DRIVE, APP_CMD_BIN_DIR, src1FileName, APP_CMD_EXTENSION);
break;
// Try command as is.
case 2:
xsprintf(&line[40], "%s");
break;
// Try command as is but with drive and bin dir.
case 3:
xsprintf(&line[40], "%d:\\%s\\%s", APP_CMD_BIN_DRIVE, APP_CMD_BIN_DIR, src1FileName);
break;
// Try command as is but with just drive.
case 4:
default:
xsprintf(&line[40], "%d:\\%s", APP_CMD_BIN_DRIVE, src1FileName);
break;
}
retCode = fileExec(&line[40], APP_CMD_LOAD_ADDR, APP_CMD_EXEC_ADDR, EXEC_MODE_CALL, (uint32_t) ++ptr, 0, (uint32_t)&G, (uint32_t)&cfgSoC);
if(retCode == 0xffffffff && trying <= 3)
{
trying++;
} else
{
trying = 0;
}
}
}
if(!diskInitialised || !fsInitialised || retCode == 0xffffffff)
{

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@@ -43,7 +43,7 @@
#define BUILTIN_BUFFER_FILL 0
#define BUILTIN_BUFFER_LEN 0
// Memory components to be embedded in the program.
#define BUILTIN_MEM_CLEAR 0
#define BUILTIN_MEM_CLEAR 1
#define BUILTIN_MEM_COPY 0
#define BUILTIN_MEM_DIFF 0
#define BUILTIN_MEM_DUMP 1
@@ -51,6 +51,7 @@
#define BUILTIN_MEM_EDIT_HWORD 1
#define BUILTIN_MEM_EDIT_WORD 1
#define BUILTIN_MEM_PERF 0
#define BUILTIN_MEM_SRCH 1
#define BUILTIN_MEM_TEST 0
// Hardware components to be embedded in the program.
#define BUILTIN_HW_SHOW_REGISTER 0