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@@ -32,31 +32,23 @@
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| A12 <-02--| |--39-> A09 that can stand the test of time |
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| A13 <-03--| |--38-> A08 with no need for major changes. |
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| A14 <-04--| |--37-> A07 |
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| A15 <-05--| |--36-> A06 Everything that is known about the |
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| CLK --06->| |--35-> A05 Z80 is emulated here, including |
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| D4 <-07->| |--34-> A04 the interrupt mode 0, which has |
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| D3 <-08->|.---------.|--33-> A03 not been fully implemented to date |
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| D5 <-09->|| ZILOG ||--32-> A02 in any other known open source Z80 |
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| D6 <-10->|| Z80 ||--31-> A01 emulator. This is, therefore, the |
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| +5V --11--|| CPU ||--30-> A00 first complete and free emulator. |
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| A15 <-05--| |--36-> A06 Some of the main design decisions |
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| CLK --06->| |--35-> A05 have been the following: |
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| D4 <-07->| |--34-> A04 |
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| D3 <-08->|.---------.|--33-> A03 1. Opcode partial decoding keeps |
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| +5V --11--|| CPU ||--30-> A00 the code small and maintainable. |
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| D2 <-12->|| ||--29-- GND |
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| D7 <-13->|'---------'|--28-> RFSH Some of the main design decisions |
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| D0 <-14->| |--27-> M1 have been the following: |
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| D1 <-15->| |<-26-- RESET |
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| INT --16->| |<-25-- BUSREQ 1. The logic of the opcodes has |
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| NMI --17->| |<-24-- WAIT been separated from that of the |
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| HALT <-18--| |--23-> BUSACK arguments to reduce the size of |
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| MREQ <-19--| |--22-> WR the emulator, thus increasing the |
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| IORQ <-20--| |--21-> RD possibility that the CPU loads all |
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| '-----------' its code in the L1 cache. |
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| D7 <-13->|'---------'|--28-> RFSH 2. Function pointer tables for |
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| D0 <-14->| |--27-> M1 opcode selection allow easy reuse |
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| D1 <-15->| |<-26-- RESET of almost all instruction code |
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| INT --16->| |<-25-- BUSREQ in the interrupt mode 0. |
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| NMI --17->| |<-24-- WAIT |
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| HALT <-18--| |--23-> BUSACK 3. Avoiding conditional statements |
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| MREQ <-19--| |--22-> WR as much as possible reduces the |
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| IORQ <-20--| |--21-> RD branch penalty in modern pipelined |
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| '-----------' processors. |
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| Zilog Z80 CPU, May 1976 version |
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| 40-pin ceramic DIP pinout 2. The use of function pointer |
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| tables has been chosen over large |
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| switch statements for opcode selection. This allows easy reuse of almost |
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| all instruction emulation code in the interrupt mode 0. |
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| |
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| 3. Special attention has been given to avoid conditional statements as |
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| much as possible to reduce the branch penalty in pipelined processors. |
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| 40-pin ceramic DIP pinout Manuel |
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| |
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'=============================================================================*/
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