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Extracted a working version from my various dev versions, tested, commented out the STORM and NEO430 Processor sections and all working fine

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Philip Smart
2020-04-30 01:03:10 +01:00
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README.md
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# Sharp MZ Series Personal and Business Computer Emulation
<br>
This project aims to provide full hardware emulation (along with extensions) of the Sharp MZ Series Computers.
Please consult my [GitHub](https://pdsmart.github.io) website for more upto date information, I will update this repository shortly.
The initial version is based on the Terasic DE10 Nano board and hosted under the [MiSTer_Devel](https://github.com/MiSTer_Devel) project using the HPS processor for UI operations. Work is currently under way to embed the ZPU Evo into the design to act as the UI processor such that the emulation can be hosted on different hardware as needed.
Written by Philip Smart, 2018 for the Terasic DE10 Nano board under the MiSTer framework.
The following emulations have been written:
This project aims to provide full emulation (along with extensions) of the Sharp MZ Series Computers.
The following emulations have been written
- MZ80K
- MZ80C
- MZ1200
- MZ80A
- MZ700
- MZ80B
| Emulator | Status | | | Emulator | Status |
| -------- | ------ | --- | -------- | ------ |
| MZ80K | Developed | | | MZ80C | Developed |
| MZ1200 | Developed | | | MZ80A | Developed |
| MZ700 | Developed | | | MZ80B | Developed |
| MZ2000 | Partially Developed | | | MZ800 | Under development |
and the following are under development:
- MZ800
- MZ2000
<br>
The current version of the emulator provides:
- 48K RAM for MZ80K,C,1200,A
- 64K RAM for MZ700, MZ80B
- Hardware Tape Read/Write with selectable 1x - 32x Fast Mode
- Turbo Mode 1x - 32x (ie. 112MHz for MZ700)
- Programmable Character Generator (PCG-8000/PCG-1200)
- 40x25, 80x25 Mono and Colour Display Modes
- 320x200, 640x200 8 Colour Bit addressed Graphics
- Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type.
- i8253 mono audio
| 48K RAM for MZ80K,C,1200,A |
| 64K RAM for MZ700, MZ80B |
| Hardware Tape Read/Write with selectable 1x - 32x Fast Mode |
| APSS Tape Drive for the MZ80B/MZ2000 - Fully automated APSS using the Menu Queue system. |
| Turbo Mode 1x - 32x (ie. 112MHz for MZ700) |
| Programmable Character Generator (PCG-8000/PCG-1200) |
| 40x25, 80x25 Mono and Colour Display Modes |
| 320x200, 640x200 8 Colour Bit addressed Graphics |
| VGA Scaling |
| Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type. |
| i8253 mono audio or Tape audio |
### Enhancements in test/under development:
- Floppy Disk Drive/Controller 5.25"
- Quick Disk Controller
- Dual digital Joystick Input (MZ700)
### Enhancements in test/under development
| Floppy Disk Drive/Controller 5.25" |
| Quick Disk Controller |
| Dual digital Joystick Input (MZ700) |
### Known Issues
- Tape Write isn’t working correctly, I made some structural changes resulting in it no longer working, so this needs to be resolved.
- Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A.
- HDMI needs to be re-enabled in the design.
- The Aspect Ratio/Scandoubler options aren’t working on the VGA output.
| Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A. |
| HDMI needs to be re-enabled in the design. |
| Need to complete the status frame buffer, used by the ZPU I/O processor for status information display - not critical to use. |
## Installation
1. Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide
2. Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:-
scp SharpMZ_MiSTer/releases/SharpMZ_\<date\>.rbf root@\<de10 ip address\>/media/fat/SharpMZ.rbf
Target name can be anything you like ending with .rbf
3. Make a SharpMZ directory on the SD card, ie:
|1. |Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide |
|2. |Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:- |
| |scp SharpMZ_MiSTer/releases/SharpMZ_\<date\>.rbf root@\<de10 ip address\>/media/fat/SharpMZ.rbf |
| |Target name can be anything you like ending with .rbf |
|3. |Make a SharpMZ directory on the SD card, ie: |
| |ssh root@\<de10 ip address\> |
| |mkdir /media/fat/SharpMZ |
|4. |Copy any Rom Files, MZF Tape Files, DSK files across to the new directory, ie: |
| |scp \*.mzf root@\<de10 ip address\>:/media/fat/SharpMZ/ |
|5. |Start the MiSTer menu (ie. press the DE10 reset button if it is not showing). |
|6. |Select the SharpMZ core (or whatever name you called it). |
|7. |The emulator will boot into an MZ80K model with the SP-1002 monitor. |
|8. |Press F12 to change the configuration, select Save Config to store it. |
ssh root@\<de10 ip address\>
mkdir /media/fat/SharpMZ
4. Copy any Rom Files, MZF Tape Files, DSK files across to the new directory, ie:
scp \*.mzf root@\<de10 ip address\>:/media/fat/SharpMZ/
5. Start the MiSTer menu (ie. press the DE10 reset button if it is not showing).
6. Select the SharpMZ core (or whatever name you called it).
7. The emulator will boot into an MZ80K model with the SP-1002 monitor.
8. Press F12 to change the configuration, select Save Config to store it.
## Detail
## Design Detail
### Design Summary
The idea of this design is to keep the emulation as independent of the HPS as possible (so it works standalone), only needing the HPS to set control registers,
read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be
someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone
wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external
SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
### Menu System
The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the display parameters, debugging and access to the MiSTer control menu.
The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the
display parameters, debugging and access to the MiSTer control menu.
### Tape Storage
In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved on to Floppy/Quick Disks.
In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved
on to Floppy/Quick Disks.
This menu controls the hardware CMT unit and has the following choices:
- Load direct to RAM
This option allows you to load an MZF format tape file (ie. 128 bytes header + code) directly into RAM. It uses the Load Address and Size stored in the header in order to correctly locate the code and also stores the header in the Cassette Work area at 10F0H. After load is completed and warm reset is made, the details of the tape are displayed on-screen. In order to run the loaded program, simply issue the correct monitor command, ie. J1200 (Jump to 1200H where 1200H is shown as the Execution Address in the tape summary).
This option allows you to load an MZF format tape file (ie. 128 bytes header + code) directly into RAM. It uses the Load Address and Size stored in the header in order to correctly
locate the code and also stores the header in the Cassette Work area at 10F0H. After load is completed and warm reset is made, the details of the tape are displayed on-screen. In
order to run the loaded program, simply issue the correct monitor command, ie. J1200 (Jump to 1200H where 1200H is shown as the Execution Address in the tape summary).
- Queue Tape
A real cassette has 1 or more programs stored on it sequentially. The emulation cache only stores 1 full program so this is a mechanism to line up multiple programs and they will be fed into the emulation cache as it becomes empty, thus simulating a real cassette.
Selecting this option presents you with a directory listing of all MZF files. Choose one per selection and it will be added to the Queue. The programs queued will be displayed on the menu.
A real cassette has 1 or more programs stored on it sequentially. The emulation cache only stores 1 full program so this is a mechanism to line up multiple programs and they will
be fed into the emulation cache as it becomes empty, thus simulating a real cassette. Selecting this option presents you with a directory listing of all MZF files. Choose one per
selection and it will be added to the Queue. The programs queued will be displayed on the menu.
For the MZ80B/MZ2000, the original tape drive was an automated APSS drive capable of searching backwards and forwards for a program. The queue emulates this by interpreting the
APSS signals, moving the queue forward and backwards as necessary. Thus is you are to use a database program or similar which has multiple volumes you need to add these into the
tape queue for the program to function correctly.
- Clear Queue
This option allows you to purge all queue entries.
- Save Tape
- <s>Save Tape</s>
This option allows you to save a program to the MiSTer SD card which is in the emulation cache. Normally the emulation would have written a program/data to tape (ie. via the BASIC ‘SAVE’ command) which in reality is stored in the emulation cache.
The tape is saved under the name given in the emulation save command (ie. in BASIC ‘SAVE “myfile”’ would result in a file called myfile.mzf being saved).
- Auto Save Tape
<s>This option allows you to save a program to the MiSTer SD card which is in the emulation cache. Normally the emulation would have written a program/data to tape (ie. via the BASIC ‘SAVE’
command) which in reality is stored in the emulation cache. The tape is saved under the name given in the emulation save command (ie. in BASIC ‘SAVE “myfile”’ would result in a file
called myfile.mzf being saved).</s>
- <s>Auto Save Tape</s>
This option allows you to auto save the emulation cache. Ie. when an emulation save completes, a flag is raised which is seen by the MiSTer program and the emulation cache is saved to SD under the name given in the emulation.
- Tape Buttons
<s>This option allows you to auto save the emulation cache. Ie. when an emulation save completes, a flag is raised which is seen by the MiSTer program and the emulation cache is saved to SD under
the name given in the emulation.</s>
- <s>Tape Buttons</s>
This option allows you to set the active Tape buttons, ie. Play, Record or Auto. Auto is a hardware mechanism to detect if the emulation is reading or writing to tape and process accordingly.
<s>This option allows you to set the active Tape buttons, ie. Play, Record or Auto. Auto is a hardware mechanism to detect if the emulation is reading or writing to tape and process accordingly.</s>
- Fast Tape Load
This option allows you to set the speed of the tape drive. On the original machines, the tape runs at 1200baud which is quite slow, so use of this option is recommended.
You can select one of: "Off", "2x", "4x", "8x", "16x", "32x"
You can select one of: "Off", "2x", "4x", "8x", "16x"
Selecting “Off” runs the tape drive at the original speed.
*NB: With the introduction of the APSS functionality, Save Tape and Auto Save Tape are redundant. When a program running on the emulation issues a save, the name is transferred through to the
MiSTer Main binary which then uses that name to create a file on the SD card.*
### Machine
The emulation emulates several Sharp MZ computers and this menu allows you to make selections accordingly.
@@ -168,25 +179,41 @@ The display on the Sharp MZ computers was originally quite simplistic. In order
This option allows you to select the display used. Normally, when a machine model is chosen, it defaults to the original display, this option allows you to override the default. The choices are:
"Mono 40x25", "Mono 80x25 ", "Colour 40x25", "Colour 80x25"
- VGA Scaling
In order to cater for various VGA monitors, this option programs the sync generator to mimic standard VGA signals. As VGA resolution is higher than the original Sharp MZ 40x25 screen (320x200 pixels), scaling occurs from the original format
upto the VGA format. The choices are:
"640x480@60Hz", "Off"
- Video
An extension to the original design was the addition of a graphics frame buffer. It is possible to blend the original display video with the graphics frame buffer. This option allows you to enable or disable the original display video (ie. if you only want graphics).
An extension to the original design was the addition of a graphics frame buffer. It is possible to blend the original display video with the graphics frame buffer. This option allows you to enable or disable the original display video (ie.
if you only want graphics).
- Graphics
There were various add-on boards made available in order to display bit addressable pixel graphics. This is my extension to the original design and as I gather information on other add-on boards, I will adapt the hardware interface so it accommodates these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
There were various add-on boards made available in order to display bit addressable pixel graphics. This is my extension to the original design and as I gather information on other add-on boards, I will adapt the hardware interface so it accommodates
these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
- Graphics Addr
As the emulation is catering for several Sharp MZ models in addition to adding graphics onto machines which originally didnt have graphics there can be a clash of I/O address for selecting the graphics mode and options. This option sets the default
IO address for accessing the graphics control registers.
- VRAM CPU Wait
I deviated from the original design by adding a pixel based display buffer. During the Vertical Blanking period, I expand the character based VRAM and Attribute RAM into pixels and store them in the display buffer (a double buffer technique). This consequently means that no snow/tearing will occur if the CPU accesses the VRAM/Attribute RAM during the visible display period. The original design added software waits (MZ80K) and hardware CPU wait states (MZ80A/700) to eliminate snow/tearing and due to the addition of double buffering, this is no longer needed. You can thus disable the wait states with this option and gain some speed or enable them to keep compatibility.
I deviated from the original design by adding a pixel based display buffer. During the Vertical Blanking period, I expand the character based VRAM and Attribute RAM into pixels and store them in the display buffer (a double buffer technique).
This consequently means that no snow/tearing will occur if the CPU accesses the VRAM/Attribute RAM during the visible display period. The original design added software waits (MZ80K) and hardware CPU wait states (MZ80A/700) to eliminate snow/tearing and
due to the addition of double buffering, this is no longer needed. You can thus disable the wait states with this option and gain some speed or enable them to keep compatibility.
- PCG Mode
All of the Sharp MZ computers used character generators which were hard coded in a ROM. External vendors offered add-ons to allow for a Programmable Character Generator based in RAM. This option enables the Programmable Character Generator which is compatible with the HAL PCG-8000/PCG-1200 add-ons.
- Aspect Ratio
This option is a MiSTer framework extension which converts the Aspect Ratio from 4:3 to 16:9. It doesn’t work at the moment with VGA output but should work on HDMI. Use this option to choose the desired format.
- Scandoubler
This option is a MiSTer framework extension which doubles the scan lines to widen/improve the image of older computer displays. It doesn’t work correctly with VGA output at the moment but should work on HDMI.
The choices are: "None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%"
All of the Sharp MZ computers used character generators which were hard coded in a ROM. External vendors offered add-ons to allow for a Programmable Character Generator based in RAM. This option enables the Programmable Character Generator which is
compatible with the HAL PCG-8000/PCG-1200 add-ons.
- <s>Aspect Ratio</s>
### System
This is the MiSTer main control menu which allows you to select a core, map keys etc.
<s>This option is a MiSTer framework extension which converts the Aspect Ratio from 4:3 to 16:9. It doesn’t work at the moment with VGA output but should work on HDMI. Use this option to choose the desired format.</s>
- <s>Scandoubler</s>
<s>This option is a MiSTer framework extension which doubles the scan lines to widen/improve the image of older computer displays. It doesn’t work correctly with VGA output at the moment but should work on HDMI. The choices are:<br></s>
<s>"None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%"</s>
*NB: Aspect Ratio and Scandoubler are currently disabled due to the inclusion of the VGA Scaling hardware. When HDMI output is compiled into the design in the near future they will be re-enabled.*
### Debugging
*Debugging has now been made a compile time option. If debugging logic has been enabled in the RTL and Main MiSTer binary, the debugging options below will be available.*
As you cannot easily get out a trusty Oscilloscope or write breakpoint/debug messages with an FPGA, I’ve added a debugging mode which can be used at any time without affecting the emulation (unless you choose a debug frequency in which case the emulation will run at the selected frequency).
Basically, the 8 LED’s on the main DE10 main board can display a selectable set of signals, either in auto mode (move from set to set after a fixed period) or a static set. The sample rate of the signals displayed on the LED’s is selectable from the Z80 CPU frequency down to 1Hz. You can also attach an oscilloscope onto the LED’s and thus see the waveform if a simple flicker is not sufficient. In addition, you can slow the CPU frequency down in steps from 1MHz to 1/10Hz so you have a good chance of seeing what is happening internally.
This debugging addition is also a great method of understanding the internals of a computer and seeing the Z80 in action.
@@ -249,6 +276,21 @@ To use the debug mode, press F12 to enter the MiSTer menu, then select Debug and
- MZ80B I => Not yet defined.
- MZ80B II => Not yet defined.
### System
This is the MiSTer main control menu which allows you to select a core, map keys, set bluetooth, view IP address etc.
### Control Options
The menu system presents additional control options whose function is detailed below:
| Option | Description |
| ------ | ----------- |
| Boot Reset | Perform a cold reset on the Emulator, ie. reset the FPGA and the HPS Processor |
| Reset | Reset the emulation, ie. toggle it's reset line. |
| Reload config | Reload the configuration saved previously. Any change made in these menus can be stored for future use, if additional changes are unwanted, use this option to reload your last good configuration. |
| Save config | Save the configuration to SD card. Any changes you made in the Menu system will be saved. |
| Reset config | Reset the configuration to standard defaults. |
### Graphics Frame Buffer
An addition to the original design is a 640x200/320x200 8 colour Graphics frame buffer. There were many additions to the Sharp MZ series to allow graphics (ie. MZ80B comes with standard mono graphics) display and as I don’t have detailed information of these to date, I designed my own extension with the intention of adding hardware abstraction layers at a later date to add compatibility to external vendor add-ons.
@@ -320,17 +362,29 @@ Blend Operator (00=OR ,01=AND, 10=NAND, 11=XOR). Operator to blend Character dis
For Indirect mode (Control Register bits 3/2 set to 11), a write to the Graphics RAM when mapped into CPU address space C000H – FFFFH will see the byte masked by the Red Colour Writer Register and written to the Red Bank with the same operation for Green and Blue. This allows rapid setting of a colour across the 3 banks.
## Credits
My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab and his excellent work.
Also credit to Sorgelig for his hard work in creating the MiSTer framework and design of some excellent hardware add-ons. The MiSTer framework makes it significantly easier to design/port emulations.
## Links
The Sharp MZ Series Computers were not as wide spread as Commodore, Atari or Sinclair but they had a dedicated following. Given their open design it was very easy to modify and extend applications such as the BASIC interpreters and likewise easy to add hardware extension. As such, a look round the web finds some very comprehensive User Groups with invaluable resources. If you need manuals, programs, information then please look (for starters) at the following sites:
- https://www.eaw.app/
- https://original.sharpmz.org/
- https://www.sharpmz.no/
- https://mz-80a.com
- http://www.sharpusersclub.org/
- http://www.scav.cz/uvod.htm (use chrome to auto translate Czech)
## Credits
My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab and his excellent work.
Also credit to Sorgelig for his hard work in creating the MiSTer framework and design of some excellent hardware add-ons. The MiSTer framework makes it significantly easier to design/port emulations.
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. All 3rd party software, to my knowledge and research, is open source and freely useable, if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.
## Licenses
This design, hardware and software, is licensed under the GNU Public Licence v3.
### The Gnu Public License v3
The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.

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---------------------------------------------------------------------------------------------------------
--
-- Name: bridge.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series compatible logic IO Control.
--
-- This module is the IO control layer which provides io services to the emulation,
-- which at time of writing can come from the DE10 Nano HPS or the soft-core STORM
-- or NEO430 microcontroller.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial creation.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.config_pkg.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity bridge is
port(
-------------------- Clock Input ----------------------------
clkmaster : in std_logic; -- Master Clock(50MHz)
clksys : out std_logic; -- System clock.
clkvid : out std_logic; -- Pixel base clock of video.
-------------------- Reset ----------------------------
cold_reset : in std_logic;
warm_reset : in std_logic;
-------------------- main_leds ----------------------------
main_leds : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
ps2_key : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
vga_hb_o : out std_logic; -- VGA Horizontal Blank
vga_vb_o : out std_logic; -- VGA Vertical Blank
vga_hs_o : out std_logic; -- VGA H_SYNC
vga_vs_o : out std_logic; -- VGA V_SYNC
vga_r_o : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
vga_g_o : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
vga_b_o : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
audio_l_o : out std_logic;
audio_r_o : out std_logic;
uart_rx : in std_logic;
uart_tx : out std_logic;
sd_sck : out std_logic;
sd_mosi : out std_logic;
sd_miso : in std_logic;
sd_cs : out std_logic;
sd_cd : out std_logic;
-------------------- HPS Interface ------------------------------
ioctl_download : in std_logic; -- HPS Downloading to FPGA.
ioctl_upload : in std_logic; -- HPS Uploading from FPGA.
ioctl_clk : in std_logic; -- HPS I/O Clock.
ioctl_wr : in std_logic; -- HPS Write Enable to FPGA.
ioctl_rd : in std_logic; -- HPS Read Enable from FPGA.
ioctl_addr : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
ioctl_dout : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
ioctl_din : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS.
);
end bridge;
architecture rtl of bridge is
--
-- Signals.
--
signal CON_CLKMASTER : std_logic;
signal CON_CLKSYS : std_logic;
signal CON_CLKVID : std_logic;
signal CON_CLKIOP : std_logic;
signal CON_COLD_RESET : std_logic;
signal CON_WARM_RESET : std_logic;
signal CON_MAIN_LEDS : std_logic_vector(7 downto 0);
signal CON_PS2_KEY : std_logic_vector(10 downto 0);
signal CON_VGA_HB_O : std_logic;
signal CON_VGA_VB_O : std_logic;
signal CON_VGA_HS_O : std_logic;
signal CON_VGA_VS_O : std_logic;
signal CON_VGA_R_O : std_logic_vector(7 downto 0);
signal CON_VGA_G_O : std_logic_vector(7 downto 0);
signal CON_VGA_B_O : std_logic_vector(7 downto 0);
signal CON_AUDIO_L_O : std_logic;
signal CON_AUDIO_R_O : std_logic;
signal CON_IOCTL_DOWNLOAD : std_logic;
signal CON_IOCTL_UPLOAD : std_logic;
signal CON_IOCTL_CLK : std_logic;
signal CON_IOCTL_WR : std_logic;
signal CON_IOCTL_RD : std_logic;
signal CON_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal CON_IOCTL_DOUT : std_logic_vector(31 downto 0);
signal CON_IOCTL_DIN : std_logic_vector(31 downto 0);
--
-- IO Processor Signals.
--
signal IOP_IOCTL_DOWNLOAD : std_logic;
signal IOP_IOCTL_UPLOAD : std_logic;
signal IOP_IOCTL_CLK : std_logic;
signal IOP_IOCTL_WR : std_logic;
signal IOP_IOCTL_RD : std_logic;
signal IOP_IOCTL_ADDR : std_logic_vector(24 downto 0);
signal IOP_IOCTL_DOUT : std_logic_vector(31 downto 0);
signal IOP_IOCTL_DIN : std_logic_vector(31 downto 0);
signal IOP_IOCTL_SENSE : std_logic;
signal IOP_IOCTL_SELECT : std_logic;
--
--
--
signal CON_UART_TX : std_logic;
signal CON_UART_RX : std_logic;
signal CON_SPI_SCLK : std_logic;
signal CON_SPI_MOSI : std_logic;
signal CON_SPI_MISO : std_logic;
signal CON_SPI_CS : std_logic_vector(7 downto 0);
--
-- Components
--
component sharpmz
port (
-------------------- Clock Input ----------------------------
CLKMASTER : in std_logic; -- Master Clock(50MHz)
CLKSYS : out std_logic; -- System clock.
CLKVID : out std_logic; -- Pixel base clock of video.
CLKIOP : out std_logic; -- IO processor clock.
-------------------- Reset ----------------------------
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
-------------------- main_leds ----------------------------
MAIN_LEDS : out std_logic_vector(7 downto 0); -- main_leds Green[7:0]
-------------------- PS2 ----------------------------
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
-------------------- VGA ----------------------------
VGA_HB_O : out std_logic; -- VGA Horizontal Blank
VGA_VB_O : out std_logic; -- VGA Vertical Blank
VGA_HS_O : out std_logic; -- VGA H_SYNC
VGA_VS_O : out std_logic; -- VGA V_SYNC
VGA_R_O : out std_logic_vector(7 downto 0); -- VGA Red[3:0], [7:4] = 0
VGA_G_O : out std_logic_vector(7 downto 0); -- VGA Green[3:0]
VGA_B_O : out std_logic_vector(7 downto 0); -- VGA Blue[3:0]
-------------------- AUDIO ------------------------------
AUDIO_L_O : out std_logic;
AUDIO_R_O : out std_logic;
-------------------- HPS Interface ------------------------------
IOCTL_DOWNLOAD : in std_logic; -- Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- Uploading from FPGA.
IOCTL_CLK : in std_logic; -- I/O Clock.
IOCTL_WR : in std_logic; -- Write Enable to FPGA.
IOCTL_RD : in std_logic; -- Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0) -- Data to be read into HPS.
);
end component;
--component STORM_SoC
-- port (
-- -- Global Control --
-- CLK_I : in std_logic;
-- RST_I : in std_logic;
--
-- -- General purpose (debug) UART --
-- UART0_RXD_I : in std_logic;
-- UART0_TXD_O : out std_logic;
--
-- -- System Control --
-- START_I : in std_logic; -- low active
-- BOOT_CONFIG_I : in std_logic_vector(03 downto 0); -- low active
-- LED_BAR_O : out std_logic_vector(07 downto 0);
--
-- -- GP Input Pins --
-- GP_INPUT_I : in std_logic_vector(07 downto 0);
--
-- -- GP Output Pins --
-- GP_OUTPUT_O : out std_logic_vector(07 downto 0);
--
-- -- I²C Port --
-- I2C_SCL_IO : inout std_logic;
-- I2C_SDA_IO : inout std_logic;
--
-- -- SPI Port 0 [3 devices] --
-- SPI_P0_CLK_O : out std_logic;
-- SPI_P0_MISO_I : in std_logic;
-- SPI_P0_MOSI_O : out std_logic;
-- SPI_P0_CS_O : out std_logic_vector(02 downto 0);
--
-- -- SPI Port 1 [3 devices] --
-- SPI_P1_CLK_O : out std_logic;
-- SPI_P1_MISO_I : in std_logic;
-- SPI_P1_MOSI_O : out std_logic;
-- SPI_P1_CS_O : out std_logic_vector(02 downto 0);
--
-- -- SPI Port 2 [2 devices] --
-- SPI_P2_CLK_O : out std_logic;
-- SPI_P2_MISO_I : in std_logic;
-- SPI_P2_MOSI_O : out std_logic;
-- SPI_P2_CS_O : out std_logic_vector(01 downto 0);
--
-- -- PWM Port 0 --
---- PWM0_PORT_O : out std_logic_vector(07 downto 0)
--
-- -- IOCTL Bus --
-- IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA.
-- IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA.
-- IOCTL_CLK : out std_logic; -- I/O Clock.
-- IOCTL_WR : out std_logic; -- Write Enable to FPGA.
-- IOCTL_RD : out std_logic; -- Read Enable from FPGA.
-- IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus.
-- IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus.
-- IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
-- IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
-- IOCTL_DIN : in std_logic_vector(31 downto 0) -- Data to be read into HPS.
--
---- -- SDRAM Interface --
---- SDRAM_CLK_O : out std_logic;
---- SDRAM_CSN_O : out std_logic;
---- SDRAM_CKE_O : out std_logic;
---- SDRAM_RASN_O : out std_logic;
---- SDRAM_CASN_O : out std_logic;
---- SDRAM_WEN_O : out std_logic;
---- SDRAM_DQM_O : out std_logic_vector(01 downto 0);
---- SDRAM_BA_O : out std_logic_vector(01 downto 0);
---- SDRAM_ADR_O : out std_logic_vector(11 downto 0);
---- SDRAM_DAT_IO : inout std_logic_vector(15 downto 0)
-- );
--end component;
--
--component neo430
-- generic (
-- -- general configuration --
-- CLOCK_SPEED : natural := 100000000; -- main clock in Hz
-- IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
-- DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- -- additional configuration --
-- USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- -- module configuration --
-- DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
-- MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
-- WB32_USE : boolean := false;-- implement WB32 unit? (default=true)
-- WDT_USE : boolean := true; -- implement WDT? (default=true)
-- GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
-- TIMER_USE : boolean := true; -- implement timer? (default=true)
-- UART_USE : boolean := true; -- implement UART? (default=true)
-- CRC_USE : boolean := true; -- implement CRC unit? (default=true)
-- CFU_USE : boolean := true; -- implement custom functions unit? (default=false)
-- PWM_USE : boolean := true; -- implement PWM controller?
-- TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
-- SPI_USE : boolean := true; -- implement SPI? (default=true)
-- -- boot configuration --
-- BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
-- IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
-- );
-- port (
-- -- global control --
-- clk_i : in std_logic; -- global clock, rising edge
-- rst_i : in std_logic; -- global reset, async, low-active
-- -- gpio --
-- gpio_o : out std_logic_vector(15 downto 0); -- parallel output
-- gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- -- pwm channels --
-- pwm_o : out std_logic_vector(02 downto 0); -- pwm channels
-- -- serial com --
-- uart_txd_o : out std_logic; -- UART send data
-- uart_rxd_i : in std_logic; -- UART receive data
-- spi_sclk_o : out std_logic; -- serial clock line
-- spi_mosi_o : out std_logic; -- serial data line out
-- spi_miso_i : in std_logic; -- serial data line in
-- spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
-- twi_sda_io : inout std_logic; -- twi serial data line
-- twi_scl_io : inout std_logic; -- twi serial clock line
-- -- IOCTL Bus --
-- ioctl_download : out std_logic; -- Downloading to FPGA.
-- ioctl_upload : out std_logic; -- Uploading from FPGA.
-- ioctl_clk : out std_logic; -- I/O Clock.
-- ioctl_wr : out std_logic; -- Write Enable to FPGA.
-- ioctl_rd : out std_logic; -- Read Enable from FPGA.
-- ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus.
-- ioctl_select : out std_logic; -- Enable CFU control over ioctl bus.
-- ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
-- ioctl_dout : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
-- ioctl_din : in std_logic_vector(31 downto 0); -- Data to be read into HPS.
-- -- 32-bit wishbone interface --
-- wb_adr_o : out std_logic_vector(31 downto 0); -- address
-- wb_dat_i : in std_logic_vector(31 downto 0); -- read data
-- wb_dat_o : out std_logic_vector(31 downto 0); -- write data
-- wb_we_o : out std_logic; -- read/write
-- wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
-- wb_stb_o : out std_logic; -- strobe
-- wb_cyc_o : out std_logic; -- valid cycle
-- wb_ack_i : in std_logic; -- transfer acknowledge
-- -- interrupts --
-- irq_i : in std_logic; -- external interrupt request line
-- irq_ack_o : out std_logic -- external interrupt request acknowledge
-- );
--end component;
begin
--
-- Instantiation
--
SHARPMZ_0 : sharpmz
port map (
-------------------- Clock Input ----------------------------
CLKMASTER => CON_CLKMASTER, -- Master Clock(50MHz)
CLKSYS => CON_CLKSYS, -- System clock.
CLKVID => CON_CLKVID, -- Pixel base clock of video.
CLKIOP => CON_CLKIOP, -- IO Processor Clock.
-------------------- ----------------------------
COLD_RESET => CON_COLD_RESET,
WARM_RESET => CON_WARM_RESET,
-------------------- ----------------------------
MAIN_LEDS => CON_MAIN_LEDS, -- main_leds Green[7:0]
-------------------- ----------------------------
PS2_KEY => CON_PS2_KEY, -- PS2 Key data.
-------------------- ----------------------------
VGA_HB_O => CON_VGA_HB_O, -- VGA Horizontal Blank
VGA_VB_O => CON_VGA_VB_O, -- VGA Vertical Blank
VGA_HS_O => CON_VGA_HS_O, -- VGA H_SYNC
VGA_VS_O => CON_VGA_VS_O, -- VGA V_SYNC
VGA_R_O => CON_VGA_R_O, -- VGA Red[3:0], [7:4] = 0
VGA_G_O => CON_VGA_G_O, -- VGA Green[3:0]
VGA_B_O => CON_VGA_B_O, -- VGA Blue[3:0]
-------------------- ------------------------------
AUDIO_L_O => CON_AUDIO_L_O,
AUDIO_R_O => CON_AUDIO_R_O,
-------------------- ------------------------------
IOCTL_DOWNLOAD => CON_IOCTL_DOWNLOAD, -- Downloading to FPGA.
IOCTL_UPLOAD => CON_IOCTL_UPLOAD, -- Uploading from FPGA.
IOCTL_CLK => CON_IOCTL_CLK, -- I/O Clock.
IOCTL_WR => CON_IOCTL_WR, -- Write Enable to FPGA.
IOCTL_RD => CON_IOCTL_RD, -- Read Enable from FPGA.
IOCTL_ADDR => CON_IOCTL_ADDR, -- Address in FPGA to write into.
IOCTL_DOUT => CON_IOCTL_DOUT, -- Data to be written into FPGA.
IOCTL_DIN => CON_IOCTL_DIN -- Data to be read into HPS.
);
-- -- If enabled, instantiate the local STORM IO processor to provide IO and user interface services.
-- --
-- STORM_ENABLED: if STORM_ENABLE = 1 generate
-- STORM_0: STORM_SoC
-- port map (
-- -- Global Control --
-- CLK_I => CON_CLKIOP, -- global clock, rising edge
-- RST_I => (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
--
-- -- General purpose (debug) UART --
-- UART0_RXD_I => CON_UART_RX,
-- UART0_TXD_O => CON_UART_TX,
--
-- -- System Control --
-- START_I => '1',
-- BOOT_CONFIG_I => "0000",
-- LED_BAR_O => open,
--
-- -- GP Input Pins --
-- GP_INPUT_I => x"FF",
--
-- -- GP Output Pins --
-- GP_OUTPUT_O => open,
--
-- -- I²C Port --
-- I2C_SCL_IO => open,
-- I2C_SDA_IO => open,
--
-- -- SPI Port 0 [3 devices] --
-- SPI_P0_CLK_O => CON_SPI_SCLK,
-- SPI_P0_MISO_I => CON_SPI_MISO,
-- SPI_P0_MOSI_O => CON_SPI_MOSI,
-- SPI_P0_CS_O => CON_SPI_CS(2 downto 0),
--
-- -- SPI Port 1 [3 devices] --
-- SPI_P1_CLK_O => open,
-- SPI_P1_MISO_I => '0',
-- SPI_P1_MOSI_O => open,
-- SPI_P1_CS_O => open,
--
-- -- SPI Port 2 [2 devices] --
-- SPI_P2_CLK_O => open,
-- SPI_P2_MISO_I => '0',
-- SPI_P2_MOSI_O => open,
-- SPI_P2_CS_O => open,
--
-- -- PWM Port 0 --
---- PWM0_PORT_O => open
--
-- -- IOCTL Bus --
-- IOCTL_DOWNLOAD => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
-- IOCTL_UPLOAD => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
-- IOCTL_CLK => IOP_IOCTL_CLK, -- I/O Clock.
-- IOCTL_WR => IOP_IOCTL_WR, -- Write Enable to FPGA.
-- IOCTL_RD => IOP_IOCTL_RD, -- Read Enable from FPGA.
-- IOCTL_SENSE => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
-- IOCTL_SELECT => IOP_IOCTL_SELECT, -- Enable IOP control over ioctl bus.
-- IOCTL_ADDR => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
-- IOCTL_DOUT => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
-- IOCTL_DIN => IOP_IOCTL_DIN -- Data to be read into HPS.
--
---- -- SDRAM Interface --
---- SDRAM_CLK_O => open,
---- SDRAM_CSN_O => open,
---- SDRAM_CKE_O => open,
---- SDRAM_RASN_O => open,
---- SDRAM_CASN_O => open,
---- SDRAM_WEN_O => open,
---- SDRAM_DQM_O => open,
---- SDRAM_BA_O => open,
---- SDRAM_ADR_O => open,
---- SDRAM_DAT_IO => open
-- );
-- end generate;
--
-- -- If enabled, instantiate the local IO processor to provide IO and user interface services.
-- --
-- NEO430_ENABLED: if NEO_ENABLE = 1 generate
-- NEO430_0 : neo430
-- generic map (
-- -- general configuration --
-- CLOCK_SPEED => 64000000, -- main clock in Hz
-- IMEM_SIZE => 48*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
-- DMEM_SIZE => 12*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- -- additional configuration --
-- USER_CODE => x"0000", -- custom user code
-- -- module configuration --
-- DADD_USE => true, -- implement DADD instruction? (default=true)
-- MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
-- WB32_USE => false, -- implement WB32 unit? (default=true)
-- WDT_USE => true, -- implement WDT? (default=true)
-- GPIO_USE => true, -- implement GPIO unit? (default=true)
-- TIMER_USE => true, -- implement timer? (default=true)
-- UART_USE => true, -- implement UART? (default=true)
-- CRC_USE => false, -- implement CRC unit? (default=true)
-- CFU_USE => false, -- implement custom functions unit? (default=false)
-- PWM_USE => true, -- implement PWM controller?
-- TWI_USE => false, -- implement two wire serial interface? (default=true)
-- SPI_USE => true, -- implement SPI? (default=true)
-- -- boot configuration --
-- BOOTLD_USE => true, -- implement and use bootloader? (default=true)
-- IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
-- )
-- port map (
-- -- global control --
-- clk_i => CON_CLKIOP, -- global clock, rising edge
-- rst_i => not (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
-- -- gpio --
-- gpio_o => open, -- parallel output
-- gpio_i => X"0000", -- parallel input
-- -- pwm channels --
-- pwm_o => open, -- pwm channels
-- -- serial com --
-- uart_txd_o => CON_UART_TX, -- UART send data
-- uart_rxd_i => CON_UART_RX, -- UART receive data
-- spi_sclk_o => CON_SPI_SCLK, -- serial clock line
-- spi_mosi_o => CON_SPI_MOSI, -- serial data line out
-- spi_miso_i => CON_SPI_MISO, -- serial data line in
-- spi_cs_o => CON_SPI_CS, -- SPI CS 0..7
-- twi_sda_io => open, -- twi serial data line
-- twi_scl_io => open, -- twi serial clock line
-- -- IOCTL Bus --
-- ioctl_download => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
-- ioctl_upload => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
-- ioctl_clk => IOP_IOCTL_CLK, -- I/O Clock.
-- ioctl_wr => IOP_IOCTL_WR, -- Write Enable to FPGA.
-- ioctl_rd => IOP_IOCTL_RD, -- Read Enable from FPGA.
-- ioctl_sense => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
-- ioctl_select => IOP_IOCTL_SELECT, -- Enable CFU control over ioctl bus.
-- ioctl_addr => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
-- ioctl_dout => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
-- ioctl_din => IOP_IOCTL_DIN, -- Data to be read into HPS.
-- -- 32-bit wishbone interface --
-- wb_adr_o => open, -- address
-- wb_dat_i => (others => '0'), -- read data
-- wb_dat_o => open, -- write data
-- wb_we_o => open, -- read/write
-- wb_sel_o => open, -- byte enable
-- wb_stb_o => open, -- strobe
-- wb_cyc_o => open, -- valid cycle
-- wb_ack_i => '0', -- transfer acknowledge
-- -- interrupts --
-- irq_i => '0', -- external interrupt request line
-- irq_ack_o => open -- external interrupt request acknowledge
-- );
-- end generate;
-- -- If the IO Processor is disabled, set the signals to inactive.
-- --
-- IOP_DISABLED: if NEO_ENABLE = 0 and STORM_ENABLE = 0 generate
IOP_IOCTL_DOWNLOAD <= '0';
IOP_IOCTL_UPLOAD <= '0';
IOP_IOCTL_CLK <= '0';
IOP_IOCTL_WR <= '0';
IOP_IOCTL_RD <= '0';
IOP_IOCTL_ADDR <= (others => '0');
IOP_IOCTL_DOUT <= (others => '0');
--IOP_IOCTL_DIN => open;
--IOP_IOCTL_SENSE => open;
IOP_IOCTL_SELECT <= '0';
-- end generate;
-- Assign signals from the emu onto local wires.
--
CON_CLKMASTER <= clkmaster;
clksys <= CON_CLKSYS;
clkvid <= CON_CLKVID;
CON_COLD_RESET <= cold_reset;
CON_WARM_RESET <= warm_reset;
main_leds <= CON_MAIN_LEDS;
CON_PS2_KEY <= ps2_key;
vga_hb_o <= CON_VGA_HB_O;
vga_vb_o <= CON_VGA_VB_O;
vga_hs_o <= CON_VGA_HS_O;
vga_vs_o <= CON_VGA_VS_O;
vga_r_o <= CON_VGA_R_O;
vga_g_o <= CON_VGA_G_O;
vga_b_o <= CON_VGA_B_O;
audio_l_o <= CON_AUDIO_L_O;
audio_r_o <= CON_AUDIO_R_O;
uart_tx <= CON_UART_TX;
CON_UART_RX <= uart_rx;
sd_sck <= CON_SPI_SCLK;
sd_mosi <= CON_SPI_MOSI;
CON_SPI_MISO <= sd_miso;
sd_cs <= CON_SPI_CS(0);
--
-- Multiplexer, default IO control to the HPS unless the IOP is enabled and selects.
-- The IOP first senses to ensure there is no activity on the bus, then takes control
--
CON_IOCTL_DOWNLOAD <= ioctl_download when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_DOWNLOAD;
CON_IOCTL_UPLOAD <= ioctl_upload when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_UPLOAD;
CON_IOCTL_CLK <= ioctl_clk when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_CLK;
CON_IOCTL_WR <= ioctl_wr when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_WR;
CON_IOCTL_RD <= ioctl_rd when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_RD;
CON_IOCTL_ADDR <= ioctl_addr when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_ADDR;
CON_IOCTL_DOUT <= X"0000" & ioctl_dout when IOP_IOCTL_SELECT = '0'
else
IOP_IOCTL_DOUT;
ioctl_din <= CON_IOCTL_DIN(15 downto 0) when IOP_IOCTL_SELECT = '0'
else
(others => '0');
IOP_IOCTL_DIN <= CON_IOCTL_DIN when IOP_IOCTL_SELECT = '1'
else
(others => '0');
IOP_IOCTL_SENSE <= ioctl_download or ioctl_upload or ioctl_wr or ioctl_rd;
end rtl;

4
build_id.v
View File

@@ -1,2 +1,2 @@
`define BUILD_DATE "180928"
`define BUILD_TIME "165433"
`define BUILD_DATE "200430"
`define BUILD_TIME "002036"

4
clean.sh
View File

@@ -32,6 +32,6 @@ rm -f *.cdf
rm -f *.rpt
rm -f new_rtl_netlist
rm -f old_rtl_netlist
rm -f asm/*.obj
rm -f asm/*.sym
rm -f software/asm/*.obj
rm -f software/asm/*.sym
(cd ../Main_MiSTer; make clean)

1479
common/clkgen.vhd
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File diff suppressed because it is too large Load Diff

1615
common/cmt.vhd Normal file
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File diff suppressed because it is too large Load Diff

34
common/config_pkg.vhd Normal file
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@@ -0,0 +1,34 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: config_pkg.vhd
-- Created: July 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series compilation configuration parameters.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: September 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
package config_pkg is
constant DEBUG_ENABLE : integer := 1; -- Enable debug logic,
constant NEO_ENABLE : integer := 0; -- Enable local NEO430 IO processor,
constant STORM_ENABLE : integer := 1; -- Enable local STORM IO processor,
end config_pkg;

65
common/functions.vhd Normal file
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@@ -0,0 +1,65 @@
---------------------------------------------------------------------------------------------------------
--
-- Name: functions.vhd
-- Created: October 2018
-- Author(s): Philip Smart
-- Description: Collection of re-usable functions for the SharpMZ Project.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: October 2018 - Initial module written.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
package functions_pkg is
-- Function to reverse the order of the bits in a standard logic vector.
-- ie. 1010 becomes 0101
function reverse_vector(slv:std_logic_vector) return std_logic_vector;
-- Function to convert an integer (0 or 1) into std_logic.
--
function to_std_logic(i : in integer) return std_logic;
end functions_pkg;
package body functions_pkg is
function reverse_vector(slv:std_logic_vector) return std_logic_vector is
variable target : std_logic_vector(slv'high downto slv'low);
begin
for idx in slv'high downto slv'low loop
target(idx) := slv(slv'low + (slv'high-idx));
end loop;
return target;
end reverse_vector;
function to_std_logic(i : in integer) return std_logic is
begin
if i = 0 then
return '0';
end if;
return '1';
end function;
end functions_pkg;

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---------------------------------------------------------------------------------------------------------
--
-- Name: i8254.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series i8254 Timer
-- This module emulates the Intel i8254 Programmable Interval Timer.
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial write.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i8254 is
Port (
RST : in std_logic;
CLK : in std_logic;
ENA : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
WR_n : in std_logic;
RD_n : in std_logic;
--
CLK0 : in std_logic;
GATE0 : in std_logic;
OUT0 : out std_logic;
CLK1 : in std_logic;
GATE1 : in std_logic;
OUT1 : out std_logic;
CLK2 : in std_logic;
GATE2 : in std_logic;
OUT2 : out std_logic
);
end i8254;
architecture Behavioral of i8254 is
signal WREN : std_logic;
signal RDEN : std_logic;
signal WRCTRLEN : std_logic;
signal WR0 : std_logic;
signal WR1 : std_logic;
signal WR2 : std_logic;
signal RD0 : std_logic;
signal RD1 : std_logic;
signal RD2 : std_logic;
signal DO0 : std_logic_vector(7 downto 0);
signal DO1 : std_logic_vector(7 downto 0);
signal DO2 : std_logic_vector(7 downto 0);
signal LDO0 : std_logic_vector(7 downto 0);
signal LDO1 : std_logic_vector(7 downto 0);
signal LDO2 : std_logic_vector(7 downto 0);
signal READDATA_NEXT : std_logic_vector(7 downto 0);
signal CTRLM0 : std_logic;
signal CTRLM1 : std_logic;
signal CTRLM2 : std_logic;
signal LATCNT0 : std_logic;
signal LATCNT1 : std_logic;
signal LATCNT2 : std_logic;
signal LATSTS0 : std_logic;
signal LATSTS1 : std_logic;
signal LATSTS2 : std_logic;
component i8254_counter
Port (
CLK : in std_logic;
RESET : in std_logic;
--
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
WRITE : in std_logic;
READ : in std_logic;
CTRL_MODE_EN : in std_logic;
LATCH_COUNT_EN : in std_logic;
LATCH_STATUS_EN : in std_logic;
--
CTR_CLK : in std_logic;
CTR_GATE : in std_logic;
CTR_OUT : out std_logic
);
end component;
begin
-- Create signals to select a given register for read or write.
--
WREN <= '1' when ENA = '1' and CS_n = '0' and WR_n = '0'
else '0';
RDEN <= '1' when ENA = '1' and CS_n = '0' and RD_n = '0'
else '0';
WRCTRLEN <= '1' when WREN = '1' and A = "11"
else '0';
WR0 <= '1' when WREN = '1' and A = "00"
else '0';
WR1 <= '1' when WREN = '1' and A = "01"
else '0';
WR2 <= '1' when WREN = '1' and A = "10"
else '0';
RD0 <= '1' when RDEN = '1' and A = "00"
else '0';
RD1 <= '1' when RDEN = '1' and A = "01"
else '0';
RD2 <= '1' when RDEN = '1' and A = "10"
else '0';
-- Create signals to enable setting of a command, a count value or latching status per counter.
--
CTRLM0 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "00" and DI(5 downto 4) /= "00"
else '0';
CTRLM1 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "01" and DI(5 downto 4) /= "00"
else '0';
CTRLM2 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "10" and DI(5 downto 4) /= "00"
else '0';
LATCNT0 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "00" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(1) = '1'))
else '0';
LATCNT1 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "01" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(2) = '1'))
else '0';
LATCNT2 <= '1' when WRCTRLEN = '1' and ((DI(7 downto 6) = "10" and DI(5 downto 4) = "00") or (DI(7 downto 5) = "110" and DI(3) = '1'))
else '0';
LATSTS0 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(1) = '1'
else '0';
LATSTS1 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(2) = '1'
else '0';
LATSTS2 <= '1' when WRCTRLEN = '1' and DI(7 downto 6) = "11" and DI(4) = '0' and DI(3) = '1'
else '0';
-- Assign the counter whose address is active. Not permissible to read back control register.
--
DO <= DO0 when A = "00"
else
DO1 when A = "01"
else
DO2 when A = "10"
else
(others => '0');
-- Instantiate the 3 counters within the 8254.
--
CTR0 : i8254_counter port map (
CLK => CLK,
RESET => RST,
--
DATA_IN => DI,
DATA_OUT => DO0,
WRITE => WR0,
READ => RD0,
CTRL_MODE_EN => CTRLM0,
LATCH_COUNT_EN => LATCNT0,
LATCH_STATUS_EN => LATSTS0,
--
CTR_CLK => CLK0,
CTR_GATE => GATE0,
CTR_OUT => OUT0
);
CTR1 : i8254_counter port map (
CLK => CLK,
RESET => RST,
--
DATA_IN => DI,
DATA_OUT => DO1,
WRITE => WR1,
READ => RD1,
CTRL_MODE_EN => CTRLM1,
LATCH_COUNT_EN => LATCNT1,
LATCH_STATUS_EN => LATSTS1,
--
CTR_CLK => CLK1,
CTR_GATE => GATE1,
CTR_OUT => OUT1
);
CTR2 : i8254_counter port map (
CLK => CLK,
RESET => RST,
--
DATA_IN => DI,
DATA_OUT => DO2,
WRITE => WR2,
READ => RD2,
CTRL_MODE_EN => CTRLM2,
LATCH_COUNT_EN => LATCNT2,
LATCH_STATUS_EN => LATSTS2,
--
CTR_CLK => CLK2,
CTR_GATE => GATE2,
CTR_OUT => OUT2
);
end Behavioral;

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---------------------------------------------------------------------------------------------------------
--
-- Name: i8254_counter.vhd
-- Created: November 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series i8254 Timer
-- This module emulates the Intel i8254 Programmable Interval Timer.
--
-- Credits: Based on Verilog pit_counter by Aleksander Osman, 2014.
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: November 2018 - Initial write.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i8254_counter is
Port (
CLK : in std_logic;
RESET : in std_logic;
--
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
WRITE : in std_logic;
READ : in std_logic;
CTRL_MODE_EN : in std_logic;
LATCH_COUNT_EN : in std_logic;
LATCH_STATUS_EN : in std_logic;
--
CTR_CLK : in std_logic;
CTR_GATE : in std_logic;
CTR_OUT : out std_logic
);
end i8254_counter;
architecture Behavioral of i8254_counter is
subtype LSB is integer range 7 downto 0;
subtype MSB is integer range 15 downto 8;
signal MODE : std_logic_vector(2 downto 0);
signal RW_MODE : std_logic_vector(1 downto 0);
signal BCD : std_logic;
signal REGISTER_IN : std_logic_vector(15 downto 0);
signal REGISTER_OUT : std_logic_vector(15 downto 0);
signal REGISTER_OUT_LATCHED : std_logic;
signal NULL_COUNTER : std_logic;
signal MSB_WRITE : std_logic;
signal MSB_READ : std_logic;
signal STATUS : std_logic_vector(7 downto 0);
signal STATUS_LATCHED : std_logic;
--
signal CLOCK_LAST : std_logic;
signal CLOCK_PULSE : std_logic;
signal GATE_LAST : std_logic;
signal GATE_SAMPLED : std_logic;
signal TRIGGER : std_logic;
signal TRIGGER_SAMPLED : std_logic;
signal WRITTEN : std_logic;
signal LOADED : std_logic;
signal CTR_OUTi : std_logic;
--
signal MODE0 : std_logic;
signal MODE1 : std_logic;
signal MODE2 : std_logic;
signal MODE3 : std_logic;
signal MODE4 : std_logic;
signal MODE5 : std_logic;
signal LOAD : std_logic;
signal LOAD_MODE0 : std_logic;
signal LOAD_MODE1 : std_logic;
signal LOAD_MODE2 : std_logic;
signal LOAD_MODE3 : std_logic;
signal LOAD_MODE4 : std_logic;
signal LOAD_MODE5 : std_logic;
signal LOAD_EVEN : std_logic;
signal ENABLE_MODE0 : std_logic;
signal ENABLE_MODE1 : std_logic;
signal ENABLE_MODE2 : std_logic;
signal ENABLE_MODE3 : std_logic;
signal ENABLE_MODE4 : std_logic;
signal ENABLE_MODE5 : std_logic;
signal ENABLE_DOUBLE : std_logic;
signal ENABLE : std_logic;
signal BCD_DIGIT_1 : std_logic_vector(3 downto 0);
signal BCD_DIGIT_2 : std_logic_vector(3 downto 0);
signal BCD_DIGIT_3 : std_logic_vector(3 downto 0);
signal COUNTER_MINUS_1 : std_logic_vector(15 downto 0);
signal COUNTER_MINUS_2 : std_logic_vector(15 downto 0);
signal COUNTER : std_logic_vector(15 downto 0);
begin
-- Control register settings. A write to the control register sets up the mode of this counter, wether it
-- uses BCD or 16 bit binary and how the data is accessed, ie. LSB, MSB or both.
--
process(RESET, CLK)
begin
if RESET = '1' then
MODE <= "010";
BCD <= '0';
RW_MODE <= "01";
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
MODE <= DATA_IN(3 downto 1);
BCD <= DATA_IN(0);
RW_MODE <= DATA_IN(5 downto 4);
end if;
end if;
end process;
-- Staging counter loading. Depending on the mode, the byte is stored in the LSB, NSB or according to the write flag
-- for 16 bit mode. The staging counter is used to load the main counter.
--
process(RESET, CLK)
begin
if RESET = '1' then
REGISTER_IN <= (others => '0');
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
REGISTER_IN <= (others => '0');
elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '0' then
REGISTER_IN(LSB) <= DATA_IN;
elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '1' then
REGISTER_IN(MSB) <= DATA_IN;
elsif WRITE = '1' and RW_MODE = "01" then
REGISTER_IN(LSB) <= DATA_IN;
elsif WRITE = '1' and RW_MODE = "10" then
REGISTER_IN(MSB) <= DATA_IN;
end if;
end if;
end process;
-- Store the counter contents on every clock until a latch request is made, then we suspend storing
-- until data is read.
--
process(RESET, CLK)
begin
if RESET = '1' then
REGISTER_OUT <= (others => '0');
elsif CLK'event and CLK = '1' then
-- Store each clock cycle, stop on the clock between LATCH going active and REGISTER_OUT_LATCHED going active.
--
if LATCH_COUNT_EN = '1' and REGISTER_OUT_LATCHED = '0' then
REGISTER_OUT <= COUNTER(15 downto 0);
elsif REGISTER_OUT_LATCHED = '0' then
REGISTER_OUT <= COUNTER(15 downto 0);
end if;
end if;
end process;
-- Set the output latched signal if LATCH_COUNT_EN goes high, this will stop the storing of the counter until
-- output latch is cleared, which can be done by a control register access or a 1/2 byte read depending on mode.
--
process(RESET, CLK)
begin
if RESET = '1' then
REGISTER_OUT_LATCHED <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
REGISTER_OUT_LATCHED <= '0';
elsif LATCH_COUNT_EN = '1' then
REGISTER_OUT_LATCHED <= '1';
elsif (READ = '1' and (RW_MODE /= "11" or MSB_READ = '1')) then
REGISTER_OUT_LATCHED <= '0';
end if;
end if;
end process;
-- Status flag null count - indicates if the counter can be read (0) or it is being loaded (1).
--
process(RESET, CLK)
begin
if RESET = '1' then
NULL_COUNTER <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
NULL_COUNTER <= '1';
elsif (WRITE = '1' and (RW_MODE /= "11" or MSB_WRITE = '1')) then
NULL_COUNTER <= '1';
elsif LOAD = '1' then
NULL_COUNTER <= '0';
end if;
end if;
end process;
-- Double byte handling for 16 bit load and fetch. An access to the control register resets the flag,
-- but on each write or read it gets toggled. The flag indicates wether the LSB(0) or MSB(1) is being read or writted.
--
process(RESET, CLK)
begin
if RESET = '1' then
MSB_WRITE <= '0';
MSB_READ <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
MSB_WRITE <= '0';
MSB_READ <= '0';
elsif WRITE = '1' and RW_MODE = "11" then
MSB_WRITE <= not MSB_WRITE;
elsif READ = '1' and RW_MODE = "11" then
MSB_READ <= not MSB_READ;
end if;
end if;
end process;
-- Status register, contains the Output pin value, the state on the counter being read (1 = can be read) and the programmed
-- mode of the counter. The current values are latched during the clock between the LATCH_STATUS_EN going active and the latched
-- signal going active.
--
process(RESET, CLK)
begin
if RESET = '1' then
STATUS <= (others => '0');
elsif CLK'event and CLK = '1' then
if LATCH_STATUS_EN = '1' and STATUS_LATCHED = '0' then
STATUS <= CTR_OUTi & NULL_COUNTER & RW_MODE & MODE & BCD;
end if;
end if;
end process;
-- Set the status latch signal if the LATCH_STATUS_EN goes active. Any read or control mode access resets the flag.
--
process(RESET, CLK)
begin
if RESET = '1' then
STATUS_LATCHED <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
STATUS_LATCHED <= '0';
elsif LATCH_STATUS_EN = '1' then
STATUS_LATCHED <= '1';
elsif READ = '1' then
STATUS_LATCHED <= '0';
end if;
end if;
end process;
-- Set the internal counter signals according to the output clock and gate.
--
process(RESET, CLK)
begin
if RESET = '1' then
CLOCK_PULSE <= '0';
CLOCK_LAST <= '0';
GATE_LAST <= '1';
GATE_SAMPLED <= '0';
TRIGGER <= '0';
TRIGGER_SAMPLED <= '0';
elsif CLK'event and CLK = '1' then
CLOCK_LAST <= CTR_CLK;
GATE_LAST <= CTR_GATE;
if CLOCK_LAST = '1' and CTR_CLK = '0' then
CLOCK_PULSE <= '1';
else
CLOCK_PULSE <= '0';
end if;
if CLOCK_LAST = '0' and CTR_CLK = '1' then
GATE_SAMPLED <= CTR_GATE;
TRIGGER_SAMPLED <= TRIGGER;
end if;
if GATE_LAST = '0' and CTR_GATE = '1' then
TRIGGER <= '1';
elsif CLOCK_LAST = '0' and CTR_CLK = '1' then
TRIGGER <= '0';
end if;
end if;
end process;
-- Set the counter output according to programmed mode and events.
--
process(RESET, CLK)
begin
if RESET = '1' then
CTR_OUTi <= '1';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
if MODE0 = '1' then
CTR_OUTi <= '0';
elsif MODE1 = '1' or MODE2 = '1' or MODE3 = '1' or MODE4 = '1' or MODE5 = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE0 = '1' then
if WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '0' then
CTR_OUTi <= '0';
elsif WRITTEN = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE1 = '1' then
if LOAD = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE2 = '1' then
if CTR_GATE = '0' then
CTR_OUTi <= '1';
elsif COUNTER = "0000000000000010" and ENABLE = '1' then
CTR_OUTi <= '0';
elsif LOAD = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE3 = '1' then
if CTR_GATE = '0' then
CTR_OUTi <= '1';
elsif LOAD = '1' and COUNTER = "000000000000010" and CTR_OUTi = '1' and REGISTER_IN(0) = '0' then
CTR_OUTi <= '0';
elsif LOAD = '1' and COUNTER = "000000000000000" and CTR_OUTi = '1' and REGISTER_IN(0) = '1' then
CTR_OUTi <= '0';
elsif LOAD = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE4 = '1' then
if LOAD = '1' then
CTR_OUTi <= '1';
elsif COUNTER = "0000000000000010" and ENABLE = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
elsif MODE5 = '1' then
if COUNTER = "0000000000000010" and ENABLE = '1' then
CTR_OUTi <= '0';
elsif COUNTER = "0000000000000001" and ENABLE = '1' then
CTR_OUTi <= '1';
end if;
end if;
end if;
end process;
-- Setup flags to indicate if the counter has been written to or loaded. These flags then determine loading operation
-- of the staging counter into the counter.
--
process(RESET, CLK)
begin
if RESET = '1' then
WRITTEN <= '0';
LOADED <= '0';
elsif CLK'event and CLK = '1' then
if CTRL_MODE_EN = '1' then
WRITTEN <= '0';
elsif WRITE = '1' and RW_MODE /= "11" then
WRITTEN <= '1';
elsif WRITE = '1' and RW_MODE = "11" and MSB_WRITE = '1' then
WRITTEN <= '1';
elsif LOAD = '1' then
WRITTEN <= '0';
end if;
if CTRL_MODE_EN = '1' then
LOADED <= '0';
elsif LOAD = '1' then
LOADED <= '1';
end if;
end if;
end process;
-- Process to present the requested data, according to mode, to the uC. The data is latched for timing delay to allow the uC
-- more time to read the byte.
--
process(RESET, CLK)
begin
if RESET = '1' then
DATA_OUT <= (others => '0');
elsif CLK'event and CLK = '1' then
if STATUS_LATCHED = '1' then
DATA_OUT <= STATUS;
elsif RW_MODE = "11" and MSB_READ = '0' then
DATA_OUT <= REGISTER_OUT(LSB);
elsif RW_MODE = "11" and MSB_READ = '1' then
DATA_OUT <= REGISTER_OUT(MSB);
elsif RW_MODE = "01" then
DATA_OUT <= REGISTER_OUT(LSB);
else
DATA_OUT <= REGISTER_OUT(MSB);
end if;
end if;
end process;
-- Load up the primary counter according to the programmed mode and load signals coming from the uC.
--
process(RESET, CLK)
begin
if RESET = '1' then
COUNTER <= (others => '1');
elsif CLK'event and CLK = '1' then
if LOAD_EVEN = '1' then
COUNTER <= REGISTER_IN(15 downto 1) & '0';
elsif LOAD = '1' then
COUNTER <= REGISTER_IN;
elsif ENABLE_DOUBLE = '1' then
COUNTER <= COUNTER_MINUS_2;
elsif ENABLE = '1' then
COUNTER <= COUNTER_MINUS_1;
end if;
end if;
end process;
-- Quick reference signals to indicate programmed mode.
--
MODE0 <= '1' when MODE = "000"
else '0';
MODE1 <= '1' when MODE = "001"
else '0';
MODE2 <= '1' when MODE(1 downto 0) = "10"
else '0';
MODE3 <= '1' when MODE(1 downto 0) = "11"
else '0';
MODE4 <= '1' when MODE = "100"
else '0';
MODE5 <= '1' when MODE = "101"
else '0';
-- Quick reference signals to indicate a load is required for a given mode.
--
LOAD_MODE0 <= '1' when MODE0 = '1' and WRITTEN = '1'
else '0';
LOAD_MODE1 <= '1' when MODE1 = '1' and WRITTEN = '1' and TRIGGER_SAMPLED = '1'
else '0';
LOAD_MODE2 <= '1' when MODE2 = '1' and (WRITTEN = '1' or TRIGGER_SAMPLED = '1' or (LOADED = '1' and GATE_SAMPLED = '1' and COUNTER = "0000000000000001"))
else '0';
LOAD_MODE3 <= '1' when MODE3 = '1' and (WRITTEN = '1' or TRIGGER_SAMPLED = '1' or (LOADED = '1' and GATE_SAMPLED = '1' and ((COUNTER = "0000000000000010" and (REGISTER_IN(0) = '0' or CTR_OUTi = '0')) or (COUNTER = "0000000000000000" and REGISTER_IN(0) = '1' and CTR_OUTi = '1'))))
else '0';
LOAD_MODE4 <= '1' when MODE4 = '1' and WRITTEN = '1'
else '0';
LOAD_MODE5 <= '1' when MODE5 = '1' and (WRITTEN = '1' or LOADED = '1') and TRIGGER_SAMPLED = '1'
else '0';
-- Quick reference signals to indicate a programmed mode can be enabled and set running.
--
ENABLE_MODE0 <= '1' when MODE0 = '1' and GATE_SAMPLED = '1' and MSB_WRITE = '0'
else '0';
ENABLE_MODE1 <= '1' when MODE1 = '1'
else '0';
ENABLE_MODE2 <= '1' when MODE2 = '1' and GATE_SAMPLED = '1'
else '0';
ENABLE_MODE3 <= '1' when MODE3 = '1' and GATE_SAMPLED = '1'
else '0';
ENABLE_MODE4 <= '1' when MODE4 = '1' and GATE_SAMPLED = '1'
else '0';
ENABLE_MODE5 <= '1' when MODE5 = '1'
else '0';
-- Signals to indicate the type of data to be loaded into the primary counter according to programmed mode.
--
LOAD <= '1' when CLOCK_PULSE = '1' and (LOAD_MODE0 = '1' or LOAD_MODE1 = '1' or LOAD_MODE2 = '1' or LOAD_MODE3 = '1' or LOAD_MODE4 = '1' or LOAD_MODE5 = '1')
else '0';
LOAD_EVEN <= '1' when LOAD = '1' and MODE3 = '1'
else '0';
ENABLE <= '1' when LOAD = '0' and LOADED = '1' and CLOCK_PULSE = '1' and (ENABLE_MODE0 = '1' or ENABLE_MODE1 = '1' or ENABLE_MODE2 = '1' or ENABLE_MODE4 = '1' or ENABLE_MODE5 = '1')
else '0';
ENABLE_DOUBLE<= '1' when LOAD = '0' and LOADED = '1' and CLOCK_PULSE = '1' and ENABLE_MODE3 = '1'
else '0';
-- BCD logic. Calculate each digit to ease the main
BCD_DIGIT_3 <= COUNTER(15 downto 12) - X"1";
BCD_DIGIT_2 <= COUNTER(11 downto 8) - X"1";
BCD_DIGIT_1 <= COUNTER(7 downto 4) - X"1";
-- Count down of the primary counter, 1 clock at a time. If we are in BCD mode, adjust count to reflect the BCD value, otherwise make
-- a normal binary countdown.
--
COUNTER_MINUS_1 <= X"9999" when BCD = '1' and COUNTER = X"0000"
else
BCD_DIGIT_3 & X"999" when BCD = '1' and COUNTER(11 downto 0) = X"000"
else
COUNTER(15 downto 12) & BCD_DIGIT_2 & X"99" when BCD = '1' and COUNTER(7 downto 0) = X"00"
else
COUNTER(15 downto 8) & BCD_DIGIT_1 & X"9" when BCD = '1' and COUNTER(3 downto 0) = X"0"
else
COUNTER - X"0001";
-- Count down evenly. Same as above but we count down 2 clocks at a time.
--
COUNTER_MINUS_2 <= X"9998" when BCD = '1' and COUNTER = X"0000"
else
BCD_DIGIT_3 & X"998" when BCD = '1' and COUNTER(11 downto 0) = X"000"
else
COUNTER(15 downto 12) & BCD_DIGIT_2 & X"98" when BCD = '1' and COUNTER(7 downto 0) = X"00"
else
COUNTER(15 downto 8) & BCD_DIGIT_1 & X"8" when BCD = '1' and COUNTER(3 downto 0) = X"0"
else
COUNTER - X"0002";
-- Counter output.
--
CTR_OUT <= CTR_OUTi;
end Behavioral;

1209
common/i8255/i8255.vhd
View File

File diff suppressed because it is too large Load Diff

144
common/keymatrix.vhd
View File

@@ -46,6 +46,7 @@ entity keymatrix is
PA : in std_logic_vector(3 downto 0);
PB : out std_logic_vector(7 downto 0);
STALL : in std_logic;
BREAKDETECT : out std_logic;
-- PS/2 Keyboard Data
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
@@ -63,8 +64,8 @@ entity keymatrix is
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0) -- HPS Data to be read into HPS.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0) -- HPS Data to be read into HPS.
);
end keymatrix;
@@ -100,7 +101,6 @@ signal SCANLL : std_logic_vector(7 downto 0);
signal MTEN : std_logic_vector(3 downto 0);
signal F_KBDT : std_logic_vector(7 downto 0);
signal MAP_DATA : std_logic_vector(7 downto 0);
signal MAP_ADDR : std_logic_vector(7 downto 0);
signal KEY_BANK : std_logic_vector(2 downto 0);
--
@@ -150,13 +150,13 @@ begin
MAP0 : dprom
GENERIC MAP (
--init_file => "./mif/key_80k_80b.mif",
init_file => "./mif/combined_keymap.mif",
--init_file => "./software/mif/key_80k_80b.mif",
init_file => "./software/mif/combined_keymap.mif",
widthad_a => 11,
width_a => 8
)
PORT MAP (
clock_a => CLKBUS(CKCPU),
clock_a => CLKBUS(CKMASTER),
address_a => KEY_BANK & F_KBDT,
-- data_a => IOCTL_DOUT(7 DOWNTO 0),
-- wren_a =>
@@ -170,28 +170,46 @@ begin
);
-- Store changes to the key valid flag in a flip flop.
process( CLKBUS(CKCPU) ) begin
if rising_edge(CLKBUS(CKCPU)) then
KEY_FLAG <= PS2_KEY(10);
process( CLKBUS(CKMASTER) ) begin
if rising_edge(CLKBUS(CKMASTER)) then
if CLKBUS(CKENCPU) = '1' then
KEY_FLAG <= PS2_KEY(10);
end if;
end if;
end process;
KEY_PRESS <= PS2_KEY(9);
KEY_EXTENDED <= PS2_KEY(8);
KEY_VALID <= '1' when KEY_FLAG /= PS2_KEY(10) else '0';
KEY_BANK <= "000" when CONFIG(MZ80K) = '1' else -- Key map for MZ80K
"001" when CONFIG(MZ80C) = '1' else -- Key map for MZ80C
"010" when CONFIG(MZ1200) = '1' else -- Key map for MZ1200
"011" when CONFIG(MZ80A) = '1' else -- Key map for MZ80A
"100" when CONFIG(MZ700) = '1' else -- Key map for MZ700
"101" when CONFIG(MZ800) = '1' else -- Key map for MZ800
"110" when CONFIG(MZ80B) = '1' else -- Key map for MZ80B
"111" when CONFIG(MZ2000) = '1'; -- Key map for MZ2000
-- Set the key mapping to use according to selected machine.
--
process( RST_n, CLKBUS(CKMASTER) ) begin
if RST_n = '0' then
KEY_BANK <= "000";
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
if CLKBUS(CKENCPU) = '1' then
if CONFIG(MZ80K) = '1' then -- Key map for MZ80K
KEY_BANK <= "000";
elsif CONFIG(MZ80C) = '1' then -- Key map for MZ80C
KEY_BANK <= "001";
elsif CONFIG(MZ1200) = '1' then -- Key map for MZ1200
KEY_BANK <= "010";
elsif CONFIG(MZ80A) = '1' then -- Key map for MZ80A
KEY_BANK <= "011";
elsif CONFIG(MZ700) = '1' then -- Key map for MZ700
KEY_BANK <= "100";
elsif CONFIG(MZ800) = '1' then -- Key map for MZ800
KEY_BANK <= "101";
elsif CONFIG(MZ80B) = '1' then -- Key map for MZ80B
KEY_BANK <= "110";
elsif CONFIG(MZ2000) = '1' then -- Key map for MZ2000
KEY_BANK <= "111";
end if;
end if;
end if;
end process;
--
-- Convert
--
process( RST_n, CLKBUS(CKCPU) ) begin
process( RST_n, CLKBUS(CKMASTER) ) begin
if RST_n = '0' then
SCAN00 <= (others=>'0');
SCAN01 <= (others=>'0');
@@ -211,43 +229,44 @@ begin
FLGF0 <= '0';
FLGE0 <= '0';
MTEN <= (others=>'0');
MAP_ADDR <= (others=>'1');
elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='1' then
MTEN <= MTEN(2 downto 0) & KEY_VALID;
if KEY_VALID='1' then
if(KEY_EXTENDED='1') then
FLGE0 <= '1';
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
if CLKBUS(CKENCPU) = '1' then
MTEN <= MTEN(2 downto 0) & KEY_VALID;
if KEY_VALID='1' then
if(KEY_EXTENDED='1') then
FLGE0 <= '1';
end if;
if(KEY_PRESS='0') then
FLGF0 <= '1';
end if;
if(PS2_KEY(7 downto 0) = X"AA" ) then
F_KBDT <= X"EF";
else
F_KBDT <= FLGE0 & PS2_KEY(6 downto 0); FLGE0<='0';
end if;
end if;
if(KEY_PRESS='0') then
FLGF0 <= '1';
if MTEN(3)='1' then
case MAP_DATA(7 downto 4) is
when "0000" => SCAN00(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0001" => SCAN01(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0010" => SCAN02(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0011" => SCAN03(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0100" => SCAN04(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0101" => SCAN05(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0110" => SCAN06(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0111" => SCAN07(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1000" => SCAN08(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1001" => SCAN09(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1010" => SCAN10(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1011" => SCAN11(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1100" => SCAN12(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1101" => SCAN13(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1110" => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0;
when others => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
end case;
end if;
if(PS2_KEY(7 downto 0) = X"AA" ) then
F_KBDT <= X"EF";
else
F_KBDT <= FLGE0 & PS2_KEY(6 downto 0); FLGE0<='0';
end if;
end if;
if MTEN(3)='1' then
case MAP_DATA(7 downto 4) is
when "0000" => SCAN00(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0001" => SCAN01(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0010" => SCAN02(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0011" => SCAN03(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0100" => SCAN04(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0101" => SCAN05(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0110" => SCAN06(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "0111" => SCAN07(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1000" => SCAN08(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1001" => SCAN09(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1010" => SCAN10(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1011" => SCAN11(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1100" => SCAN12(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1101" => SCAN13(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
when "1110" => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0;
when others => SCAN14(conv_integer(MAP_DATA(2 downto 0))) <= not FLGF0; FLGF0 <= '0';
end case;
end if;
end if;
end process;
@@ -277,12 +296,23 @@ begin
(not SCAN12) when PA="1100" else
(not SCAN13) when PA="1101" else (others=>'1');
-- Setup key extension signals to use in mapping.
--
KEY_PRESS <= PS2_KEY(9);
KEY_EXTENDED <= PS2_KEY(8);
KEY_VALID <= '1' when KEY_FLAG /= PS2_KEY(10)
else '0';
-- Break detect is connected to SCAN line 3, bit 7. When the strobe is set to 03H and the break key is pressed
-- this signal will go low and detected in the IPL.
BREAKDETECT <= not SCAN03(7);
--
-- HPS access to reload keymap.
--
IOCTL_KEYMAP_WEN <= '1' when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_WR = '1'
IOCTL_KEYMAP_WEN <= '1' when IOCTL_ADDR(24 downto 16) = "000100011" and IOCTL_WR = '1'
else '0';
IOCTL_DIN <= X"00" & IOCTL_DIN_KEYMAP when IOCTL_ADDR(24 downto 16)="000000011" and IOCTL_RD = '1'
IOCTL_DIN <= X"000000" & IOCTL_DIN_KEYMAP when IOCTL_ADDR(24 downto 16) = "000100011" and IOCTL_RD = '1'
else
(others=>'0');

801
common/mctrl.vhd
View File

@@ -39,7 +39,7 @@ package mctrl_pkg is
-- Config Bus
--
subtype CONFIG_WIDTH is integer range 58 downto 0;
subtype CONFIG_WIDTH is integer range 70 downto 0;
-- Mode signals indicating type of machine we are emulating.
@@ -53,11 +53,11 @@ package mctrl_pkg is
constant MZ80B : integer := 6; -- Machine is an MZ80B
constant MZ2000 : integer := 7; -- Machine is an MZ2000
subtype CURRENTMACHINE is integer range 7 downto 0; -- Range of bits to indicate current machine, only 1 bit is set at a time.
constant MZ_KC : integer := 8; -- Machine is an MZ80K/MZ80C
constant MZ_A : integer := 9; -- Machine is an MZ1200/MZ80A
constant MZ_B : integer := 10; -- Machine is an MZ2000/MZ80B
constant MZ_80B : integer := 11; -- Machine is an MZ2000/MZ80B
constant MZ_80C : integer := 12; -- Machine is an MZ80K/MZ80C/MZ1200/MZ80A
constant MZ_KC : integer := 8; -- Machine is an MZ80K/MZ80C Series
constant MZ_A : integer := 9; -- Machine is an MZ1200/MZ80A Series
constant MZ_B : integer := 10; -- Machine is an MZ2000/MZ80B Series
constant MZ_80B : integer := 11; -- Machine is an MZ2000/MZ80B Series
constant MZ_80C : integer := 12; -- Machine is an MZ80K/MZ80C/MZ1200/MZ80A Series
-- Type of display to emulate.
--
@@ -65,46 +65,71 @@ package mctrl_pkg is
constant NORMAL80 : integer := 14; -- Normal 80 x 25 character monochrome display.
constant COLOUR : integer := 15; -- Colour 40 x 25 character display.
constant COLOUR80 : integer := 16; -- Colour 80 x 25 character display.
subtype VGAMODE is integer range 18 downto 17; -- Output display to 640x400 or 640x480, double up pixels as required.
-- Option Roms Enable (some machines by design dont have them, but this emulation allows them to be enabled if needed).
--
subtype USERROM is integer range 24 downto 17; -- User ROM E800 - EFFF enable per machine.
subtype FDCROM is integer range 32 downto 25; -- FDC ROM F000 - FFFF enable per machine.
subtype USERROM is integer range 26 downto 19; -- User ROM E800 - EFFF enable per machine.
subtype FDCROM is integer range 34 downto 27; -- FDC ROM F000 - FFFF enable per machine.
subtype GRAMIOADDR is integer range 39 downto 35;
-- Various configurable settings.
--
constant AUDIOSRC : integer := 33; -- Audio source, 0 = sound generator, 1 = tape audio.
subtype TURBO is integer range 36 downto 34; -- 2MHz/4MHz/8MHz/16MHz/32MHz switch (various).
subtype FASTTAPE is integer range 39 downto 37; -- Speed of tape read/write.
subtype BUTTONS is integer range 41 downto 40; -- Various external buttons, such as CMT play/record.
constant PCGRAM : integer := 42; -- PCG ROM(0) or RAM(1) based.
constant VRAMWAIT : integer := 43; -- Insert video wait states on CPU access as per original design.
constant VRAMDISABLE : integer := 44; -- Disable the Video RAM from display output.
constant GRAMDISABLE : integer := 45; -- Disable the graphics RAM from display output.
constant AUDIOSRC : integer := 40; -- Audio source, 0 = sound generator, 1 = tape audio.
subtype TURBO is integer range 43 downto 41; -- 2MHz/4MHz/8MHz/16MHz/32MHz switch (various).
subtype FASTTAPE is integer range 46 downto 44; -- Speed of tape read/write.
subtype BUTTONS is integer range 48 downto 47; -- Various external buttons, such as CMT play/record.
constant PCGRAM : integer := 49; -- PCG ROM(0) or RAM(1) based.
constant VRAMWAIT : integer := 50; -- Insert video wait states on CPU access as per original design.
constant VRAMDISABLE : integer := 51; -- Disable the Video RAM from display output.
constant GRAMDISABLE : integer := 52; -- Disable the graphics RAM from display output.
constant MENUENABLE : integer := 53; -- Enable the OSD menu on display output.
constant STATUSENABLE : integer := 54; -- Enable the OSD menu on display output.
constant BOOT_RESET : integer := 55; -- MZ80B/2000 Boot IPL Reset Enable.
constant CMTASCII_IN : integer := 56; -- Enable CMT conversion of Sharp Ascii <-> Ascii on receipt of data from Sharp.
constant CMTASCII_OUT : integer := 57; -- Enable CMT conversion of Sharp Ascii <-> Ascii on sending data to Sharp.
-- Derivative settings to program the clock generator.
--
subtype CPUSPEED is integer range 49 downto 46; -- Active CPU Speed.
subtype VIDSPEED is integer range 52 downto 50; -- Active Video Speed.
subtype PERSPEED is integer range 54 downto 53; -- Active Peripheral Speed.
subtype RTCSPEED is integer range 56 downto 55; -- Active RTC Speed.
subtype SNDSPEED is integer range 58 downto 57; -- Active Sound Speed.
subtype CPUSPEED is integer range 61 downto 58; -- Active CPU Speed.
subtype VIDSPEED is integer range 64 downto 62; -- Active Video Speed.
subtype PERSPEED is integer range 66 downto 65; -- Active Peripheral Speed.
subtype RTCSPEED is integer range 68 downto 67; -- Active RTC Speed.
subtype SNDSPEED is integer range 70 downto 69; -- Active Sound Speed.
-- CMT Bus
--
subtype CMTBUS_WIDTH is integer range 8 downto 0;
subtype CMT_BUS_OUT_WIDTH is integer range 13 downto 0;
subtype CMT_BUS_IN_WIDTH is integer range 7 downto 0;
-- CMT Signals.
-- CMT exported Signals.
--
constant PLAY_READY : integer := 0; -- Tape play back buffer, 0 = empty, 1 = full.
constant PLAYING : integer := 1; -- Tape playback, 0 = stopped, 1 = in progress.
constant RECORD_READY : integer := 2; -- Tape record buffer full.
constant RECORD_READY : integer := 2; -- Tape record buffer full, 0 = empty, 1 = full.
constant RECORDING : integer := 3; -- Tape recording, 0 = stopped, 1 = in progress.
constant ACTIVE : integer := 4; -- Tape transfer in progress, 0 = no activity, 1 = activity.
constant SENSE : integer := 5; -- Tape state Sense out.
constant WRITEBIT : integer := 6; -- Write bit to MZ.
constant READBIT : integer := 7; -- Receive bit from MZ.
constant MOTOR : integer := 8; -- Motor on/off.
constant TAPEREADY : integer := 7; -- Tape is loaded in deck when L = 0.
constant WRITEREADY : integer := 8; -- Write is prohibited when L = 0.
constant APSS_SEEK : integer := 9; -- Start to seek the next program according to APSS_DIR
constant APSS_DIR : integer := 10; -- Direction for APSS Seek, 0 = Rewind, 1 = Forward.
constant APSS_EJECT : integer := 11; -- Eject cassette.
constant APSS_PLAY : integer := 12; -- Play cassette.
constant APSS_STOP : integer := 13; -- Stop playing/rwd/ff of cassette.
-- CMT imported Signals.
--
constant READBIT : integer := 0; -- Receive bit from MZ.
constant REEL_MOTOR : integer := 1; -- APSS Reel Motor on/off.
constant STOP : integer := 2; -- Stop the motor.
constant PLAY : integer := 3; -- Play cassette.
constant SEEK : integer := 4; -- Seek cassette using DIRECTION (L = Rewind, H = FF).
constant DIRECTION : integer := 5; -- Seek direction, L = Rewind, H = Fast Forward.
constant EJECT : integer := 6; -- Eject the cassette.
constant WRITEENABLE : integer := 7; -- Enable writing to cassette.
-- Debug Bus
--
@@ -124,8 +149,10 @@ end mctrl_pkg;
library IEEE;
library pkgs;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use pkgs.config_pkg.all;
use pkgs.mctrl_pkg.all;
use pkgs.clkgen_pkg.all;
@@ -144,14 +171,18 @@ entity mctrl is
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0); -- HPS Data to be read into HPS.
-- Different operations modes.
CONFIG : out std_logic_vector(CONFIG_WIDTH);
-- Cassette magnetic tape signals.
CMTBUS : in std_logic_vector(CMTBUS_WIDTH);
CMT_BUS_OUT : in std_logic_vector(CMT_BUS_OUT_WIDTH);
CMT_BUS_IN : in std_logic_vector(CMT_BUS_IN_WIDTH);
-- MZ80B series can dynamically change the video frequency to attain 40/80 character display.
CONFIG_CHAR80 : in std_logic;
-- Debug modes.
DEBUG : out std_logic_vector(DEBUG_WIDTH)
@@ -162,299 +193,361 @@ architecture rtl of mctrl is
signal REGISTER_MODEL : std_logic_vector(7 downto 0) := "00000011";
signal REGISTER_DISPLAY : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_DISPLAY2 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_DISPLAY3 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CPU : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_AUDIO : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CMT : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_CMT2 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_USERROM : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_FDCROM : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_8 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_9 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_10 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_11 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_12 : std_logic_vector(7 downto 0) := "00000000";
signal REGISTER_13 : std_logic_vector(7 downto 0) := "00000000";
-- REGISTER_13 is a read only configuration, so no register required.
signal REGISTER_DEBUG : std_logic_vector(7 downto 0) := "00001000";
signal REGISTER_DEBUG2 : std_logic_vector(7 downto 0) := "00000000";
signal delay : integer range 0 to 31;
signal REGISTER_RESET : std_logic;
signal delay : integer range 0 to 63;
signal READ_STATUS : std_logic_vector(15 downto 0);
signal RESET_MACHINE : std_logic;
signal CMT_BUS_OUT_LAST : std_logic_vector(CMT_BUS_OUT_WIDTH);
begin
-- Synchronise the register update with the configuration signals according to the CPU clock.
--
process (COLD_RESET, CLKBUS(CKCPU))
process (COLD_RESET, CLKBUS(CKMASTER))
begin
if COLD_RESET = '1' then
CONFIG(CONFIG_WIDTH) <= "00000000000000000000000000000000000000000000011001000001000";
CONFIG(CONFIG_WIDTH) <= "00000000000000000000000000000000011000000000000000000000011001000001000";
DEBUG(DEBUG_WIDTH) <= "0000000000000000";
elsif CLKBUS(CKCPU)'event and CLKBUS(CKCPU)='0' then
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1' then
if REGISTER_MODEL(2 downto 0) = "000" then
CONFIG(MZ80K) <= '1';
else
CONFIG(MZ80K) <= '0';
end if;
if CLKBUS(CKENCPU) = '1' then
if REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ80C) <= '1';
else
CONFIG(MZ80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" then
CONFIG(MZ1200) <= '1';
else
CONFIG(MZ1200) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ80A) <= '1';
else
CONFIG(MZ80A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(MZ700) <= '1';
else
CONFIG(MZ700) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "101" then
CONFIG(MZ800) <= '1';
else
CONFIG(MZ800) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(MZ80B) <= '1';
else
CONFIG(MZ80B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ2000) <= '1';
else
CONFIG(MZ2000) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "000" or REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ_KC) <= '1';
else
CONFIG(MZ_KC) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" or REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ_A) <= '1';
else
CONFIG(MZ_A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_B) <= '1';
else
CONFIG(MZ_B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(MZ_80C) <= '1';
else
CONFIG(MZ_80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_80B) <= '1';
else
CONFIG(MZ_80B) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "000" then
CONFIG(NORMAL) <= '1';
else
CONFIG(NORMAL) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "001" then
CONFIG(NORMAL80) <= '1';
else
CONFIG(NORMAL80) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "010" then
CONFIG(COLOUR) <= '1';
else
CONFIG(COLOUR) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "011" then
CONFIG(COLOUR80) <= '1';
else
CONFIG(COLOUR80) <= '0';
end if;
-- Convert CPU/CMT and Debug speed selections to actual CPU speed.
-- If debugging enabled and Debug freq not 0, select otherwise CMT if CMT is active, otherwise CPU speed as required.
--
-- Mapping could be made in software or 1-1 with the register, but setting restrictions and mapping in hw preferred, it
-- limits frequencies belonging to a given machine and makes it easier to change the frequency by NIOS or other controller if
-- MiSTer not used.
if CMTBUS(ACTIVE) = '1' then
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "1011"; -- 112MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
if REGISTER_MODEL(2 downto 0) = "000" then
CONFIG(MZ80K) <= '1';
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
CONFIG(MZ80K) <= '0';
end if;
else
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "1011"; -- 112MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
if REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ80C) <= '1';
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
CONFIG(MZ80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" then
CONFIG(MZ1200) <= '1';
else
CONFIG(MZ1200) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ80A) <= '1';
else
CONFIG(MZ80A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(MZ700) <= '1';
else
CONFIG(MZ700) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "101" then
CONFIG(MZ800) <= '1';
else
CONFIG(MZ800) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(MZ80B) <= '1';
else
CONFIG(MZ80B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ2000) <= '1';
else
CONFIG(MZ2000) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "000" or REGISTER_MODEL(2 downto 0) = "001" then
CONFIG(MZ_KC) <= '1';
else
CONFIG(MZ_KC) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "010" or REGISTER_MODEL(2 downto 0) = "011" then
CONFIG(MZ_A) <= '1';
else
CONFIG(MZ_A) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_B) <= '1';
else
CONFIG(MZ_B) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(MZ_80C) <= '1';
else
CONFIG(MZ_80C) <= '0';
end if;
if REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(MZ_80B) <= '1';
else
CONFIG(MZ_80B) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "000" then
CONFIG(NORMAL) <= '1';
else
CONFIG(NORMAL) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "001" then
CONFIG(NORMAL80) <= '1';
else
CONFIG(NORMAL80) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "010" then
CONFIG(COLOUR) <= '1';
else
CONFIG(COLOUR) <= '0';
end if;
if REGISTER_DISPLAY(2 downto 0) = "011" then
CONFIG(COLOUR80) <= '1';
else
CONFIG(COLOUR80) <= '0';
end if;
end if;
-- Setup the video speed dependent upon model and graphics option.
--
-- MZ700/MZ800 Models.
if REGISTER_MODEL(2 downto 0) = "100" or REGISTER_MODEL(2 downto 0) = "101" then
-- Currently all modes default to one speed!
case REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8.8MHz clock, Mono and Colour.
when "000" | "010" | "100" | "101" | "110" | "111" =>
CONFIG(VIDSPEED) <= "010";
-- Convert CPU/CMT and Debug speed selections to actual CPU speed.
-- If debugging enabled and Debug freq not 0, select otherwise CMT if CMT is active, otherwise CPU speed as required.
--
-- Mapping could be made in software or 1-1 with the register, but setting restrictions and mapping in hw preferred, it
-- limits frequencies belonging to a given machine and makes it easier to change the frequency by NIOS or other controller if
-- MiSTer not used.
if CMT_BUS_OUT(ACTIVE) = '1' then
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CMT(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
end if;
else
if REGISTER_MODEL /= "100" and REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "001" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "010" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "011" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "100" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "101" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "110" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
when "111" => CONFIG(CPUSPEED) <= "0000"; -- 2MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "100" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "001" => CONFIG(CPUSPEED) <= "0011"; -- 7MHz
when "010" => CONFIG(CPUSPEED) <= "0101"; -- 14MHz
when "011" => CONFIG(CPUSPEED) <= "0111"; -- 28MHz
when "100" => CONFIG(CPUSPEED) <= "1001"; -- 56MHz
when "101" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "110" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
when "111" => CONFIG(CPUSPEED) <= "0001"; -- 3.5MHz
end case;
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "110" then
case REGISTER_CPU(2 downto 0) is
when "000" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "001" => CONFIG(CPUSPEED) <= "0100"; -- 8MHz
when "010" => CONFIG(CPUSPEED) <= "0110"; -- 16MHz
when "011" => CONFIG(CPUSPEED) <= "1000"; -- 32MHz
when "100" => CONFIG(CPUSPEED) <= "1010"; -- 64MHz
when "101" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "110" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
when "111" => CONFIG(CPUSPEED) <= "0010"; -- 4MHz
end case;
else
CONFIG(CPUSPEED) <= "0000"; -- Default 2MHz
end if;
end if;
-- Setup the video speed dependent upon model and graphics option. VGA OUT currently
-- forces all pixel clocks to 25.175MHz, otherwise the original pixel clock is chosen.
--
case REGISTER_MODEL(2 downto 0) is
-- 80x25 mode requires 17.7MHz clock, Mono and Colour.
when "001" | "011" =>
CONFIG(VIDSPEED) <= "011";
-- MZ80K/C/1200/A
when "000" | "001" | "010" | "011" =>
case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8MHz clock, Mono and Colour.
when "11000" | "11010" | "11100" | "11101" | "11110" | "11111" =>
CONFIG(VIDSPEED) <= "000";
-- 80x25 mode requires 16MHz clock, Mono and Colour.
when "11001" | "11011" =>
CONFIG(VIDSPEED) <= "001";
-- VGA Timing 640x480 @ 60Hz
when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
CONFIG(VIDSPEED) <= "100";
-- VGA Timing 640x480 @ 75Hz
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
CONFIG(VIDSPEED) <= "110";
-- VGA Timing 640x480 @ 85Hz
when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
CONFIG(VIDSPEED) <= "111";
end case;
-- MZ700/MZ800 Models.
when "100" | "101" =>
-- Currently all modes default to one speed!
case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8.8MHz clock, Mono and Colour.
when "11000" | "11010" | "11100" | "11101" | "11110" | "11111" =>
CONFIG(VIDSPEED) <= "010";
-- 80x25 mode requires 17.7MHz clock, Mono and Colour.
when "11001" | "11011" =>
CONFIG(VIDSPEED) <= "011";
-- VGA Timing 640x480 @ 60Hz
when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
CONFIG(VIDSPEED) <= "100";
-- VGA Timing 640x480 @ 75Hz
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
CONFIG(VIDSPEED) <= "110";
-- VGA Timing 640x480 @ 85Hz
when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
CONFIG(VIDSPEED) <= "111";
end case;
-- MZ80B or MZ2200
when "110" | "111" =>
case REGISTER_DISPLAY2(1 downto 0) & REGISTER_DISPLAY(2 downto 0) is
-- 80x25 mode requires 16MHz clock, 40x25 requires 8MHz, switched on the CHAR80 signal.
when "11000" | "11001" | "11010" | "11011" | "11100" | "11101" | "11110" | "11111" =>
if CONFIG_CHAR80 = '1' then
CONFIG(VIDSPEED) <= "001";
else
CONFIG(VIDSPEED) <= "000";
end if;
-- VGA Timing 640x480 @ 60Hz
when "01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111" =>
CONFIG(VIDSPEED) <= "100";
-- VGA Timing 640x480 @ 75Hz
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" | "10110" | "10111" =>
CONFIG(VIDSPEED) <= "110";
-- VGA Timing 640x480 @ 85Hz
when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" =>
CONFIG(VIDSPEED) <= "111";
end case;
end case;
-- MZ80K/C/1200/A
elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
case REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 8MHz clock, Mono and Colour.
when "000" | "010" | "100" | "101" | "110" | "111" =>
CONFIG(VIDSPEED) <= "000";
-- 80x25 mode requires 16MHz clock, Mono and Colour.
when "001" | "011" =>
CONFIG(VIDSPEED) <= "001";
end case;
-- MZ80B or MZ2200
elsif REGISTER_MODEL(2 downto 0) = "110" or REGISTER_MODEL(2 downto 0) = "111" then
case REGISTER_DISPLAY(2 downto 0) is
-- 40x25 mode requires 16MHz clock
when "000" | "001" | "010" | "011" | "100" | "101" | "110" | "111" =>
CONFIG(VIDSPEED) <= "001";
end case;
else
CONFIG(VIDSPEED) <= "000";
-- Setup RTC clock frequency dependent upon model.
if REGISTER_MODEL(2 downto 0) = "110" and REGISTER_MODEL(2 downto 0) = "111" then
CONFIG(RTCSPEED) <= "01";
elsif REGISTER_MODEL(2 downto 0) = "100" or REGISTER_MODEL(2 downto 0) = "101" then
CONFIG(RTCSPEED) <= "10";
else
CONFIG(RTCSPEED) <= "00";
end if;
if REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(SNDSPEED) <= "01";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(SNDSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(SNDSPEED) <= "00";
else
CONFIG(SNDSPEED) <= "00";
end if;
-- Setup the peripheral speed.
if REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(PERSPEED) <= "00";
else
CONFIG(PERSPEED) <= "00";
end if;
CONFIG(GRAMIOADDR) <= REGISTER_DISPLAY2(7 downto 3);
CONFIG(VRAMDISABLE) <= REGISTER_DISPLAY(4);
CONFIG(GRAMDISABLE) <= REGISTER_DISPLAY(5);
CONFIG(VRAMWAIT) <= REGISTER_DISPLAY(6);
CONFIG(PCGRAM) <= REGISTER_DISPLAY(7);
CONFIG(VGAMODE) <= REGISTER_DISPLAY2(1 downto 0);
CONFIG(MENUENABLE) <= REGISTER_DISPLAY3(0);
CONFIG(STATUSENABLE) <= REGISTER_DISPLAY3(1);
CONFIG(TURBO) <= REGISTER_CPU(2 downto 0);
CONFIG(FASTTAPE) <= REGISTER_CMT(2 downto 0);
CONFIG(BUTTONS) <= REGISTER_CMT(4 downto 3);
CONFIG(CMTASCII_IN) <= REGISTER_CMT(5);
CONFIG(CMTASCII_OUT) <= REGISTER_CMT(6);
CONFIG(AUDIOSRC) <= REGISTER_AUDIO(0);
CONFIG(USERROM) <= REGISTER_USERROM;
CONFIG(FDCROM) <= REGISTER_FDCROM;
CONFIG(BOOT_RESET) <= REGISTER_CPU(7);
DEBUG(LEDS_BANK) <= REGISTER_DEBUG(2 downto 0);
DEBUG(LEDS_SUBBANK) <= REGISTER_DEBUG(5 downto 3);
DEBUG(LEDS_ON) <= REGISTER_DEBUG(6);
DEBUG(ENABLED) <= REGISTER_DEBUG(7);
DEBUG(SMPFREQ) <= REGISTER_DEBUG2(3 downto 0);
DEBUG(CPUFREQ) <= REGISTER_DEBUG2(7 downto 4);
end if;
-- Setup RTC clock frequency dependent upon model.
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(RTCSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(RTCSPEED) <= "01";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(RTCSPEED) <= "10";
else
CONFIG(RTCSPEED) <= "00";
end if;
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(SNDSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(SNDSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(SNDSPEED) <= "01";
else
CONFIG(SNDSPEED) <= "00";
end if;
-- Setup the peripheral speed.
if REGISTER_MODEL(2 downto 0) /= "110" and REGISTER_MODEL(2 downto 0) /= "111" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "101" or REGISTER_MODEL(2 downto 0) = "110" then
CONFIG(PERSPEED) <= "00";
elsif REGISTER_MODEL(2 downto 0) = "100" then
CONFIG(PERSPEED) <= "00";
else
CONFIG(PERSPEED) <= "00";
end if;
CONFIG(VRAMDISABLE)<= REGISTER_DISPLAY(4);
CONFIG(GRAMDISABLE)<= REGISTER_DISPLAY(5);
CONFIG(VRAMWAIT) <= REGISTER_DISPLAY(6);
CONFIG(PCGRAM) <= REGISTER_DISPLAY(7);
CONFIG(TURBO) <= REGISTER_CPU(2 downto 0);
CONFIG(FASTTAPE) <= REGISTER_CMT(2 downto 0);
CONFIG(BUTTONS) <= REGISTER_CMT(4 downto 3);
CONFIG(AUDIOSRC) <= REGISTER_AUDIO(0);
DEBUG(LEDS_BANK) <= REGISTER_DEBUG(2 downto 0);
DEBUG(LEDS_SUBBANK)<= REGISTER_DEBUG(5 downto 3);
DEBUG(LEDS_ON) <= REGISTER_DEBUG(6);
DEBUG(ENABLED) <= REGISTER_DEBUG(7);
DEBUG(SMPFREQ) <= REGISTER_DEBUG2(3 downto 0);
DEBUG(CPUFREQ) <= REGISTER_DEBUG2(7 downto 4);
end if;
end process;
@@ -468,42 +561,68 @@ begin
if COLD_RESET = '1' then
REGISTER_MODEL <= "00000011";
REGISTER_DISPLAY <= "00000000";
REGISTER_DISPLAY2<= "00000000";
REGISTER_DISPLAY3<= "00000000";
REGISTER_CPU <= "00000000";
REGISTER_AUDIO <= "00000000";
REGISTER_CMT <= "00000000";
REGISTER_CMT2 <= "00000000";
REGISTER_USERROM <= "00000000";
REGISTER_FDCROM <= "00000000";
REGISTER_8 <= "00000000";
REGISTER_9 <= "00000000";
REGISTER_10 <= "00000000";
REGISTER_11 <= "00000000";
REGISTER_12 <= "00000000";
REGISTER_13 <= "00000000";
REGISTER_DEBUG <= "00000000";
REGISTER_DEBUG2 <= "00000000";
REGISTER_RESET <= '1';
READ_STATUS <= (others => '0');
RESET_MACHINE <= '1';
CMT_BUS_OUT_LAST <= (others => '0');
elsif IOCTL_CLK'event and IOCTL_CLK='1' then
-- Reset a register if it has been read, ready for next status change.
--
if READ_STATUS(6) = '1' then
REGISTER_CMT2 <= (others => '0');
end if;
-- CMT Register 2, for bits 0,2,3 & 4, they set an active bit, then upon read it is reset.
--
if CMT_BUS_OUT(APSS_STOP) /= CMT_BUS_OUT_LAST(APSS_STOP) and CMT_BUS_OUT(APSS_STOP) = '1' then
REGISTER_CMT2(4) <= CMT_BUS_OUT(APSS_STOP);
end if;
--if CMT_BUS_OUT(APSS_PLAY) /= CMT_BUS_OUT_LAST(APSS_PLAY) and CMT_BUS_OUT(APSS_PLAY) = '1' then
REGISTER_CMT2(3) <= CMT_BUS_OUT(APSS_PLAY);
--end if;
if CMT_BUS_OUT(APSS_EJECT) /= CMT_BUS_OUT_LAST(APSS_EJECT) and CMT_BUS_OUT(APSS_EJECT) = '1' then
REGISTER_CMT2(2) <= '1';
end if;
REGISTER_CMT2(1) <= CMT_BUS_OUT(APSS_DIR);
if CMT_BUS_OUT(APSS_SEEK) /= CMT_BUS_OUT_LAST(APSS_SEEK) and CMT_BUS_OUT(APSS_SEEK) = '1' then
REGISTER_CMT2(0) <= '1';
end if;
CMT_BUS_OUT_LAST <= CMT_BUS_OUT;
READ_STATUS <= (others => '0');
-- For reading of registers, if no specific signal is required, just read back the output latch.
--
if IOCTL_ADDR(24) = '1' and IOCTL_RD = '1' then
case IOCTL_ADDR(3 downto 0) is
when "0000" => IOCTL_DIN <= X"00" & REGISTER_MODEL;
when "0001" => IOCTL_DIN <= X"00" & REGISTER_DISPLAY;
when "0010" => IOCTL_DIN <= X"00" & REGISTER_CPU;
when "0011" => IOCTL_DIN <= X"00" & REGISTER_AUDIO;
when "0100" => IOCTL_DIN <= X"00" & CMTBUS(7 downto 0);
when "0101" => IOCTL_DIN <= X"00" & REGISTER_CMT2(7 downto 1) & CMTBUS(8 downto 8);
when "0110" => IOCTL_DIN <= X"00" & REGISTER_USERROM;
when "0111" => IOCTL_DIN <= X"00" & REGISTER_FDCROM;
when "1000" => IOCTL_DIN <= X"00" & REGISTER_8;
when "1001" => IOCTL_DIN <= X"00" & REGISTER_9;
when "1010" => IOCTL_DIN <= X"00" & REGISTER_10;
when "1011" => IOCTL_DIN <= X"00" & REGISTER_11;
when "1100" => IOCTL_DIN <= X"00" & REGISTER_12;
when "1101" => IOCTL_DIN <= X"00" & REGISTER_13;
when "1110" => IOCTL_DIN <= X"00" & REGISTER_DEBUG;
when "1111" => IOCTL_DIN <= X"00" & REGISTER_DEBUG2;
when "0000" => IOCTL_DIN <= X"000000" & REGISTER_MODEL; READ_STATUS(0) <= '1';
when "0001" => IOCTL_DIN <= X"000000" & REGISTER_DISPLAY; READ_STATUS(1) <= '1';
when "0010" => IOCTL_DIN <= X"000000" & REGISTER_DISPLAY2; READ_STATUS(2) <= '1';
when "0011" => IOCTL_DIN <= X"000000" & REGISTER_DISPLAY3; READ_STATUS(3) <= '1';
when "0100" => IOCTL_DIN <= X"000000" & REGISTER_CPU; READ_STATUS(4) <= '1';
when "0101" => IOCTL_DIN <= X"000000" & REGISTER_AUDIO; READ_STATUS(5) <= '1';
when "0110" => IOCTL_DIN <= X"000000" & CMT_BUS_OUT(7 downto 0); READ_STATUS(6) <= '1';
when "0111" => IOCTL_DIN <= X"000000" & REGISTER_CMT2; READ_STATUS(7) <= '1';
when "1000" => IOCTL_DIN <= X"000000" & REGISTER_USERROM; READ_STATUS(8) <= '1';
when "1001" => IOCTL_DIN <= X"000000" & REGISTER_FDCROM; READ_STATUS(9) <= '1';
when "1010" => IOCTL_DIN <= X"000000" & REGISTER_10; READ_STATUS(10) <= '1';
when "1011" => IOCTL_DIN <= X"000000" & REGISTER_11; READ_STATUS(11) <= '1';
when "1100" => IOCTL_DIN <= X"000000" & REGISTER_12; READ_STATUS(12) <= '1';
when "1101" => IOCTL_DIN <= X"000000" & "000000" & std_logic_vector(to_unsigned(NEO_ENABLE, 1)) & std_logic_vector(to_unsigned(DEBUG_ENABLE, 1));
when "1110" => IOCTL_DIN <= X"000000" & REGISTER_DEBUG; READ_STATUS(14) <= '1';
when "1111" => IOCTL_DIN <= X"000000" & REGISTER_DEBUG2; READ_STATUS(15) <= '1';
end case;
end if;
-- For writing of registers, just assign the input bus to the register.
@@ -518,28 +637,38 @@ begin
when "100" | "101" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "010";
when "110" | "111" =>
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "000";
REGISTER_DISPLAY <= REGISTER_DISPLAY(7 downto 3) & "001";
end case;
REGISTER_RESET <= '1';
RESET_MACHINE <= '1';
when "0001" =>
REGISTER_DISPLAY <= IOCTL_DOUT(7 downto 0);
-- Reset display if the mode changes.
if REGISTER_DISPLAY(2 downto 0) /= IOCTL_DOUT(2 downto 0) then
REGISTER_RESET <= '1';
RESET_MACHINE <= '1';
end if;
when "0010" => REGISTER_CPU <= IOCTL_DOUT(7 downto 0);
when "0011" => REGISTER_AUDIO <= IOCTL_DOUT(7 downto 0);
when "0100" => REGISTER_CMT <= IOCTL_DOUT(7 downto 0);
when "0101" => REGISTER_CMT2 <= IOCTL_DOUT(7 downto 0);
when "0110" => REGISTER_USERROM <= IOCTL_DOUT(7 downto 0);
when "0111" => REGISTER_FDCROM <= IOCTL_DOUT(7 downto 0);
when "1000" => REGISTER_8 <= IOCTL_DOUT(7 downto 0);
when "1001" => REGISTER_9 <= IOCTL_DOUT(7 downto 0);
when "0010" =>
-- Check the sanity, certain address ranges are blocked by the underlying machine.
--
if IOCTL_DOUT(7 downto 4) /= "1111" and IOCTL_DOUT(7 downto 4) /= "1110" and IOCTL_DOUT(7 downto 4) /= "1101" then
REGISTER_DISPLAY2 <= IOCTL_DOUT(7 downto 0);
end if;
when "0011" => REGISTER_DISPLAY3<= IOCTL_DOUT(7 downto 0);
when "0100" => REGISTER_CPU <= IOCTL_DOUT(7 downto 0);
if REGISTER_CPU(7) = '1' then
RESET_MACHINE<= '1';
end if;
when "0101" => REGISTER_AUDIO <= IOCTL_DOUT(7 downto 0);
when "0110" => REGISTER_CMT <= IOCTL_DOUT(7 downto 0);
when "0111" => REGISTER_CMT2 <= IOCTL_DOUT(7 downto 0);
when "1000" => REGISTER_USERROM <= IOCTL_DOUT(7 downto 0);
when "1001" => REGISTER_FDCROM <= IOCTL_DOUT(7 downto 0);
when "1010" => REGISTER_10 <= IOCTL_DOUT(7 downto 0);
when "1011" => REGISTER_11 <= IOCTL_DOUT(7 downto 0);
when "1100" => REGISTER_12 <= IOCTL_DOUT(7 downto 0);
when "1101" => REGISTER_13 <= IOCTL_DOUT(7 downto 0);
when "1101" => -- Setup register showing configuration, cannot be changed.
when "1110" => REGISTER_DEBUG <= IOCTL_DOUT(7 downto 0);
when "1111" => REGISTER_DEBUG2 <= IOCTL_DOUT(7 downto 0);
end case;
@@ -547,28 +676,28 @@ begin
-- Only allow reset signal to be active for 1 clock cycle, just enough to trigger a system reset.
--
if REGISTER_RESET = '1' then
REGISTER_RESET <= '0';
if RESET_MACHINE = '1' then
RESET_MACHINE <= '0';
end if;
end if;
end process;
-- System reset oneshot, triggered on COLD/WARM reset or a status change.
process (CLKBUS(CKRESET), COLD_RESET, WARM_RESET, REGISTER_RESET)
process (CLKBUS(CKMASTER), COLD_RESET, WARM_RESET, RESET_MACHINE)
begin
if COLD_RESET = '1' or WARM_RESET = '1' or REGISTER_RESET = '1' then
if COLD_RESET = '1' or WARM_RESET = '1' or RESET_MACHINE = '1' then
if COLD_RESET = '1' then
delay <= 1;
delay <= 15;
elsif WARM_RESET = '1' then
delay <= 16;
delay <= 31;
else
delay <= 16;
delay <= 31;
end if;
elsif CLKBUS(CKRESET)'event and CLKBUS(CKRESET) = '1' then
elsif CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER) = '1' then
if delay /= 0 then
delay <= delay + 1;
elsif delay >= 31 then
elsif delay >= 63 then
delay <= 0;
end if;
end if;

1318
common/pll.qip
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common/spi_master.vhd Normal file
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@@ -0,0 +1,172 @@
--------------------------------------------------------------------------------
--
-- FileName: spi_master.vhd
-- Dependencies: none
-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 7/23/2010 Scott Larson
-- Initial Public Release
-- Version 1.1 4/11/2013 Scott Larson
-- Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY spi_master IS
GENERIC(
slaves : INTEGER := 4; --number of spi slaves
d_width : INTEGER := 2); --data bus width
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
enable : IN STD_LOGIC; --initiate transaction
cpol : IN STD_LOGIC; --spi clock polarity
cpha : IN STD_LOGIC; --spi clock phase
cont : IN STD_LOGIC; --continuous mode command
clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
addr : IN INTEGER; --address of slave
tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
miso : IN STD_LOGIC; --master in, slave out
sclk : BUFFER STD_LOGIC; --spi clock
ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
mosi : OUT STD_LOGIC; --master out, slave in
busy : OUT STD_LOGIC; --busy / data ready signal
rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
END spi_master;
ARCHITECTURE logic OF spi_master IS
TYPE machine IS(ready, execute); --state machine data type
SIGNAL state : machine; --current state
SIGNAL slave : INTEGER; --slave selected for current transaction
SIGNAL clk_ratio : INTEGER; --current clk_div
SIGNAL count : INTEGER; --counter to trigger sclk from system clock
SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1; --count spi clock toggles
SIGNAL assert_data : STD_LOGIC; --'1' is tx sclk toggle, '0' is rx sclk toggle
SIGNAL continue : STD_LOGIC; --flag to continue transaction
SIGNAL rx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
SIGNAL tx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2; --last rx data bit location
BEGIN
PROCESS(clock, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset system
busy <= '1'; --set busy signal
ss_n <= (OTHERS => '1'); --deassert all slave select lines
mosi <= '0'; --set master out to high impedance
rx_data <= (OTHERS => '0'); --clear receive data port
state <= ready; --go to ready state when reset is exited
ELSIF(clock'EVENT AND clock = '1') THEN
CASE state IS --state machine
WHEN ready =>
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave select outputs high
mosi <= '0'; --set mosi output high impedance
continue <= '0'; --clear continue flag
--user input to initiate transaction
IF(enable = '1') THEN
busy <= '1'; --set busy signal
IF(addr < slaves) THEN --check for valid slave address
slave <= addr; --clock in current slave selection if valid
ELSE
slave <= 0; --set to first slave if not valid
END IF;
IF(clk_div = 0) THEN --check for valid spi speed
clk_ratio <= 1; --set to maximum speed if zero
count <= 1; --initiate system-to-spi clock counter
ELSE
clk_ratio <= clk_div; --set to input selection if valid
count <= clk_div; --initiate system-to-spi clock counter
END IF;
sclk <= cpol; --set spi clock polarity
assert_data <= NOT cpha; --set spi clock phase
tx_buffer <= tx_data; --clock in data for transmit into buffer
clk_toggles <= 0; --initiate clock toggle counter
last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
state <= execute; --proceed to execute state
ELSE
state <= ready; --remain in ready state
END IF;
WHEN execute =>
busy <= '1'; --set busy signal
ss_n(slave) <= '0'; --set proper slave select output
--system clock to sclk ratio is met
IF(count = clk_ratio) THEN
count <= 1; --reset system-to-spi clock counter
assert_data <= NOT assert_data; --switch transmit/receive indicator
IF(clk_toggles = d_width*2 + 1) THEN
clk_toggles <= 0; --reset spi clock toggles counter
ELSE
clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
END IF;
--spi clock toggle needed
IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN
sclk <= NOT sclk; --toggle spi clock
END IF;
--receive spi clock toggle
IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN
rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
END IF;
--transmit spi clock toggle
IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN
mosi <= tx_buffer(d_width-1); --clock out data bit
tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
END IF;
--last data receive, but continue
IF(clk_toggles = last_bit_rx AND cont = '1') THEN
tx_buffer <= tx_data; --reload transmit buffer
clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
continue <= '1'; --set continue flag
END IF;
--normal end of transaction, but continue
IF(continue = '1') THEN
continue <= '0'; --clear continue flag
busy <= '0'; --clock out signal that first receive data is ready
rx_data <= rx_buffer; --clock out received data to output port
END IF;
--end of transaction
IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave selects high
mosi <= '0'; --set mosi output high impedance
rx_data <= rx_buffer; --clock out received data to output port
state <= ready; --return to ready state
ELSE --not end of transaction
state <= execute; --remain in execute state
END IF;
ELSE --system clock to sclk ratio not met
count <= count + 1; --increment counter
state <= execute; --remain in execute state
END IF;
END CASE;
END IF;
END PROCESS;
END logic;

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common/z8420/Interrupt.vhd Normal file
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@@ -0,0 +1,125 @@
--
-- Interrupt.vhd
--
-- Z80 Daisy-Chain Interrupt Logic for FPGA
--
-- Nibbles Lab. 2013-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Interrupt is
Port (
-- System Signal
RESET : in std_logic;
-- CPU Signals
DI : in std_logic_vector(7 downto 0);
IORQ_n : in std_logic; -- same as Z80
RD_n : in std_logic; -- same as Z80
M1_n : in std_logic; -- same as Z80
IEI : in std_logic; -- same as Z80
IEO : out std_logic; -- same as Z80
INTO_n : out std_logic;
-- Control Signals
VECTEN : out std_logic;
INTI : in std_logic;
INTEN : in std_logic
);
end Interrupt;
architecture Behavioral of Interrupt is
-----------------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------------
signal IREQ : std_logic;
signal IRES : std_logic;
signal INTR : std_logic;
signal IAUTH : std_logic;
signal AUTHRES : std_logic;
signal IED1 : std_logic;
signal IED2 : std_logic;
signal ICB : std_logic;
signal I4D : std_logic;
signal FETCH : std_logic;
signal INTA : std_logic;
signal IENB : std_logic;
signal iINT : std_logic;
signal iIEO : std_logic;
begin
--
-- External signals
--
INTO_n <= iINT;
IEO <= iIEO;
--
-- Internal signals
--
iINT <= '0' when IEI='1' and IREQ='1' and IAUTH='0' else '1';
iIEO <= not (((not IED1) and IREQ) or IAUTH or (not IEI));
INTA <= ((not M1_n) and (not IORQ_n) and IEI);
AUTHRES <= RESET or (IEI and IED2 and I4D);
FETCH <= M1_n or RD_n;
IRES <= RESET or INTA;
INTR <= M1_n and (INTI and INTEN);
VECTEN <= '1' when INTA='1' and IEI='1' and IAUTH='1' else '0';
--
-- Keep Interrupt Request
--
process( IRES, INTR ) begin
if IRES='1' then
IREQ <= '0';
elsif INTR'event and INTR='1' then
IREQ <= '1';
end if;
end process;
--
-- Interrupt Authentication
--
process( AUTHRES, INTA ) begin
if AUTHRES='1' then
IAUTH <= '0';
elsif INTA'event and INTA='1' then
IAUTH <= IREQ;
end if;
end process;
--
-- Fetch 'RETI'
--
process( RESET, FETCH ) begin
if RESET='1' then
IED1 <= '0';
IED2 <= '0';
ICB <= '0';
I4D <= '0';
elsif FETCH'event and FETCH='1' then
IED2 <= IED1;
if DI=X"ED" and ICB='0' then
IED1 <= '1';
else
IED1 <= '0';
end if;
if DI=X"CB" then
ICB <= '1';
else
ICB <= '0';
end if;
if DI=X"4D" then
I4D <= IEI;
else
I4D <= '0';
end if;
end if;
end process;
end Behavioral;

246
common/z8420/z8420.vhd Normal file
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@@ -0,0 +1,246 @@
--
-- z8420.vhd
--
-- Zilog Z80PIO partiality compatible module
-- for MZ-80B on FPGA
--
-- Port A : Output, mode 0 only
-- Port B : Input, mode 0 only
--
-- Nibbles Lab. 2005-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity z8420 is
Port (
-- System
RST_n : in std_logic; -- Only Power On Reset
-- Z80 Bus Signals
CLK : in std_logic;
ENA : in std_logic;
BASEL : in std_logic;
CDSEL : in std_logic;
CE : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
IORQ_n : in std_logic;
M1_n : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
IEI : in std_logic;
IEO : out std_logic;
INT_n : out std_logic;
-- Port
A : out std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0)
);
end z8420;
architecture Behavioral of z8420 is
--
-- Port Selecter
--
signal SELAD : std_logic;
signal SELBD : std_logic;
signal SELAC : std_logic;
signal SELBC : std_logic;
--
-- Port Register
--
signal AREG : std_logic_vector(7 downto 0); -- Output Register (Port A)
signal DIRA : std_logic_vector(7 downto 0); -- Data Direction (Port A)
signal DDWA : std_logic; -- Prepare for Data Direction (Port A)
signal IMWA : std_logic_vector(7 downto 0); -- Interrupt Mask Word (Port A)
signal MFA : std_logic; -- Mask Follows (Port A)
signal VECTA : std_logic_vector(7 downto 0); -- Interrupt Vector (Port A)
signal MODEA : std_logic_vector(1 downto 0); -- Mode Word (Port A)
signal HLA : std_logic; -- High/Low (Port A)
signal AOA : std_logic; -- AND/OR (Port A)
signal DIRB : std_logic_vector(7 downto 0); -- Data Direction (Port B)
signal DDWB : std_logic; -- Prepare for Data Direction (Port B)
signal IMWB : std_logic_vector(7 downto 0); -- Interrupt Mask Word (Port B)
signal MFB : std_logic; -- Mask Follows (Port B)
signal VECTB : std_logic_vector(7 downto 0); -- Interrupt Vector (Port B)
signal MODEB : std_logic_vector(1 downto 0); -- Mode Word (Port B)
signal HLB : std_logic; -- High/Low (Port B)
signal AOB : std_logic; -- AND/OR (Port B)
--
-- Interrupt
--
--signal VECTENA : std_logic;
signal EIA : std_logic; -- Interrupt Enable (Port A)
--signal MINTA : std_logic_vector(7 downto 0);
--signal INTA : std_logic;
signal VECTENB : std_logic;
signal EIB : std_logic; -- Interrupt Enable (Port B)
signal MINTB : std_logic_vector(7 downto 0);
signal INTB : std_logic;
--
-- Components
--
component Interrupt is
Port (
-- System Signal
RESET : in std_logic;
-- CPU Signals
DI : in std_logic_vector(7 downto 0);
IORQ_n : in std_logic; -- same as Z80
RD_n : in std_logic; -- same as Z80
M1_n : in std_logic; -- same as Z80
IEI : in std_logic; -- same as Z80
IEO : out std_logic; -- same as Z80
INTO_n : out std_logic;
-- Control Signals
VECTEN : out std_logic;
INTI : in std_logic;
INTEN : in std_logic
);
end component;
begin
--
-- Instantiation
--
-- INT0 : Interrupt port map (
-- -- System Signal
-- RESET => RST_n,
-- -- CPU Signals
-- IORQ_n => IORQ_n,
-- RD_n => RD_n,
-- M1_n => M1_n,
-- IEI => IEI,
-- IEO => IEO,
-- INTO_n => INTA_n,
-- -- Control Signals
-- VECTEN => VECTENA,
-- INTI => INTA,
-- INTEN => EIA
-- );
INT1 : Interrupt port map (
-- System Signal
RESET => RST_n,
-- CPU Signals
DI => DI,
IORQ_n => IORQ_n,
RD_n => RD_n,
M1_n => M1_n,
IEI => IEI,
IEO => IEO,
INTO_n => INT_n, --INTB_n,
-- Control Signals
VECTEN => VECTENB,
INTI => INTB,
INTEN => EIB
);
--
-- Port select for Output
--
SELAD <= '1' when BASEL='0' and CDSEL='0' else '0';
SELBD <= '1' when BASEL='1' and CDSEL='0' else '0';
SELAC <= '1' when BASEL='0' and CDSEL='1' else '0';
SELBC <= '1' when BASEL='1' and CDSEL='1' else '0';
--
-- Output
--
process( RST_n, CLK, ENA ) begin
if RST_n='0' then
AREG <= (others=>'0');
MODEA <= "01";
DDWA <= '0';
MFA <= '0';
EIA <= '0';
-- B<=(others=>'0');
MODEB <= "01";
DDWB <= '0';
MFB <= '0';
EIB <= '0';
elsif CLK'event and CLK='0' then
if ENA = '1' then
if CE='0' and WR_n='0' then
if SELAD='1' then
AREG <=DI;
end if;
-- if SELBD='1' then
-- B<=DI;
-- end if;
if SELAC='1' then
if DDWA='1' then
DIRA <=DI;
DDWA <='0';
elsif MFA='1' then
IMWA <=DI;
MFA <='0';
elsif DI(0)='0' then
VECTA <=DI;
elsif DI(3 downto 0)="1111" then
MODEA <=DI(7 downto 6);
DDWA <=DI(7) and DI(6);
elsif DI(3 downto 0)="0111" then
MFA <=DI(4);
HLA <=DI(5);
AOA <=DI(6);
EIA <=DI(7);
elsif DI(3 downto 0)="0011" then
EIA <=DI(7);
end if;
end if;
if SELBC='1' then
if DDWB='1' then
DIRB <=DI;
DDWB <='0';
elsif MFB='1' then
IMWB <=DI;
MFB <='0';
elsif DI(0)='0' then
VECTB <=DI;
elsif DI(3 downto 0)="1111" then
MODEB <=DI(7 downto 6);
DDWB <=DI(7) and DI(6);
elsif DI(3 downto 0)="0111" then
MFB <=DI(4);
HLB <=DI(5);
AOB <=DI(6);
EIB <=DI(7);
elsif DI(3 downto 0)="0011" then
EIB <=DI(7);
end if;
end if;
end if;
end if;
end if;
end process;
A<=AREG;
--
-- Input select
--
DO<=AREG when RD_n='0' and CE='0' and SELAD='1' else
B when RD_n='0' and CE='0' and SELBD='1' else
-- VECTA when VECTENA='1' else
VECTB when VECTENB='1' else (others=>'0');
--
-- Interrupt select
--
INTMASK : for I in 0 to 7 generate
-- MINTA(I)<=(A(I) xnor HLA) and (not IMWA(I)) when AOA='0' else
-- (A(I) xnor HLA) or IMWA(I);
MINTB(I)<=(B(I) xnor HLB) and (not IMWB(I)) when AOB='0' else
(B(I) xnor HLB) or IMWB(I);
end generate INTMASK;
-- INTA<=MINTA(7) or MINTA(6) or MINTA(5) or MINTA(4) or MINTA(3) or MINTA(2) or MINTA(1) or MINTA(0) when AOA='0' else
-- MINTA(7) and MINTA(6) and MINTA(5) and MINTA(4) and MINTA(3) and MINTA(2) and MINTA(1) and MINTA(0);
INTB<=MINTB(7) or MINTB(6) or MINTB(5) or MINTB(4) or MINTB(3) or MINTB(2) or MINTB(1) or MINTB(0) when AOB='0' else
MINTB(7) and MINTB(6) and MINTB(5) and MINTB(4) and MINTB(3) and MINTB(2) and MINTB(1) and MINTB(0);
end Behavioral;

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<br>
This project aims to provide full hardware emulation (along with extensions) of the Sharp MZ Series Computers.
The initial version is based on the Terasic DE10 Nano board and hosted under the [MiSTer_Devel](https://github.com/MiSTer_Devel) project using the HPS processor for UI operations. Work is currently under way to embed the ZPU Evo into the design to act as the UI processor such that the emulation can be hosted on different hardware as needed.
The following emulations have been written:
| Emulator | Status | | | Emulator | Status |
| -------- | ------ | --- | -------- | ------ |
| MZ80K | Developed | | | MZ80C | Developed |
| MZ1200 | Developed | | | MZ80A | Developed |
| MZ700 | Developed | | | MZ80B | Developed |
| MZ2000 | Partially Developed | | | MZ800 | Under development |
<br>
The current version of the emulator provides:
| 48K RAM for MZ80K,C,1200,A |
| 64K RAM for MZ700, MZ80B |
| Hardware Tape Read/Write with selectable 1x - 32x Fast Mode |
| APSS Tape Drive for the MZ80B/MZ2000 - Fully automated APSS using the Menu Queue system. |
| Turbo Mode 1x - 32x (ie. 112MHz for MZ700) |
| Programmable Character Generator (PCG-8000/PCG-1200) |
| 40x25, 80x25 Mono and Colour Display Modes |
| 320x200, 640x200 8 Colour Bit addressed Graphics |
| VGA Scaling |
| Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type. |
| i8253 mono audio or Tape audio |
### Enhancements in test/under development
| Floppy Disk Drive/Controller 5.25" |
| Quick Disk Controller |
| Dual digital Joystick Input (MZ700) |
### Known Issues
| Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A. |
| HDMI needs to be re-enabled in the design. |
| Need to complete the status frame buffer, used by the ZPU I/O processor for status information display - not critical to use. |
## Installation
|1. |Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide |
|2. |Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:- |
| |scp SharpMZ_MiSTer/releases/SharpMZ_\<date\>.rbf root@\<de10 ip address\>/media/fat/SharpMZ.rbf |
| |Target name can be anything you like ending with .rbf |
|3. |Make a SharpMZ directory on the SD card, ie: |
| |ssh root@\<de10 ip address\> |
| |mkdir /media/fat/SharpMZ |
|4. |Copy any Rom Files, MZF Tape Files, DSK files across to the new directory, ie: |
| |scp \*.mzf root@\<de10 ip address\>:/media/fat/SharpMZ/ |
|5. |Start the MiSTer menu (ie. press the DE10 reset button if it is not showing). |
|6. |Select the SharpMZ core (or whatever name you called it). |
|7. |The emulator will boot into an MZ80K model with the SP-1002 monitor. |
|8. |Press F12 to change the configuration, select Save Config to store it. |
## Design Detail
### Design Summary
The idea of this design is to keep the emulation as independent of the HPS as possible (so it works standalone), only needing the HPS to set control registers,
read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be
someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone
wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external
SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
### Menu System
The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the
display parameters, debugging and access to the MiSTer control menu.
### Tape Storage
In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved
on to Floppy/Quick Disks.
This menu controls the hardware CMT unit and has the following choices:
- Load direct to RAM
This option allows you to load an MZF format tape file (ie. 128 bytes header + code) directly into RAM. It uses the Load Address and Size stored in the header in order to correctly
locate the code and also stores the header in the Cassette Work area at 10F0H. After load is completed and warm reset is made, the details of the tape are displayed on-screen. In
order to run the loaded program, simply issue the correct monitor command, ie. J1200 (Jump to 1200H where 1200H is shown as the Execution Address in the tape summary).
- Queue Tape
A real cassette has 1 or more programs stored on it sequentially. The emulation cache only stores 1 full program so this is a mechanism to line up multiple programs and they will
be fed into the emulation cache as it becomes empty, thus simulating a real cassette. Selecting this option presents you with a directory listing of all MZF files. Choose one per
selection and it will be added to the Queue. The programs queued will be displayed on the menu.
For the MZ80B/MZ2000, the original tape drive was an automated APSS drive capable of searching backwards and forwards for a program. The queue emulates this by interpreting the
APSS signals, moving the queue forward and backwards as necessary. Thus is you are to use a database program or similar which has multiple volumes you need to add these into the
tape queue for the program to function correctly.
- Clear Queue
This option allows you to purge all queue entries.
- <s>Save Tape</s>
<s>This option allows you to save a program to the MiSTer SD card which is in the emulation cache. Normally the emulation would have written a program/data to tape (ie. via the BASIC ‘SAVE’
command) which in reality is stored in the emulation cache. The tape is saved under the name given in the emulation save command (ie. in BASIC ‘SAVE “myfile”’ would result in a file
called myfile.mzf being saved).</s>
- <s>Auto Save Tape</s>
<s>This option allows you to auto save the emulation cache. Ie. when an emulation save completes, a flag is raised which is seen by the MiSTer program and the emulation cache is saved to SD under
the name given in the emulation.</s>
- <s>Tape Buttons</s>
<s>This option allows you to set the active Tape buttons, ie. Play, Record or Auto. Auto is a hardware mechanism to detect if the emulation is reading or writing to tape and process accordingly.</s>
- Fast Tape Load
This option allows you to set the speed of the tape drive. On the original machines, the tape runs at 1200baud which is quite slow, so use of this option is recommended.
You can select one of: "Off", "2x", "4x", "8x", "16x"
Selecting “Off” runs the tape drive at the original speed.
*NB: With the introduction of the APSS functionality, Save Tape and Auto Save Tape are redundant. When a program running on the emulation issues a save, the name is transferred through to the
MiSTer Main binary which then uses that name to create a file on the SD card.*
### Machine
The emulation emulates several Sharp MZ computers and this menu allows you to make selections accordingly.
- Machine Model
This option allows you to choose which Sharp MZ computer is emulated. Currently the choices are:
"MZ80K", "MZ80C", "MZ1200", "MZ80A", "MZ700" with "MZ800", "MZ80B", "MZ2000" in the pipeline.
- CPU Speed
This option allows you to set the speed at which the emulation runs. Generally speaking, higher speeds can be beneficial in non-graphics based applications although some games benefit from a small speed boost. The choices are:
- MZ80K/C/1200/A => "2MHz", "4MHz", "8MHz", "16MHz", "32MHz", "64MHz"
- MZ700 => "3.5MHz", "7MHz", "14MHz", "28MHz", "56MHz", "112MHz"
- Audio Source
This option allows you to choose what is played through the audio output. The choices are:
- Sound => The mono audio generated by the emulation output on L/R channels.
- Tape => The CMT signals as sound, Playback on Right channel, Record on Left channel. In theory you should be able to connect the right channel to an external tape drive and record to physical tape.
- Audio Volume
This option allows you to set the output volume. There are 16 possible steps from Min .. Max.
- Audio Mute
This option allows you to Mute the output.
- Rom Management
The emulation comes with the Monitor, Character Generator and Key Mapping Roms built-in for each machine emulated. This option selects a sub-menu which allows you to upload non-standard Roms when the emulation is started (ie. the Core is selected).
- Machine Model
This option allows you to select the emulated Sharp MZ computer to which the custom rom images will affect. The choices are:
"MZ80K", "MZ80C", "MZ1200", "MZ80A", "MZ700" with "MZ800", "MZ80B", "MZ2000" in the pipeline.
- User ROM
On some machine models (ie. MZ80A) there exists a socket to place a User ROM, which will have control passed to it should the first byte be 0 and non-writeable. Although this option only exists on certain models, it is a nice to have feature it is available for all machine models.
This option allows you to enable or disable the User ROM (NB. If you enable this option, it only enables hardware select, you still need to upload a ROM which has the first byte set to 0).
- Floppy Disk ROM
A Floppy Disk drive was an expansion option for the Sharp MZ computers, and with the advent of the MZ700, a Quick Disk drive was also an option. These options typically held control software in a ROM at location F000H. This option allows you to enable this feature, albeit you still need to upload a ROM.
- Enable Custom Rom
This section allows you to enable custom Roms and select the image which will be uploaded. For each Rom, you can enable or disable. If enabled, you can choose the required file. The Roms which can be customized are:
- Monitor (40x25)
- Monitor (80x25)
- Char Generator
- Key Mapping
- User Rom
- Floppy Disk
The Monitor Rom is a special case. Most of the Personal Sharp MZ Computers were only able to display 40x25 characters so the Rom hardcodes these parameters. Some people required wider screens for use with CPM, so hardware modifications were made to create an 80x25 display. The emulation is capable of both modes but in order to run correctly, a different Monitor Rom for 80x25 display is needed.
### Display
The display on the Sharp MZ computers was originally quite simplistic. In order to cater for enhancements made in each model and by external vendors, the emulation has several configurable parameters which are grouped under this menu.
- Display Type
This option allows you to select the display used. Normally, when a machine model is chosen, it defaults to the original display, this option allows you to override the default. The choices are:
"Mono 40x25", "Mono 80x25 ", "Colour 40x25", "Colour 80x25"
- VGA Scaling
In order to cater for various VGA monitors, this option programs the sync generator to mimic standard VGA signals. As VGA resolution is higher than the original Sharp MZ 40x25 screen (320x200 pixels), scaling occurs from the original format
upto the VGA format. The choices are:
"640x480@60Hz", "Off"
- Video
An extension to the original design was the addition of a graphics frame buffer. It is possible to blend the original display video with the graphics frame buffer. This option allows you to enable or disable the original display video (ie.
if you only want graphics).
- Graphics
There were various add-on boards made available in order to display bit addressable pixel graphics. This is my extension to the original design and as I gather information on other add-on boards, I will adapt the hardware interface so it accommodates
these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
- Graphics Addr
As the emulation is catering for several Sharp MZ models in addition to adding graphics onto machines which originally didnt have graphics there can be a clash of I/O address for selecting the graphics mode and options. This option sets the default
IO address for accessing the graphics control registers.
- VRAM CPU Wait
I deviated from the original design by adding a pixel based display buffer. During the Vertical Blanking period, I expand the character based VRAM and Attribute RAM into pixels and store them in the display buffer (a double buffer technique).
This consequently means that no snow/tearing will occur if the CPU accesses the VRAM/Attribute RAM during the visible display period. The original design added software waits (MZ80K) and hardware CPU wait states (MZ80A/700) to eliminate snow/tearing and
due to the addition of double buffering, this is no longer needed. You can thus disable the wait states with this option and gain some speed or enable them to keep compatibility.
- PCG Mode
All of the Sharp MZ computers used character generators which were hard coded in a ROM. External vendors offered add-ons to allow for a Programmable Character Generator based in RAM. This option enables the Programmable Character Generator which is
compatible with the HAL PCG-8000/PCG-1200 add-ons.
- <s>Aspect Ratio</s>
<s>This option is a MiSTer framework extension which converts the Aspect Ratio from 4:3 to 16:9. It doesn’t work at the moment with VGA output but should work on HDMI. Use this option to choose the desired format.</s>
- <s>Scandoubler</s>
<s>This option is a MiSTer framework extension which doubles the scan lines to widen/improve the image of older computer displays. It doesn’t work correctly with VGA output at the moment but should work on HDMI. The choices are:<br></s>
<s>"None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%"</s>
*NB: Aspect Ratio and Scandoubler are currently disabled due to the inclusion of the VGA Scaling hardware. When HDMI output is compiled into the design in the near future they will be re-enabled.*
### Debugging
*Debugging has now been made a compile time option. If debugging logic has been enabled in the RTL and Main MiSTer binary, the debugging options below will be available.*
As you cannot easily get out a trusty Oscilloscope or write breakpoint/debug messages with an FPGA, I’ve added a debugging mode which can be used at any time without affecting the emulation (unless you choose a debug frequency in which case the emulation will run at the selected frequency).
Basically, the 8 LED’s on the main DE10 main board can display a selectable set of signals, either in auto mode (move from set to set after a fixed period) or a static set. The sample rate of the signals displayed on the LED’s is selectable from the Z80 CPU frequency down to 1Hz. You can also attach an oscilloscope onto the LED’s and thus see the waveform if a simple flicker is not sufficient. In addition, you can slow the CPU frequency down in steps from 1MHz to 1/10Hz so you have a good chance of seeing what is happening internally.
This debugging addition is also a great method of understanding the internals of a computer and seeing the Z80 in action.
To use the debug mode, press F12 to enter the MiSTer menu, then select Debug and you are offered the following choices:
- Select Memory Bank
This option allows you to select one of the memory banks so it can be written to a local (DE10 SD Card) file.
- SysROM = System ROM. This is the complete concatenated set of Monitor ROM’s for all the emulations.
- SysRAM = System RAM. This is the 64K Main RAM.
- KeyMap = Key Mapping ROM. This is the complete concatenated set of Key Mapping’s for all the emulations.
- VRAM = Video RAM. This is the 2K Video RAM concatenated with the 2K Attribute RAM.
- CMTHDR = Cassette Header. This is the 128 byte memory holding the last loaded or saved tape header.
- CMTDATA = Cassette Data. This is the 64K memory holding the last loaded or saved tape data.
- CGROM = Character Generator ROM. This is the complete concatenated set of CGROM’s for all the emulations.
- CGRAM = Character Generator RAM. This is the 2K contents of the Programmable Character Generator RAM.
- All = This is the complete memory set as one file.
- Dump To <memory bank name>
Dump the selected memory bank. The system will show the file name used for the dump.
- Debug Mode
Select to Enable or Disable
- CPU Frequency
Select the CPU Frequency which can be one of:
"CPU/CMT", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz"
- Debug LEDS
Select to Enable or Disable
- Sample Freq
This is the sampling frequency used to sample the displayed signals. It can be one of:
"CPU/CMT", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz"
- Signal Block
This is the signal block for display. It can be one of:
- T80 => CPU Address/Data Bus and associated signals.
- I/O => Video, Keyboard and Select signals.
- IOCTL => External I/O Control. Address/Data and Select signals.
- Config => Register configuration signals.
- MZ80C I => 5 sets of signals relating to the MZ80K/C/1200/A/700/800.
- MZ80C II => An additional 5 sets of signals.
- MZ80B I => 5 sets of signals relating to the MZ80B/MZ2000.
- MZ80B II => An additional 5 sets of signals.
- Bank
This is the Bank within the Block to be displayed on the LED’s. It can be one of:
- T80 => "Auto", "A7-0", "A15-8", "DI", "Signals"
- I/O => "Auto", "Video", "PS2Key", "Signals"
- IOCTL => "Auto", "A23-16", "A15-8", "A7-0", "Signals"
- Config => "Auto", "Config 1", "Config 2", "Config 3", "Config 4", "Config 5"
- MZ80C I => "Auto", "CS 1", "CS 2", "CS 3", "INT/RE", "Clk"
- MZ80C II => "Auto", "CMT 1", "CMT 2", "CMT 3"
- MZ80B I => Not yet defined.
- MZ80B II => Not yet defined.
### System
This is the MiSTer main control menu which allows you to select a core, map keys, set bluetooth, view IP address etc.
### Control Options
The menu system presents additional control options whose function is detailed below:
| Option | Description |
| ------ | ----------- |
| Boot Reset | Perform a cold reset on the Emulator, ie. reset the FPGA and the HPS Processor |
| Reset | Reset the emulation, ie. toggle it's reset line. |
| Reload config | Reload the configuration saved previously. Any change made in these menus can be stored for future use, if additional changes are unwanted, use this option to reload your last good configuration. |
| Save config | Save the configuration to SD card. Any changes you made in the Menu system will be saved. |
| Reset config | Reset the configuration to standard defaults. |
### Graphics Frame Buffer
An addition to the original design is a 640x200/320x200 8 colour Graphics frame buffer. There were many additions to the Sharp MZ series to allow graphics (ie. MZ80B comes with standard mono graphics) display and as I don’t have detailed information of these to date, I designed my own extension with the intention of adding hardware abstraction layers at a later date to add compatibility to external vendor add-ons.
This frame buffer is made up of 3x16K RAM blocks, 1 per colour with a resolution of 640x200 which matches the output display buffer bit for bit. If the display is working at 40x25 characters then the resolution is 320x200, otherwise for 80x25 it is 640x200.
The RAM for the Graphics frame buffer can be switched into the main CPU address range C000H – FFFFH by programmable registers, 1 bank at a time (ie. Red, Green, Blue banks). This allows for direct CPU addressable pixels to be read and/or written. Each pixel is stored in groups of 8 (1 byte in RAM) scanning from right to left per byte, left to right per row, top to bottom. Ie. if the Red bank is mapped into CPU address space, the byte at C000H represents pixels 7 - 0 of 320/640 (X) at pixel 0 of 200 (Y). Thus 01H written to C000H would set Pixel 7 (X) on Row 0 (Y). This applies for Green and Blue banks when mapped into CPU address space.
In order to speed up display, there is a Colour Write register, so that a write to the graphics RAM will update all 3 banks at the same time.
The programmable registers are as follows:
*Switching Graphics RAM Bank into ZPU CPU Address Range*
- Graphics Bank Switch Set Register: I/O Address: E8H (232 decimal)
Switches in 1 of the 16Kb Graphics RAM pages (of the 3 pages) to C000 - FFFF. The bank which is switched in is set in the Control Register by bits 1/0 for Read operations and 3/2 for Write operations. This bank switch overrides all MZ80A/MZ700 page switching functions.
- Graphics Bank Switch Reset Register: I/O Address: E9H (233 decimal)
Switches out the Graphics RAM and returns to previous state.
*Control Register: I/O Address: EAH (234 decimal)*
- Bit 1:0
Read mode (00=Red Bank, 01=Green Bank, 10=Blue Bank, 11=Not used). Select which bank to be read when enabled in CPU address space.
- Bit 3:2
Write mode (00=Red Bank, 01=Green Bank, 10=Blue Bank, 11=Indirect). Select which bank to be written to when enabled in CPU address space.
- Bit 4
VRAM Output. 0=Enable, 1=Disable. Output Character RAM to the display.
- Bit 5
GRAM Output. 0=Enable, 1=Disable. Output Graphics RAM to the display.
- Bit 7:6
Blend Operator (00=OR ,01=AND, 10=NAND, 11=XOR). Operator to blend Character display with Graphics Display.
*Red Colour Writer Register: I/O Address: EBH (235 decimal)*
- Bit 0 Pixel 7 Set to Red during indirect write.
- Bit 1 Pixel 6
- Bit 2 Pixel 5
- Bit 3 Pixel 4
- Bit 4 Pixel 3
- Bit 5 Pixel 2
- Bit 6 Pixel 1
- Bit 7 Pixel 0 Set to Red during indirect write.
*Green Colour Writer Register: I/O Address: ECH (236 decimal)*
- Bit 0 Pixel 7 Set to Green during indirect write.
- Bit 1 Pixel 6
- Bit 2 Pixel 5
- Bit 3 Pixel 4
- Bit 4 Pixel 3
- Bit 5 Pixel 2
- Bit 6 Pixel 1
- Bit 7 Pixel 0 Set to Green during indirect write.
*Blue Colour Writer Register: I/O Address: EDH (237 decimal)*
- Bit 0 Pixel 7 Set to Blue during indirect write.
- Bit 1 Pixel 6
- Bit 2 Pixel 5
- Bit 3 Pixel 4
- Bit 4 Pixel 3
- Bit 5 Pixel 2
- Bit 6 Pixel 1
- Bit 7 Pixel 0 Set to Blue during indirect write.
For Indirect mode (Control Register bits 3/2 set to 11), a write to the Graphics RAM when mapped into CPU address space C000H – FFFFH will see the byte masked by the Red Colour Writer Register and written to the Red Bank with the same operation for Green and Blue. This allows rapid setting of a colour across the 3 banks.
## Links
The Sharp MZ Series Computers were not as wide spread as Commodore, Atari or Sinclair but they had a dedicated following. Given their open design it was very easy to modify and extend applications such as the BASIC interpreters and likewise easy to add hardware extension. As such, a look round the web finds some very comprehensive User Groups with invaluable resources. If you need manuals, programs, information then please look (for starters) at the following sites:
- https://www.eaw.app/
- https://original.sharpmz.org/
- https://www.sharpmz.no/
- https://mz-80a.com
- http://www.sharpusersclub.org/
- http://www.scav.cz/uvod.htm (use chrome to auto translate Czech)
## Credits
My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab and his excellent work.
Also credit to Sorgelig for his hard work in creating the MiSTer framework and design of some excellent hardware add-ons. The MiSTer framework makes it significantly easier to design/port emulations.
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. All 3rd party software, to my knowledge and research, is open source and freely useable, if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.
## Licenses
This design, hardware and software, is licensed under the GNU Public Licence v3.
### The Gnu Public License v3
The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.

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@@ -0,0 +1,15 @@
theme: jekyll-theme-tactile
plugins:
- jekyll-relative-links
relative_links:
enabled: true
collections: true
include:
- CONTRIBUTING.md
- README.md
- LICENSE.md
- COPYING.md
- CODE_OF_CONDUCT.md
- CONTRIBUTING.md
- ISSUE_TEMPLATE.md
- PULL_REQUEST_TEMPLATE.md

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@@ -0,0 +1,5 @@
<head>
<meta name="google-site-verification" content="7aW3GSa8lLGX4NCpZ-7SgoucuhoFArJ7qQudH-UpMFU" />
</head>
<body>
</body>

105
emu.sv
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@@ -30,7 +30,7 @@
module emu
(
//Master input clock
//Master input clocks
input CLK_50M,
//Async reset from top-level module.
@@ -77,11 +77,11 @@ module emu
// input TAPE_IN,
// SD-SPI
// output SD_SCK,
// output SD_MOSI,
// input SD_MISO,
// output SD_CS,
// input SD_CD,
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
@@ -94,7 +94,7 @@ module emu
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE
output DDRAM_WE,
//SDRAM interface with lower latency
// ,output SDRAM_CLK,
@@ -108,6 +108,8 @@ module emu
// output SDRAM_nCAS,
// output SDRAM_nRAS,
// output SDRAM_nWE
input UART_RX,
output UART_TX
);
//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
@@ -130,7 +132,7 @@ localparam CONF_STR =
{
"SHARP MZ SERIES;;",
"J,Fire;",
"V,v1.01.",`BUILD_DATE
"V,v1.02.",`BUILD_DATE
};
///////////////// CLOCKS ////////////////////////
@@ -151,8 +153,8 @@ wire [7:0] ioctl_index;
wire ioctl_wr;
wire ioctl_rd;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [7:0] ioctl_din;
wire [15:0] ioctl_dout;
wire [15:0] ioctl_din;
wire forced_scandoubler;
hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io
@@ -239,7 +241,7 @@ wire vblank_emu;
wire hsync_emu;
wire vsync_emu;
sharpmz sharp_mz
bridge sharp_mz
(
// Clocks Input to Emulator.
.clkmaster(CLK_50M),
@@ -273,6 +275,14 @@ sharpmz sharp_mz
.audio_l_o(audio_l_emu),
.audio_r_o(audio_r_emu),
.uart_rx(UART_RX),
.uart_tx(UART_TX),
.sd_sck(SD_SCK),
.sd_mosi(SD_MOSI),
.sd_miso(SD_MISO),
.sd_cs(SD_CS),
.sd_cd(SD_CD),
// HPS Interface
.ioctl_download(ioctl_download), // HPS Downloading to FPGA.
.ioctl_upload(ioctl_upload), // HPS Uploading from FPGA.
@@ -291,40 +301,47 @@ sharpmz sharp_mz
assign CLK_VIDEO = clk_video_in;
assign CE_PIXEL = clk_video_in;
assign VGA_R = R_emu;
assign VGA_G = G_emu;
assign VGA_B = B_emu;
assign VGA_VS = vsync_emu;
assign VGA_HS = hsync_emu;
assign VGA_DE = ~(vblank_emu | hblank_emu);
//video_mixer #(.HALF_DEPTH(0)) video_mixer
video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer
(
.clk_sys(clk_sys),
.ce_pix(clk_video_in), // Video pixel clock from core.
//.ce_pix_out(CE_PIXEL),
.scanlines({scale == 4, scale == 3, scale == 2}),
.scandoubler(scale || forced_scandoubler),
.hq2x(scale==1),
.mono(0),
// Input signals into the mixer, originating from the emulator.
.R(R_emu),
.G(G_emu),
.B(B_emu),
// Positive pulses.
.HSync(hsync_emu),
.VSync(vsync_emu),
.HBlank(hblank_emu),
.VBlank(vblank_emu),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.VGA_DE(VGA_DE)
// Outputs of the mixer are bound to the VGA_x signals defined in the sys_top module and passed into this module as parameters.
// These signals then feed the vga_osd -> vga_out modules in systop.v
);
//video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer
//(
// .clk_sys(clk_sys),
// .ce_pix(clk_video_in), // Video pixel clock from core.
// //.ce_pix_out(CE_PIXEL),
//
// .scanlines({scale == 4, scale == 3, scale == 2}),
// .scandoubler(scale || forced_scandoubler),
// .hq2x(scale==1),
//
// .mono(0),
//
// // Input signals into the mixer, originating from the emulator.
// .R(R_emu),
// .G(G_emu),
// .B(B_emu),
//
// // Positive pulses.
// .HSync(hsync_emu),
// .VSync(vsync_emu),
// .HBlank(hblank_emu),
// .VBlank(vblank_emu),
//
// .VGA_R(VGA_R),
// .VGA_G(VGA_G),
// .VGA_B(VGA_B),
// .VGA_VS(VGA_VS),
// .VGA_HS(VGA_HS),
// .VGA_DE(VGA_DE)
//
// // Outputs of the mixer are bound to the VGA_x signals defined in the sys_top module and passed into this module as parameters.
// // These signals then feed the vga_osd -> vga_out modules in systop.v
//);
// Uncomment below and comment out video_mixer to pass original signal to sys_top.v.
// To output original signal, edit sys_top.v and comment out vga_osd and vga_out, uncomment the assign statements.

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mz80b/cmt.vhd Normal file
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@@ -0,0 +1,294 @@
--
-- cmt.vhd
--
-- Sharp PWM Tape I/F and Pseudo-CMT module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2013-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cmt is
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Tape action interrupt
-- Z80 Bus
ZCLK : in std_logic;
-- ZA8 : in std_logic_vector(7 downto 0);
-- ZIWR_x : in std_logic;
-- ZDI : in std_logic_vector(7 downto 0);
-- ZDO : out std_logic_vector(7 downto 0);
-- Tape signals
T_END : out std_logic; -- Sense CMT(Motor on/off)
OPEN_x : in std_logic; -- Open
PLAY_x : in std_logic; -- Play
STOP_x : in std_logic; -- Stop
FF_x : in std_logic; -- Fast Foward
REW_x : in std_logic; -- Rewind
APSS_x : in std_logic; -- APSS
FFREW : in std_logic; -- FF/REW mode
FMOTOR : in std_logic; -- FF/REW start
FLATCH : in std_logic; -- FF/REW latch
WREADY : out std_logic; -- Write enable
TREADY : out std_logic; -- Tape exist
-- EXIN : in std_logic; -- CMT IN from I/O board
RDATA : out std_logic; -- to 8255
-- Status Signal
SCLK : in std_logic; -- Slow Clock(31.25kHz)
MZMODE : in std_logic; -- Hardware Mode
DMODE : in std_logic -- Display Mode
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end cmt;
architecture RTL of cmt is
--
-- Status
--
signal RPLBUF : std_logic_vector(2 downto 0);
signal REG_PL : std_logic;
signal RSTBUF : std_logic_vector(2 downto 0);
signal REJBUF : std_logic_vector(2 downto 0);
signal REG_EJ : std_logic;
signal RREBUF : std_logic_vector(2 downto 0);
signal REG_RE : std_logic;
signal RFFBUF : std_logic_vector(2 downto 0);
signal REG_FF : std_logic;
signal RASBUF : std_logic_vector(2 downto 0);
signal REG_AS : std_logic;
signal RLTBUF : std_logic_vector(2 downto 0);
signal RFMBUF : std_logic_vector(2 downto 0);
signal REG_RE_M : std_logic;
signal REG_FF_M : std_logic;
signal TAPE : std_logic;
signal WP : std_logic;
signal MOTOR : std_logic;
signal PBIT : std_logic;
signal RBYTE : std_logic_vector(15 downto 0);
signal PON : std_logic;
signal APSS : std_logic;
signal FA : std_logic;
--
-- Pulse Generator
--
signal POUT : std_logic;
signal PCNT : std_logic_vector(10 downto 0);
signal PBUSY : std_logic;
signal PEXT : std_logic_vector(4 downto 0);
----
---- Filters
----
--signal CNT3 : std_logic_vector(1 downto 0);
--signal PL_BTN : std_logic_vector(1 downto 0);
--signal ST_BTN : std_logic_vector(1 downto 0);
--signal T_BTN : std_logic;
----
---- Divider
----
--signal DIV : std_logic_vector(13 downto 0);
----
---- Registers for Z80
----
--signal MADR : std_logic_vector(15 downto 0);
--signal MBYTE : std_logic_vector(15 downto 0);
--signal MCMD : std_logic_vector(7 downto 0);
--signal STAT : std_logic_vector(7 downto 0);
--
-- Components
--
begin
--
-- HPS Bus
--
process( RST_n, CLK ) begin
if RST_n='0' then
WP <='0';
MOTOR <='0';
TAPE <='0';
REG_PL <='0';
REG_EJ <='0';
REG_FF <='0';
REG_RE <='0';
REG_AS <='0';
REG_FF_M <='0';
REG_RE_M <='0';
PBIT <='0';
PON <='0';
FA <='0';
PEXT <=(others=>'0');
elsif CLK'event and CLK='1' then
-- Edge Sense
if MZMODE='0' then
RPLBUF<=RPLBUF(1 downto 0)&PLAY_x; -- MZ-80B
else
RPLBUF <= RPLBUF(1 downto 0)&(not PLAY_x); -- MZ-2000
end if;
if RPLBUF(2 downto 1)="01" then
REG_PL <= TAPE;
REG_AS <= '0';
end if;
if MZMODE='0' then
RSTBUF <= RSTBUF(1 downto 0)&STOP_x; -- MZ-80B
else
RSTBUF <= RSTBUF(1 downto 0)&(not STOP_x); -- MZ-2000
end if;
if RSTBUF(2 downto 1)="01" then
MOTOR <= '0';
REG_AS <= '0';
REG_FF <= '0';
REG_RE <= '0';
end if;
REJBUF<=REJBUF(1 downto 0)&(not OPEN_x);
if REJBUF(2 downto 1)="01" then
REG_EJ <= '1';
TAPE <= '0';
REG_AS <= '0';
REG_FF <= '0';
REG_RE <= '0';
end if;
if MZMODE='0' then -- MZ-80B
RLTBUF <= RLTBUF(1 downto 0)&FLATCH;
if RLTBUF(2 downto 1)="01" then
REG_RE_M <= not FFREW;
REG_FF_M <= FFREW;
end if;
RFMBUF<=RFMBUF(1 downto 0)&FMOTOR;
if RFMBUF(2 downto 1)="01" then
REG_RE <= REG_RE_M and TAPE;
REG_FF <= REG_FF_M and TAPE;
REG_AS <= TAPE;
end if;
else -- MZ-2000
RREBUF<=RREBUF(1 downto 0)&(not REW_x);
if RREBUF(2 downto 1)="01" then
REG_RE <= TAPE;
end if;
RFFBUF<=RFFBUF(1 downto 0)&(not FF_x);
if RFFBUF(2 downto 1)="01" then
REG_FF <= TAPE;
end if;
RASBUF<=RASBUF(1 downto 0)&(not APSS_x);
if RASBUF(2 downto 1)="01" then
REG_AS <= TAPE;
end if;
end if;
-- Register
if IOCTL_RD='1' and IOCTL_WR='1' then
if IOCTL_ADDR=X"0010" and PBUSY='0' then -- MZ_CMT_POUT
PBIT <= IOCTL_DOUT(0);
PEXT <= "11111";
else
PEXT <= PEXT(3 downto 0)&'0';
end if;
if IOCTL_ADDR=X"0011" then -- MZ_CMT_STATUS
REG_AS <= REG_AS and (not IOCTL_DOUT(4));
REG_RE <= REG_RE and (not IOCTL_DOUT(3));
REG_FF <= REG_FF and (not IOCTL_DOUT(2));
REG_PL <= REG_PL and (not IOCTL_DOUT(1));
REG_EJ <= REG_EJ and (not IOCTL_DOUT(0));
end if;
if IOCTL_ADDR=X"0012" then -- MZ_CMT_COUNT
RBYTE(7 downto 0) <= IOCTL_DOUT;
end if;
if IOCTL_ADDR=X"0013" then -- MZ_CMT_COUNTH
RBYTE(15 downto 8) <= IOCTL_DOUT;
end if;
if IOCTL_ADDR=X"0014" then -- MZ_CMT_CTRL
FA <= IOCTL_DOUT(4);
PON <= IOCTL_DOUT(3);
WP <= IOCTL_DOUT(2);
MOTOR <= IOCTL_DOUT(1);
TAPE <= IOCTL_DOUT(0);
end if;
else
PEXT <= PEXT(3 downto 0)&'0';
end if;
end if;
end process;
IOCTL_DIN <= "0000000"&PBUSY when IOCTL_RD='1' and IOCTL_ADDR=X"0010" else -- MZ_CMT_POUT
"000"&REG_AS&REG_RE&REG_FF&REG_PL&REG_EJ when IOCTL_RD='1' and IOCTL_ADDR=X"0011" else -- MZ_CMT_STATUS
"000"&FA&PON&WP&MOTOR&TAPE when IOCTL_RD='1' and IOCTL_ADDR=X"0014" else -- MZ_CMT_CTRL
"00000000";
APSS <= REG_AS or FA;
INTO <= REG_PL or REG_EJ or REG_RE or REG_FF;
WREADY <= not WP;
TREADY <= not TAPE;
T_END <= not MOTOR;
RDATA <= POUT or PON;
--
-- PWM pulse generate
--
process( RST_n, ZCLK ) begin
if RST_n='0' then
POUT <='0';
PBUSY <='0';
PCNT <=(others=>'0');
elsif ZCLK'event and ZCLK='1' then
if PEXT(4)='1' then
if PBIT='0' then
PCNT <= "01010011011"; --667
else
PCNT <= "10100110100"; --1332
end if;
POUT <= '1';
PBUSY <= '1';
else
if POUT='1' and PCNT=0 then
if PBIT='0' then
PCNT <= "01010011000"; --664
else
PCNT <= "10100110110"; --1334
end if;
POUT <= '0';
elsif POUT='0' and PCNT=0 then
PBUSY <= '0';
else
PCNT <= PCNT-'1';
end if;
end if;
end if;
end process;
-- --
-- -- MZ-80B Action for Quick Access
-- --
-- process( reset, ZCLK ) begin
-- if reset='1' then
-- MADR<=(others=>'0');
-- MBYTE<=(others=>'0');
-- MCMD<=(others=>'0');
-- interrupt<='1';
-- elsif ZCLK'event and ZCLK='0' then
-- if ZIWR_x='0' and ZA8(7 downto 3)="10001" then
-- case ZA8(2 downto 0) is
-- when "000" => MADR(7 downto 0)<=ZDI; interrupt<='1';
-- when "001" => MADR(15 downto 8)<=ZDI; interrupt<='1';
-- when "010" => MBYTE(7 downto 0)<=ZDI; interrupt<='1';
-- when "011" => MBYTE(15 downto 8)<=ZDI; interrupt<='1';
-- when others => MCMD<=ZDI; interrupt<=not(ZDI(7) or ZDI(6) or ZDI(5) or ZDI(4) or ZDI(3) or ZDI(2) or ZDI(1) or ZDI(0));
-- end case;
-- end if;
-- end if;
-- end process;
-- ZDO<=STAT;
end RTL;

647
mz80b/fd55b.vhd Normal file
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@@ -0,0 +1,647 @@
--
-- fd55b.vhd
--
-- Floppy Disk Drive Emulation module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014-2015
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fd55b is
generic
(
DS_SW : std_logic_vector(4 downto 1) := "1111";
REG_ADDR : std_logic_vector(15 downto 0) := "0000000000000000"
);
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Step Pulse interrupt
-- FD signals
FCLK : in std_logic;
DS_n : in std_logic_vector(4 downto 1); -- Drive Select
HS : in std_logic; -- Head Select
MOTOR_n : in std_logic; -- Motor On
INDEX_n : out std_logic; -- Index Hole Detect
TRACK00 : out std_logic; -- Track 0
WPRT_n : out std_logic; -- Write Protect
STEP_n : in std_logic; -- Head Step In/Out
DIREC : in std_logic; -- Head Step Direction
WG_n : in std_logic; -- Write Gate
DTCLK : out std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Write Data
FDO : out std_logic_vector(7 downto 0); -- Read Data
-- Buffer RAM I/F
BCS_n : out std_logic; -- RAM Request
BADR : out std_logic_vector(22 downto 0); -- RAM Address
BWR_n : out std_logic; -- RAM Write Signal
BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end fd55b;
architecture RTL of fd55b is
--
-- Signals
--
signal DS : std_logic; -- Drive Select
signal HS_n : std_logic; -- Side One Select
signal DIV : std_logic_vector(6 downto 0); -- Divider
signal SS : std_logic; -- ROM Address multiplexer
signal PC : std_logic_vector(4 downto 0); -- ROM Address
signal OP : std_logic_vector(7 downto 0); -- OP code
signal ROMOUT : std_logic_vector(31 downto 0); -- ROM Data
signal TRACK : std_logic_vector(5 downto 0); -- Track Number
signal MF : std_logic; -- Modify Flag
signal PHASE : std_logic; -- Phase of Process
signal SSIZE : std_logic_vector(3 downto 0); -- Sector Size
signal FDOi : std_logic_vector(7 downto 0); -- Output Data(internal)
signal WP : std_logic; -- Write Protect Flag
signal DISK : std_logic; -- Disk Exist
signal D88 : std_logic; -- D88 flag(more 16bytes)
signal RSTBUF : std_logic_vector(2 downto 0); -- Step Pulse Shift Register
signal REG_ST : std_logic; -- Step Pulse Detect
signal CS : std_logic; -- Chip Select
signal RSEL : std_logic_vector(4 downto 0); -- Register Select
signal HSEL : std_logic; -- Register Select by Head
signal GAP3 : std_logic_vector(7 downto 0); -- GAP3 length
signal GAP4 : std_logic_vector(15 downto 0); -- GAP4 length
signal BADRi : std_logic_vector(22 downto 0); -- RAM Address(internal)
signal BDOi : std_logic_vector(7 downto 0); -- RAM Write Data(internal)
signal OUTEN : std_logic; -- Drive Selected, Disk Inserted, Motor On
---- Register set of side 0
signal DDEN0 : std_logic; -- density 0=FM,1=MFM side0
signal COUNT0 : std_logic_vector(10 downto 0); -- Timing Counter(Count down)
signal PSECT0 : std_logic_vector(3 downto 0); -- Phisical Sector Number
signal LSECT0 : std_logic_vector(7 downto 0); -- Logical Sector Number
signal MAXSECT0 : std_logic_vector(3 downto 0); -- Number of Sectors side0
signal TRADR0 : std_logic_vector(22 downto 0); -- Track data top address side0
signal FDO0i : std_logic_vector(7 downto 0); -- Output Data(internal)
signal PC0 : std_logic_vector(4 downto 0); -- ROM Address
signal ROMOUT0 : std_logic_vector(31 downto 0); -- ROM Data
signal OP0 : std_logic_vector(7 downto 0); -- OP code
signal FDAT0 : std_logic_vector(7 downto 0); -- Format Data
signal PHASE0 : std_logic; -- Phase of Process
signal DCLK0 : std_logic; -- Data Clock(internal)
signal FIRST0 : std_logic; -- First Action
signal MF0 : std_logic; -- Modify Flag
signal LSEL0 : std_logic_vector(3 downto 0); -- ID register select
signal LSEC00 : std_logic_vector(7 downto 0); -- Logical Sector Number table side0
signal LSEC01 : std_logic_vector(7 downto 0);
signal LSEC02 : std_logic_vector(7 downto 0);
signal LSEC03 : std_logic_vector(7 downto 0);
signal LSEC04 : std_logic_vector(7 downto 0);
signal LSEC05 : std_logic_vector(7 downto 0);
signal LSEC06 : std_logic_vector(7 downto 0);
signal LSEC07 : std_logic_vector(7 downto 0);
signal LSEC08 : std_logic_vector(7 downto 0);
signal LSEC09 : std_logic_vector(7 downto 0);
signal LSEC0A : std_logic_vector(7 downto 0);
signal LSEC0B : std_logic_vector(7 downto 0);
signal LSEC0C : std_logic_vector(7 downto 0);
signal LSEC0D : std_logic_vector(7 downto 0);
signal LSEC0E : std_logic_vector(7 downto 0);
signal LSEC0F : std_logic_vector(7 downto 0);
signal BADR0i : std_logic_vector(22 downto 0); -- RAM Address(internal)
signal BDO0i : std_logic_vector(7 downto 0); -- RAM Write Data(internal)
signal INDEX0_n : std_logic; -- Index Pulse(internal)
signal IPCNT0 : std_logic_vector(2 downto 0); -- Index Pulse Counter
signal GAP30 : std_logic_vector(7 downto 0); -- GAP3 length
signal GAP40 : std_logic_vector(15 downto 0); -- GAP4 length
---- Register set of side 1
signal DDEN1 : std_logic; -- density 0=FM,1=MFM side1
signal COUNT1 : std_logic_vector(10 downto 0); -- Timing Counter(Count down)
signal PSECT1 : std_logic_vector(3 downto 0); -- Phisical Sector Number
signal LSECT1 : std_logic_vector(7 downto 0); -- Logical Sector Number
signal MAXSECT1 : std_logic_vector(3 downto 0); -- Number of Sectors side1
signal TRADR1 : std_logic_vector(22 downto 0); -- Track data top address side1
signal FDO1i : std_logic_vector(7 downto 0); -- Output Data(internal)
signal PC1 : std_logic_vector(4 downto 0); -- ROM Address
signal ROMOUT1 : std_logic_vector(31 downto 0); -- ROM Data
signal OP1 : std_logic_vector(7 downto 0); -- OP code
signal FDAT1 : std_logic_vector(7 downto 0); -- Format Data
signal PHASE1 : std_logic; -- Phase of Process
signal DCLK1 : std_logic; -- Data Clock(internal)
signal FIRST1 : std_logic; -- First Action
signal MF1 : std_logic; -- Modify Flag
signal LSEL1 : std_logic_vector(3 downto 0); -- ID register select
signal LSEC10 : std_logic_vector(7 downto 0); -- Logical Sector Number table side1
signal LSEC11 : std_logic_vector(7 downto 0);
signal LSEC12 : std_logic_vector(7 downto 0);
signal LSEC13 : std_logic_vector(7 downto 0);
signal LSEC14 : std_logic_vector(7 downto 0);
signal LSEC15 : std_logic_vector(7 downto 0);
signal LSEC16 : std_logic_vector(7 downto 0);
signal LSEC17 : std_logic_vector(7 downto 0);
signal LSEC18 : std_logic_vector(7 downto 0);
signal LSEC19 : std_logic_vector(7 downto 0);
signal LSEC1A : std_logic_vector(7 downto 0);
signal LSEC1B : std_logic_vector(7 downto 0);
signal LSEC1C : std_logic_vector(7 downto 0);
signal LSEC1D : std_logic_vector(7 downto 0);
signal LSEC1E : std_logic_vector(7 downto 0);
signal LSEC1F : std_logic_vector(7 downto 0);
signal BADR1i : std_logic_vector(22 downto 0); -- RAM Address(internal)
signal BDO1i : std_logic_vector(7 downto 0); -- RAM Write Data(internal)
signal INDEX1_n : std_logic; -- Index Pulse(internal)
signal IPCNT1 : std_logic_vector(2 downto 0); -- Index Pulse Counter
signal GAP31 : std_logic_vector(7 downto 0); -- GAP3 length
signal GAP41 : std_logic_vector(15 downto 0); -- GAP4 length
begin
--
-- Format Direction Table
--
process( PC ) begin
case( PC ) is
-- FM
when "00000" => ROMOUT<="1111"&"0000"&"11111111"&"0000000000001111";
when "00001" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000101";
when "00010" => ROMOUT<="1111"&"0000"&"11111110"&"0000000000000000";
when "00011" => ROMOUT<="0010"&"0000"&"00000000"&"0000000000000011";
when "00100" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "00101" => ROMOUT<="1111"&"0000"&"11111111"&"0000000000001010";
when "00110" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000101";
when "00111" => ROMOUT<="0100"&"0000"&"11111011"&"00000"&SSIZE&"0000000";
when "01000" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "01001" => ROMOUT<="1100"&"0001"&"11111111"&"00000000"&GAP3;
when "01010" => ROMOUT<="0000"&"0000"&"11111111"&GAP4;
-- MFM
when "10000" => ROMOUT<="1111"&"0000"&"01001110"&"0000000000011111";
when "10001" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000001011";
when "10010" => ROMOUT<="1111"&"0000"&"10100001"&"0000000000000010";
when "10011" => ROMOUT<="1111"&"0000"&"11111110"&"0000000000000000";
when "10100" => ROMOUT<="0010"&"0000"&"00000000"&"0000000000000011";
when "10101" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "10110" => ROMOUT<="1111"&"0000"&"01001110"&"0000000000010101";
when "10111" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000001011";
when "11000" => ROMOUT<="1111"&"0000"&"10100001"&"0000000000000010";
when "11001" => ROMOUT<="0100"&"0000"&"11111011"&"00000"&SSIZE&"0000000";
when "11010" => ROMOUT<="1111"&"0000"&"00000000"&"0000000000000001";
when "11011" => ROMOUT<="1100"&"0001"&"01001110"&"00000000"&GAP3;
when "11100" => ROMOUT<="0000"&"0000"&"01001110"&GAP4;
when others => ROMOUT<=(others=>'0');
end case;
end process;
--
-- Decode Sector size from Sector ID
--
process( SS, LSECT0(1 downto 0), LSECT1(1 downto 0) ) begin
case( SS ) is
when '0' =>
case( LSECT0(1 downto 0) ) is
when "00" => SSIZE<="0001";
when "01" => SSIZE<="0010";
when "10" => SSIZE<="0100";
when others => SSIZE<="1000";
end case;
when others =>
case( LSECT1(1 downto 0) ) is
when "00" => SSIZE<="0001";
when "01" => SSIZE<="0010";
when "10" => SSIZE<="0100";
when others => SSIZE<="1000";
end case;
end case;
end process;
--
-- Select GAP3/GAP4 length
--
GAP3 <= GAP30 when SS='0' else GAP31;
GAP4 <= GAP40 when SS='0' else GAP41;
--
-- FDT access
--
process( RST_n, FCLK ) begin
if RST_n='0' then
SS<='0';
elsif FCLK'event and FCLK='1' then
SS<=not SS;
if SS='0' then
ROMOUT0<=ROMOUT;
else
ROMOUT1<=ROMOUT;
end if;
end if;
end process;
PC<=PC0 when SS='0' else PC1;
--
-- Sector Table
--
process( PSECT0, LSEC00, LSEC01, LSEC02, LSEC03, LSEC04, LSEC05, LSEC06, LSEC07, LSEC08, LSEC09, LSEC0A, LSEC0B, LSEC0C, LSEC0D, LSEC0E, LSEC0F ) begin
case PSECT0 is
when "0000" => LSECT0<=LSEC00;
when "0001" => LSECT0<=LSEC01;
when "0010" => LSECT0<=LSEC02;
when "0011" => LSECT0<=LSEC03;
when "0100" => LSECT0<=LSEC04;
when "0101" => LSECT0<=LSEC05;
when "0110" => LSECT0<=LSEC06;
when "0111" => LSECT0<=LSEC07;
when "1000" => LSECT0<=LSEC08;
when "1001" => LSECT0<=LSEC09;
when "1010" => LSECT0<=LSEC0A;
when "1011" => LSECT0<=LSEC0B;
when "1100" => LSECT0<=LSEC0C;
when "1101" => LSECT0<=LSEC0D;
when "1110" => LSECT0<=LSEC0E;
when others => LSECT0<=LSEC0F;
end case;
end process;
process( PSECT1, LSEC10, LSEC11, LSEC12, LSEC13, LSEC14, LSEC15, LSEC16, LSEC17, LSEC18, LSEC19, LSEC1A, LSEC1B, LSEC1C, LSEC1D, LSEC1E, LSEC1F ) begin
case PSECT1 is
when "0000" => LSECT1<=LSEC10;
when "0001" => LSECT1<=LSEC11;
when "0010" => LSECT1<=LSEC12;
when "0011" => LSECT1<=LSEC13;
when "0100" => LSECT1<=LSEC14;
when "0101" => LSECT1<=LSEC15;
when "0110" => LSECT1<=LSEC16;
when "0111" => LSECT1<=LSEC17;
when "1000" => LSECT1<=LSEC18;
when "1001" => LSECT1<=LSEC19;
when "1010" => LSECT1<=LSEC1A;
when "1011" => LSECT1<=LSEC1B;
when "1100" => LSECT1<=LSEC1C;
when "1101" => LSECT1<=LSEC1D;
when "1110" => LSECT1<=LSEC1E;
when others => LSECT1<=LSEC1F;
end case;
end process;
--
-- Clock Divider
--
process( RST_n, FCLK ) begin
if RST_n='0' then
DIV<=(others=>'0');
DCLK0<='0';
DCLK1<='0';
elsif FCLK'event and FCLK='1' then
DIV<=DIV+'1';
if DIV(5 downto 0)="111111" then
if MOTOR_n='0' and (DDEN0='1' or (DDEN0='0' and DIV(6)='1')) then
DCLK0<='1';
else
DCLK0<='0';
end if;
if MOTOR_n='0' and (DDEN1='1' or (DDEN1='0' and DIV(6)='1')) then
DCLK1<='1';
else
DCLK1<='0';
end if;
else
DCLK0<='0';
DCLK1<='0';
end if;
end if;
end process;
--
-- Track Sequencer
--
process( RST_n, FCLK ) begin
if RST_n='0' then
-- Side 0
PHASE0<='0';
COUNT0<=(others=>'0');
PSECT0<=(others=>'0');
PC0(3 downto 0)<=(others=>'0');
BADR0i<=(others=>'0');
BDO0i<=(others=>'0');
INDEX0_n<='1';
IPCNT0<=(others=>'1');
-- Side 1
PHASE1<='0';
COUNT1<=(others=>'0');
PSECT1<=(others=>'0');
PC1(3 downto 0)<=(others=>'0');
BADR1i<=(others=>'0');
BDO1i<=(others=>'0');
INDEX1_n<='1';
IPCNT1<=(others=>'1');
elsif FCLK'event and FCLK='1' then
-- Disk Removed
if DISK='0' then
MF0<='0';
MF1<='0';
end if;
-- Sequencer
-- Side 0
if DCLK0='1' then
PHASE0<=not PHASE0;
if PHASE0='0' then
case OP0(7 downto 4) is
when "0010" => -- ID
case COUNT0(1 downto 0) is
when "11" =>
FDO0i<="00"&TRACK;
when "10" =>
FDO0i<="0000000"&LSECT0(7);
when "01" =>
FDO0i<="000"&LSECT0(6 downto 2);
when others =>
FDO0i<="000000"&LSECT0(1 downto 0);
end case;
when "0100" => -- DATA
if FIRST0='1' then
FDO0i<=FDAT0;
else
FDO0i<=BDI;
BADR0i<=BADR0i+'1';
end if;
when "0000" => -- JMP
if COUNT0="00000000000" then
PC0(3 downto 0)<=OP0(3 downto 0);
end if;
FDO0i<=FDAT0;
when "1100" => -- LOOP
if COUNT0="00000000000" then
if PSECT0=MAXSECT0 then
PSECT0<=(others=>'0');
else
PC0(3 downto 0)<=OP0(3 downto 0);
PSECT0<=PSECT0+'1';
end if;
end if;
FDO0i<=FDAT0;
when others => -- NOP
FDO0i<=FDAT0;
end case;
else -- PHASE='1'
if COUNT0="00000000000" then
OP0<=ROMOUT0(31 downto 24);
FDAT0<=ROMOUT0(23 downto 16);
COUNT0<=ROMOUT0(10 downto 0);
FIRST0<='1';
PC0(3 downto 0)<=PC0(3 downto 0)+'1';
if PC0(3 downto 0)="0000" then
BADR0i<=TRADR0;
end if;
if OP0(7 downto 4)="0100" and D88='1' then -- DATA
BADR0i<=BADR0i+"10000";
end if;
else
FIRST0<='0';
COUNT0<=COUNT0-'1';
if OP0(7 downto 4)="0100" then -- DATA
if WG_n='0' and WP='0' then
BDO0i<=FDI;
MF0<='1';
end if;
end if;
end if;
end if;
-- Index Pulse
if PC0(3 downto 0)="0000" then
IPCNT0<=(others=>'0');
INDEX0_n<='0';
else
if IPCNT0="111" then
INDEX0_n<='1';
else
IPCNT0<=IPCNT0+'1';
end if;
end if;
end if;
-- Side 1
if DCLK1='1' then
PHASE1<=not PHASE1;
if PHASE1='0' then
case OP1(7 downto 4) is
when "0010" => -- ID
case COUNT1(1 downto 0) is
when "11" =>
FDO1i<="00"&TRACK;
when "10" =>
FDO1i<="0000000"&LSECT1(7);
when "01" =>
FDO1i<="000"&LSECT1(6 downto 2);
when others =>
FDO1i<="000000"&LSECT1(1 downto 0);
end case;
when "0100" => -- DATA
if FIRST1='1' then
FDO1i<=FDAT1;
else
FDO1i<=BDI;
BADR1i<=BADR1i+'1';
end if;
when "0000" => -- JMP
if COUNT1="00000000000" then
PC1(3 downto 0)<=OP1(3 downto 0);
end if;
FDO1i<=FDAT1;
when "1100" => -- LOOP
if COUNT1="00000000000" then
if PSECT1=MAXSECT1 then
PSECT1<=(others=>'0');
else
PC1(3 downto 0)<=OP1(3 downto 0);
PSECT1<=PSECT1+'1';
end if;
end if;
FDO1i<=FDAT1;
when others => -- NOP
FDO1i<=FDAT1;
end case;
else -- PHASE='1'
if COUNT1="00000000000" then
OP1<=ROMOUT1(31 downto 24);
FDAT1<=ROMOUT1(23 downto 16);
COUNT1<=ROMOUT1(10 downto 0);
FIRST1<='1';
PC1(3 downto 0)<=PC1(3 downto 0)+'1';
if PC1(3 downto 0)="0000" then
BADR1i<=TRADR1;
end if;
if OP1(7 downto 4)="0100" and D88='1' then -- DATA
BADR1i<=BADR1i+"10000";
end if;
else
FIRST1<='0';
COUNT1<=COUNT1-'1';
if OP1(7 downto 4)="0100" then -- DATA
if WG_n='0' and WP='0' then
BDO1i<=FDI;
MF1<='1';
end if;
end if;
end if;
end if;
-- Index Pulse
if PC1(3 downto 0)="0000" then
IPCNT1<=(others=>'0');
INDEX1_n<='0';
else
if IPCNT1="111" then
INDEX1_n<='1';
else
IPCNT1<=IPCNT1+'1';
end if;
end if;
end if;
end if;
end process;
PC0(4) <= DDEN0;
PC1(4) <= DDEN1;
MF <= MF0 or MF1;
DS <= not((DS_n(1) or DS_SW(1)) and (DS_n(2) or DS_SW(2)) and (DS_n(3) or DS_SW(3)) and (DS_n(4) or DS_SW(4)));
OUTEN <= '1' when DS='1' and DISK='1' and MOTOR_n='0' else '0';
HS_n <= not HS;
WPRT_n <= not WP when DS='1' and DISK='1' else '1';
TRACK00 <= '0' when TRACK="000000" and DS='1' else '1';
FDO <= FDOi when DS='1' and DISK='1' else (others=>'0');
DTCLK <= not PHASE when OUTEN='1' else '0';
--
-- Select Output with Head Select
--
process( HS_n, PHASE0, FDO0i, INDEX0_n, OP0, BADR0i, BDO0i, PHASE1, FDO1i, INDEX1_n, OP1, BADR1i, BDO1i ) begin
if HS_n='0' then
PHASE <= PHASE0;
FDOi <= FDO0i;
BADRi <= BADR0i;
BDOi <= BDO0i;
INDEX_n <= INDEX0_n or (not (DS and DISK));
OP <= OP0;
else
PHASE <= PHASE1;
FDOi <= FDO1i;
BADRi <= BADR1i;
BDOi <= BDO1i;
INDEX_n <= INDEX1_n or (not (DS and DISK));
OP <= OP1;
end if;
end process;
BCS_n <= '0' when PHASE='0' and OP(7 downto 4)="0100" and OUTEN='1' else '1'; -- DATA
BWR_n <= '0' when PHASE='0' and OP(7 downto 4)="0100" and WG_n='0' and WP='0' and OUTEN='1' else '1'; -- DATA
BADR <= BADRi when DS='1' else (others=>'0');
BDO <= BDOi when DS='1' else (others=>'0');
--
-- Avalon Bus
--
process( RST_n, CLK ) begin
if RST_n='0' then
DISK <='0';
DDEN0 <='0';
DDEN1 <='0';
REG_ST <='0';
TRACK <=(others=>'0');
WP <='0';
elsif CLK'event and CLK='1' then
-- Edge Sense
RSTBUF <= RSTBUF(1 downto 0)&((not STEP_n) and DS);
if RSTBUF(2 downto 1)="01" then
REG_ST <= '1';
end if;
-- Register
if IOCTL_RD='1' and IOCTL_WR='1' and CS='1' then
case RSEL is
when "00000"|"00001" => -- MZ_FDx_CTRL
D88 <= IOCTL_DOUT(2);
WP <= IOCTL_DOUT(1);
DISK <= IOCTL_DOUT(0);
when "00010"|"00011" => -- MZ_FDx_TRK
TRACK <= IOCTL_DOUT(5 downto 0);
when "00100"|"00101" => -- MZ_FDx_STEP
REG_ST <= REG_ST and (not IOCTL_DOUT(0));
when "00110"|"00111" => -- MZ_FDx_HSEL
HSEL <= IOCTL_DOUT(0);
when "01000" => -- MZ_FDx_ID
case LSEL0 is
when "0000" => LSEC00<=IOCTL_DOUT;
when "0001" => LSEC01<=IOCTL_DOUT;
when "0010" => LSEC02<=IOCTL_DOUT;
when "0011" => LSEC03<=IOCTL_DOUT;
when "0100" => LSEC04<=IOCTL_DOUT;
when "0101" => LSEC05<=IOCTL_DOUT;
when "0110" => LSEC06<=IOCTL_DOUT;
when "0111" => LSEC07<=IOCTL_DOUT;
when "1000" => LSEC08<=IOCTL_DOUT;
when "1001" => LSEC09<=IOCTL_DOUT;
when "1010" => LSEC0A<=IOCTL_DOUT;
when "1011" => LSEC0B<=IOCTL_DOUT;
when "1100" => LSEC0C<=IOCTL_DOUT;
when "1101" => LSEC0D<=IOCTL_DOUT;
when "1110" => LSEC0E<=IOCTL_DOUT;
when others => LSEC0F<=IOCTL_DOUT;
end case;
when "01001" =>
case LSEL1 is
when "0000" => LSEC10<=IOCTL_DOUT;
when "0001" => LSEC11<=IOCTL_DOUT;
when "0010" => LSEC12<=IOCTL_DOUT;
when "0011" => LSEC13<=IOCTL_DOUT;
when "0100" => LSEC14<=IOCTL_DOUT;
when "0101" => LSEC15<=IOCTL_DOUT;
when "0110" => LSEC16<=IOCTL_DOUT;
when "0111" => LSEC17<=IOCTL_DOUT;
when "1000" => LSEC18<=IOCTL_DOUT;
when "1001" => LSEC19<=IOCTL_DOUT;
when "1010" => LSEC1A<=IOCTL_DOUT;
when "1011" => LSEC1B<=IOCTL_DOUT;
when "1100" => LSEC1C<=IOCTL_DOUT;
when "1101" => LSEC1D<=IOCTL_DOUT;
when "1110" => LSEC1E<=IOCTL_DOUT;
when others => LSEC1F<=IOCTL_DOUT;
end case;
when "01010" => LSEL0 <=IOCTL_DOUT(3 downto 0); -- MZ_FDx_LSEL
when "01011" => LSEL1 <=IOCTL_DOUT(3 downto 0);
when "01100" => DDEN0 <=IOCTL_DOUT(0); -- MZ_FDx_DDEN
when "01101" => DDEN1 <=IOCTL_DOUT(0);
when "01110" => MAXSECT0 <=IOCTL_DOUT(3 downto 0); -- MZ_FDx_MAXS
when "01111" => MAXSECT1 <=IOCTL_DOUT(3 downto 0);
when "10000" => TRADR0(7 downto 0) <=IOCTL_DOUT; -- MZ_FDx_TA0
when "10010" => TRADR0(15 downto 8) <=IOCTL_DOUT; -- MZ_FDx_TA1
when "10100" => TRADR0(22 downto 16) <=IOCTL_DOUT(6 downto 0); -- MZ_FDx_TA2
when "10001" => TRADR1(7 downto 0) <=IOCTL_DOUT;
when "10011" => TRADR1(15 downto 8) <=IOCTL_DOUT;
when "10101" => TRADR1(22 downto 16) <=IOCTL_DOUT(6 downto 0);
when "11000" => GAP30 <=IOCTL_DOUT; -- MZ_FDx_G30
when "11001" => GAP31 <=IOCTL_DOUT;
when "11100" => GAP40(7 downto 0) <=IOCTL_DOUT; -- MZ_FDx_G40
when "11110" => GAP40(15 downto 8) <=IOCTL_DOUT; -- MZ_FDx_G41
when "11101" => GAP41(7 downto 0) <=IOCTL_DOUT;
when "11111" => GAP41(15 downto 8) <=IOCTL_DOUT;
when others =>
end case;
end if;
end if;
end process;
CS <= '1' when IOCTL_ADDR(15 downto 4)=REG_ADDR(15 downto 4) else '0';
RSEL <= IOCTL_ADDR(3 downto 0)&HSEL;
IOCTL_DIN <= "0000"&MF&D88&WP&DISK when IOCTL_RD='1' and CS='1' and IOCTL_ADDR(3 downto 0)="0000" else -- MZ_FDx_CTRL
"000000"&DIREC&REG_ST when IOCTL_RD='1' and CS='1' and IOCTL_ADDR(3 downto 0)="0010" else -- MZ_FDx_STEP
"00000000";
INTO <= REG_ST;
end RTL;

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--
-- fdunit.vhd
--
-- Floppy Disk Drive Unit Emulation module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fdunit is
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Step Pulse interrupt
-- FD signals
FCLK : in std_logic;
DS_n : in std_logic_vector(4 downto 1); -- Drive Select
HS : in std_logic; -- Head Select
MOTOR_n : in std_logic; -- Motor On
INDEX_n : out std_logic; -- Index Hole Detect
TRACK00 : out std_logic; -- Track 0
WPRT_n : out std_logic; -- Write Protect
STEP_n : in std_logic; -- Head Step In/Out
DIREC : in std_logic; -- Head Step Direction
WG_n : in std_logic; -- Write Gate
DTCLK : out std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Write Data
FDO : out std_logic_vector(7 downto 0); -- Read Data
-- Buffer RAM I/F
BCS_n : out std_logic; -- RAM Request
BADR : out std_logic_vector(22 downto 0); -- RAM Address
BWR_n : out std_logic; -- RAM Write Signal
BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end fdunit;
architecture RTL of fdunit is
--
-- Floppy Signals
--
signal RDO0 : std_logic_vector(7 downto 0);
signal RDO1 : std_logic_vector(7 downto 0);
signal IDX_0 : std_logic;
signal IDX_1 : std_logic;
signal TRK00_0 : std_logic;
signal TRK00_1 : std_logic;
signal WPRT_0 : std_logic;
signal WPRT_1 : std_logic;
signal FDO0 : std_logic_vector(7 downto 0);
signal FDO1 : std_logic_vector(7 downto 0);
signal DTCLK0 : std_logic;
signal DTCLK1 : std_logic;
--
-- Control
--
signal INT0 : std_logic;
signal INT1 : std_logic;
--
-- Memory Access
--
signal BCS0_n : std_logic;
signal BCS1_n : std_logic;
signal BADR0 : std_logic_vector(22 downto 0);
signal BADR1 : std_logic_vector(22 downto 0);
signal BWR0_n : std_logic;
signal BWR1_n : std_logic;
signal BDO0 : std_logic_vector(7 downto 0);
signal BDO1 : std_logic_vector(7 downto 0);
--
-- Component
--
component fd55b
generic
(
DS_SW : std_logic_vector(4 downto 1) := "1111";
REG_ADDR : std_logic_vector(15 downto 0) := "0000000000000000"
);
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Step Pulse interrupt
-- FD signals
FCLK : in std_logic;
DS_n : in std_logic_vector(4 downto 1); -- Drive Select
HS : in std_logic; -- Head Select
MOTOR_n : in std_logic; -- Motor On
INDEX_n : out std_logic; -- Index Hole Detect
TRACK00 : out std_logic; -- Track 0
WPRT_n : out std_logic; -- Write Protect
STEP_n : in std_logic; -- Head Step In/Out
DIREC : in std_logic; -- Head Step Direction
WG_n : in std_logic; -- Write Gate
DTCLK : out std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Write Data
FDO : out std_logic_vector(7 downto 0); -- Read Data
-- Buffer RAM I/F
BCS_n : out std_logic; -- RAM Request
BADR : out std_logic_vector(22 downto 0); -- RAM Address
BWR_n : out std_logic; -- RAM Write Signal
BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
begin
FDD0 : fd55b generic map (
DS_SW => "1110",
REG_ADDR => X"0040"
)
Port map (
RST_n => RST_n, -- Reset
CLK => CLK, -- System Clock
-- Interrupt
INTO => INT0, -- Step Pulse interrupt
-- FD signals
FCLK => FCLK,
DS_n => DS_n, -- Drive Select
HS => HS, -- Head Select
MOTOR_n => MOTOR_n, -- Motor On
INDEX_n => IDX_0, -- Index Hole Detect
TRACK00 => TRK00_0, -- Track 0
WPRT_n => WPRT_0, -- Write Protect
STEP_n => STEP_n, -- Head Step In/Out
DIREC => DIREC, -- Head Step Direction
WG_n => WG_n, -- Write Gate
DTCLK => DTCLK0, -- Data Clock
FDI => FDI, -- Write Data
FDO => FDO0, -- Read Data
-- Buffer RAM I/F
BCS_n => BCS0_n, -- RAM Request
BADR => BADR0, -- RAM Address
BWR_n => BWR0_n, -- RAM Write Signal
BDI => BDI, -- Data Bus Input from RAM
BDO => BDO0 -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
IOCTL_DIN => IOCTL_DIN, -- HPS Data to be read into HPS.
IOCTL_INTERRUPT => IOCTL_INTERRUPT -- HPS Interrupt.
);
FDD1 : fd55b generic map (
DS_SW => "1101",
REG_ADDR => X"0050"
)
Port map (
RST_n => RST_n, -- Reset
CLK => CLK, -- System Clock
-- Interrupt
INTO => INT1, -- Step Pulse interrupt
-- FD signals
FCLK => FCLK,
DS_n => DS_n, -- Drive Select
HS => HS, -- Head Select
MOTOR_n => MOTOR_n, -- Motor On
INDEX_n => IDX_1, -- Index Hole Detect
TRACK00 => TRK00_1, -- Track 0
WPRT_n => WPRT_1, -- Write Protect
STEP_n => STEP_n, -- Head Step In/Out
DIREC => DIREC, -- Head Step Direction
WG_n => WG_n, -- Write Gate
DTCLK => DTCLK1, -- Data Clock
FDI => FDI, -- Write Data
FDO => FDO1, -- Read Data
-- Buffer RAM I/F
BCS_n => BCS1_n, -- RAM Request
BADR => BADR1, -- RAM Address
BWR_n => BWR1_n, -- RAM Write Signal
BDI => BDI, -- Data Bus Input from RAM
BDO => BDO1 -- Data Bus Output to RAM
-- HPS Interface
IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
IOCTL_DIN => IOCTL_DIN, -- HPS Data to be read into HPS.
IOCTL_INTERRUPT => IOCTL_INTERRUPT -- HPS Interrupt.
);
INDEX_n <= IDX_0 and IDX_1;
TRACK00 <= TRK00_0 and TRK00_1;
WPRT_n <= WPRT_0 and WPRT_1;
FDO <= FDO0 or FDO1;
DTCLK <= DTCLK0 or DTCLK1;
BCS_n <= BCS0_n and BCS1_n;
BADR <= BADR0 or BADR1;
BWR_n <= BWR0_n and BWR1_n;
BDO <= BDO0 or BDO1;
RDO <= RDO0 or RDO1;
INTO <= INT0 or INT1;
end RTL;

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--
-- mb8876.vhd
--
-- Floppy Disk Controller partiality compatible module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014-2015
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mb8876 is
Port (
-- CPU Signals
ZCLK : in std_logic;
MR_n : in std_logic;
A : in std_logic_vector(1 downto 0); -- CPU Address Bus
RE_n : in std_logic; -- CPU Read Signal
WE_n : in std_logic; -- CPU Write Signal
CS_n : in std_logic; -- CPU Chip Select
DALI_n : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
DALO_n : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- DALI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
-- DALO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- FD signals
DDEN_n : in std_logic; -- Double Density
IP_n : in std_logic; -- Index Pulse
READY : in std_logic; -- Drive Ready
TR00_n : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP : out std_logic; -- Head Step In/Out
DIRC : out std_logic; -- Head Step Direction
WG : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end mb8876;
architecture RTL of mb8876 is
signal DALI : std_logic_vector(7 downto 0); -- non-inverted Data bus(input)
signal DALO : std_logic_vector(7 downto 0); -- non-inverted Data bus(output)
signal STS : std_logic_vector(7 downto 0); -- Command Register(backup for status)
signal TRACK : std_logic_vector(7 downto 0); -- Track Counter
signal SECTOR : std_logic_vector(7 downto 0); -- Sector Counter
signal GAPVAL : std_logic_vector(7 downto 0); -- Gap's Value
signal FDIR : std_logic_vector(7 downto 0); -- Bulk Data(pre registered)
signal FDR : std_logic_vector(7 downto 0); -- Bulk Data
signal WDATA : std_logic_vector(7 downto 0); -- Write Data
signal BCOUNT : std_logic_vector(9 downto 0); -- Byte Counter
signal DELAY : std_logic_vector(16 downto 0); -- Delay Counter
signal DCSET : std_logic_vector(16 downto 0); -- Next Delay Count Number
signal PCOUNT : std_logic_vector(4 downto 0); -- Step Pulse Width
signal BUSY : std_logic; -- Busy Flag
signal DIRC0 : std_logic; -- Step Direction(current)
signal DIRR : std_logic; -- Step Direction(registered)
signal E_SEEK : std_logic; -- Seek Error
signal E_RNF : std_logic; -- Record Not Found Error
signal E_RLOST : std_logic; -- Lost Data Error(read)
signal E_WLOST : std_logic; -- Lost Data Error(write)
signal IDXBUF : std_logic_vector(2 downto 0); -- Index Pulse Detect
signal DTBUF : std_logic_vector(2 downto 0); -- Data Enable Detect
signal FDEN : std_logic; -- Data Enable Detected
signal IDXC : std_logic_vector(2 downto 0); -- Index Pulse Counter
signal RDRQ : std_logic; -- Read Data Request
signal WDRQ : std_logic; -- Write Data Request
signal MOVING : std_logic; -- Head Stepping Flag
signal RFND0 : std_logic; -- Record Found Flag(process)
signal RFND : std_logic; -- Record Found Flag(result)
signal TFND : std_logic; -- Track Found Flag
signal CMPT : std_logic; -- Track Compared Flag
signal VFLAG : std_logic; -- Record Verify Flag
signal UFLAG : std_logic; -- Track Number Update Flag
signal CFLAG : std_logic; -- Side Compare Flag
signal MFLAG : std_logic; -- Multi Record Flag
signal SFLAG : std_logic; -- Side Flag
--
-- State Machine
--
signal CUR : std_logic_vector(5 downto 0);
signal NXT : std_logic_vector(5 downto 0);
constant IDLE : std_logic_vector(5 downto 0) := "000000";
constant REST : std_logic_vector(5 downto 0) := "000001";
--constant REST1 : std_logic_vector(5 downto 0) := "000010";
--constant REST2 : std_logic_vector(5 downto 0) := "000011";
constant SEEK0 : std_logic_vector(5 downto 0) := "000100";
constant SEEK1 : std_logic_vector(5 downto 0) := "000101";
constant SEEK2 : std_logic_vector(5 downto 0) := "000110";
constant STEP0 : std_logic_vector(5 downto 0) := "000111";
constant STEP1 : std_logic_vector(5 downto 0) := "001000";
constant STEP2 : std_logic_vector(5 downto 0) := "001001";
constant STIN0 : std_logic_vector(5 downto 0) := "001010";
constant STIN1 : std_logic_vector(5 downto 0) := "001011";
constant STIN2 : std_logic_vector(5 downto 0) := "001100";
constant STOT0 : std_logic_vector(5 downto 0) := "001101";
constant STOT1 : std_logic_vector(5 downto 0) := "001110";
constant STOT2 : std_logic_vector(5 downto 0) := "001111";
constant VTRK0 : std_logic_vector(5 downto 0) := "010000";
constant VTRK1 : std_logic_vector(5 downto 0) := "010001";
constant VTRK_ER : std_logic_vector(5 downto 0) := "010010";
constant RDAT0 : std_logic_vector(5 downto 0) := "010011";
constant RDAT1 : std_logic_vector(5 downto 0) := "010100";
constant RDAT2 : std_logic_vector(5 downto 0) := "010101";
constant RDAT3 : std_logic_vector(5 downto 0) := "010110";
constant RDAT4 : std_logic_vector(5 downto 0) := "010111";
constant RDAT5 : std_logic_vector(5 downto 0) := "011000";
constant WDAT0 : std_logic_vector(5 downto 0) := "011001";
constant WDAT1 : std_logic_vector(5 downto 0) := "011010";
constant WDAT2 : std_logic_vector(5 downto 0) := "011011";
constant WDAT3 : std_logic_vector(5 downto 0) := "011100";
constant WDAT4 : std_logic_vector(5 downto 0) := "011101";
constant WDAT5 : std_logic_vector(5 downto 0) := "011110";
constant RNF_ER : std_logic_vector(5 downto 0) := "011111";
constant RADR0 : std_logic_vector(5 downto 0) := "100000";
constant RADR1 : std_logic_vector(5 downto 0) := "100001";
constant RADR2 : std_logic_vector(5 downto 0) := "100010";
constant RADR3 : std_logic_vector(5 downto 0) := "100011";
constant CMDQ : std_logic_vector(5 downto 0) := "100100";
signal CUR2 : std_logic_vector(4 downto 0);
signal NXT2 : std_logic_vector(4 downto 0);
constant HUNT : std_logic_vector(4 downto 0) := "00000";
constant GAP1 : std_logic_vector(4 downto 0) := "00001";
constant SYNC1 : std_logic_vector(4 downto 0) := "00010";
constant ADM1 : std_logic_vector(4 downto 0) := "00011";
constant ID_TRK : std_logic_vector(4 downto 0) := "00100";
constant ID_HEAD : std_logic_vector(4 downto 0) := "00101";
constant ID_SECT : std_logic_vector(4 downto 0) := "00110";
constant ID_FMT : std_logic_vector(4 downto 0) := "00111";
constant CRC1_1 : std_logic_vector(4 downto 0) := "01000";
constant CRC1_2 : std_logic_vector(4 downto 0) := "01001";
constant GAP2_2 : std_logic_vector(4 downto 0) := "01010";
constant GAP2_1 : std_logic_vector(4 downto 0) := "01011";
constant GAP2 : std_logic_vector(4 downto 0) := "01100";
constant SYNC2 : std_logic_vector(4 downto 0) := "01101";
constant ADM2 : std_logic_vector(4 downto 0) := "01110";
constant DATA : std_logic_vector(4 downto 0) := "01111";
constant DATA_1 : std_logic_vector(4 downto 0) := "10000";
constant DATA_2 : std_logic_vector(4 downto 0) := "10001";
constant DATA_3 : std_logic_vector(4 downto 0) := "10010";
constant CRC2 : std_logic_vector(4 downto 0) := "10011";
begin
--
-- Step pulse and Seek wait
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
DELAY <= (others=>'0');
PCOUNT <= (others=>'0');
MOVING <= '0';
STEP <= '0';
elsif ZCLK'event and ZCLK='1' then
if DELAY="00000000000000000" then
if CUR=SEEK1 or CUR=STEP1 or CUR=STIN1 or CUR=STOT1 then
DELAY <= DCSET;
PCOUNT <= (others=>'1');
MOVING <= '1';
else
MOVING <= '0';
end if;
else
DELAY <= DELAY-'1';
if PCOUNT="00000" then
STEP <= '0';
else
STEP <= '1';
PCOUNT <= PCOUNT-'1';
end if;
end if;
end if;
end process;
--
-- Select Step Rate
--
process( STS(1 downto 0) ) begin
case STS(1 downto 0) is -- r0,r1
when "00" => DCSET<=conv_std_logic_vector(24000, 17); -- 6ms
when "10" => DCSET<=conv_std_logic_vector(48000, 17); -- 12ms
when "01" => DCSET<=conv_std_logic_vector(80000, 17); -- 20ms
when others => DCSET<=conv_std_logic_vector(120000, 17); -- 30ms
end case;
end process;
--
-- FD Data Sync
--
process( MR_n, ZCLK ) begin
-- process( MR_n, DTCLK ) begin
if MR_n='0' then
FDR<=(others=>'0');
CUR2<=HUNT;
BCOUNT<=(others=>'0');
elsif ZCLK'event and ZCLK='1' then
-- elsif DTCLK'event and DTCLK='1' then
-- FDIRR<=FDIR;
if FDEN='1' then
if MOVING='1' then
CUR2<=HUNT;
else
CUR2<=NXT2;
end if;
FDR<=FDI;
if CUR2=ID_FMT then
case FDR(1 downto 0) is
when "00" => BCOUNT<="0001111101";
when "01" => BCOUNT<="0011111101";
when "10" => BCOUNT<="0111111101";
when others => BCOUNT<="1111111101";
end case;
end if;
if CUR2=DATA then
BCOUNT<=BCOUNT-'1';
end if;
end if;
end if;
end process;
process( CUR2, IP_n, FDI, GAPVAL, BCOUNT ) begin
case CUR2 is
when HUNT =>
if IP_n='0' and FDI=GAPVAL then
NXT2<=GAP1;
else
NXT2<=HUNT;
end if;
when GAP1 =>
if FDI=X"00" then
NXT2<=SYNC1;
else
NXT2<=GAP1;
end if;
when SYNC1 =>
if FDI=X"FE" then
NXT2<=ADM1;
else
NXT2<=SYNC1;
end if;
when ADM1 =>
NXT2<=ID_TRK;
when ID_TRK =>
NXT2<=ID_HEAD;
when ID_HEAD =>
NXT2<=ID_SECT;
when ID_SECT =>
NXT2<=ID_FMT;
when ID_FMT =>
NXT2<=CRC1_1;
when CRC1_1 =>
NXT2<=CRC1_2;
when CRC1_2 =>
NXT2<=GAP2_2;
when GAP2_2 =>
NXT2<=GAP2_1;
when GAP2_1 =>
NXT2<=GAP2;
when GAP2 =>
if FDI=X"00" then
NXT2<=SYNC2;
else
NXT2<=GAP2;
end if;
when SYNC2 =>
if FDI=X"FB" then
NXT2<=DATA;
else
NXT2<=SYNC2;
end if;
when DATA =>
if BCOUNT="0000000000" then
NXT2<=DATA_1;
else
NXT2<=DATA;
end if;
when DATA_1 =>
NXT2<=DATA_2;
when DATA_2 =>
NXT2<=DATA_3;
when DATA_3 =>
NXT2<=CRC2;
when CRC2 =>
if FDI=GAPVAL then
NXT2<=GAP1;
else
NXT2<=CRC2;
end if;
when others =>
NXT2<=HUNT;
end case;
end process;
GAPVAL<=X"4E" when DDEN_n='0' else X"FF";
--
-- FD data sample timing
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
DTBUF<=(others=>'0');
FDEN<='0';
elsif ZCLK'event and ZCLK='1' then
DTBUF<=DTBUF(1 downto 0)&DTCLK;
if DTBUF(2 downto 1)="01" then
FDEN<='1';
else
FDEN<='0';
end if;
end if;
end process;
--
-- DRQ
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
E_RLOST<='0';
E_WLOST<='0';
RDRQ<='0';
WDRQ<='0';
elsif ZCLK'event and ZCLK='1' then
-- Reset
if CUR=RDAT0 then
E_RLOST<='0';
RDRQ<='0';
end if;
if CUR=WDAT0 then
E_WLOST<='0';
WDRQ<='0';
end if;
if CUR=CMDQ then
if RDRQ='1' then
E_RLOST<='1';
end if;
if WDRQ='1' then
E_WLOST<='1';
end if;
RDRQ<='0';
WDRQ<='0';
end if;
-- DRQ on (Read)
if (CUR=RDAT3 and (CUR2=DATA or CUR2=DATA_1 or CUR2=DATA_2)) or (CUR=RADR2 and (CUR2=ADM1 or CUR2=ID_TRK or CUR2=ID_HEAD or CUR2=ID_SECT or CUR2=ID_FMT or CUR2=CRC1_1)) then
if FDEN='1' then
RDRQ<='1';
if RDRQ='1' then
E_RLOST<='1';
end if;
end if;
end if;
-- Write
if CUR=WDAT3 and (CUR2=DATA or CUR2=GAP2_1 or (CUR2=SYNC2 and FDI=X"FB")) then
if FDEN='1' then
WDRQ<='1';
if WDRQ='1' then
E_WLOST<='1';
end if;
end if;
end if;
-- DRQ off
if CS_n='0' and A="11" then
if WE_n='1' then
-- Read
RDRQ<='0';
else
-- Write
WDRQ<='0';
end if;
end if;
end if;
end process;
--
-- Index Pulse Counter with ID check
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
IDXC<=(others=>'0');
IDXBUF<=(others=>'1');
RFND0<='0';
RFND<='0';
TFND<='0';
CMPT<='0';
elsif ZCLK'event and ZCLK='1' then
-- stand by
if CUR=VTRK0 then
TFND<='0';
CMPT<='0';
end if;
-- count or reset
IDXBUF<=IDXBUF(1 downto 0)&IP_n;
if CUR=RDAT0 or CUR=WDAT0 then
IDXC<=(others=>'0');
else
if IDXBUF(2 downto 1)="10" then
IDXC<=IDXC+'1';
end if;
end if;
-- find and compare ID
if FDEN='1' then
if CUR2=ID_TRK then
if FDR=TRACK then
RFND0<='1';
TFND<='1';
else
RFND0<='0';
TFND<='0';
end if;
CMPT<='1';
end if;
if CUR2=ID_HEAD then
if CFLAG='1' then
if FDR(0)/=SFLAG then
RFND0<='0';
end if;
end if;
end if;
if CUR2=ID_SECT then
if FDR=SECTOR then
if RFND0='1' then
IDXC<=(others=>'0');
end if;
else
RFND0<='0';
end if;
end if;
if CUR2=GAP2_2 then
RFND<=RFND0;
end if;
if CUR2=CRC2 then
RFND<='0';
end if;
end if;
end if;
end process;
--
-- Compatibility
--
DALI<=not DALI_n;
DALO_n<=not DALO when CS_n='0' and RE_n='0' else (others=>'0');
--
-- CPU Interface and State movement
--
process( MR_n, ZCLK ) begin
if MR_n='0' then
STS<=(others=>'0');
E_SEEK<='0';
E_RNF<='0';
TRACK<=(others=>'0');
SECTOR<=X"01";
WDATA<=(others=>'0');
CUR<=IDLE;
DIRR<='0';
FDO<=(others=>'0');
elsif ZCLK'event and ZCLK='1' then
-- Registers
if CS_n='0' then
if WE_n='0' then
case A is
when "00" =>
if DALI(7 downto 4)="1101" then
if BUSY='0' then
STS<=DALI;
end if;
else
STS<=DALI;
end if;
when "01" =>
if BUSY='0' then
TRACK<=DALI;
end if;
when "10" =>
if BUSY='0' then
SECTOR<=DALI;
end if;
when others =>
if CUR=WDAT3 then
FDO<=DALI;
else
WDATA<=DALI;
end if;
end case;
end if;
end if;
-- State Machine
if CS_n='0' and WE_n='0' and A="00" and DALI(7 downto 4)="1101" then
CUR<=CMDQ; -- Force Interrupt
else
CUR<=NXT;
end if;
--
-- Save Step Direction
if CUR=SEEK1 or CUR=STEP1 or CUR=STIN1 or CUR=STOT1 then
DIRR<=DIRC0;
end if;
-- Seek Error
if CUR=SEEK0 or CUR=STEP0 or CUR=STIN0 or CUR=STOT0 then
E_SEEK<='0';
end if;
if CUR=VTRK_ER then
E_SEEK<='1';
end if;
-- Restore
if CUR=REST then
TRACK<=(others=>'1');
WDATA<=(others=>'0');
end if;
-- Step
if (UFLAG='1' and (CUR=STIN1 or (CUR=STEP1 and DIRC0='1'))) or (CUR=SEEK1 and DIRC0='1') then
TRACK<=TRACK+'1';
elsif (UFLAG='1' and (CUR=STOT1 or (CUR=STEP1 and DIRC0='0'))) or (CUR=SEEK1 and DIRC0='0') then
TRACK<=TRACK-'1';
end if;
if (DIRC0='0' and (CUR=SEEK2 or CUR=STEP2)) or CUR=STOT2 then
if TR00_n='0' then
TRACK<=(others=>'0');
end if;
end if;
-- Multi Read/Write
if CUR=RDAT5 or CUR=WDAT5 then
SECTOR<=SECTOR+'1';
end if;
-- Record Not Found Error
if CUR=RDAT0 or CUR=WDAT0 then
E_RNF<='0';
end if;
if CUR=RNF_ER then
E_RNF<='1';
end if;
-- Read Address function
if CUR=RADR2 and CUR2=ID_TRK then
SECTOR<=FDR;
end if;
end if;
end process;
VFLAG<=STS(2);
UFLAG<=STS(4);
CFLAG<=STS(1);
MFLAG<=STS(4);
SFLAG<=STS(3);
--
-- State Machine
--
process( CUR, CS_n, WE_n, A, DALI(7 downto 4), TR00_n, VFLAG, MOVING, TRACK, WDATA, CMPT, TFND, RFND, DIRR, IDXC, MFLAG, E_RLOST , E_WLOST ) begin
case CUR is
when IDLE =>
if CS_n='0' and WE_n='0' and A="00" then
case DALI(7 downto 4) is
when "0000" => NXT<=REST;
when "0001" => NXT<=SEEK0;
when "0010"|"0011" => NXT<=STEP0;
when "0100"|"0101" => NXT<=STIN0;
when "0110"|"0111" => NXT<=STOT0;
when "1000"|"1001" => NXT<=RDAT0;
when "1010"|"1011" => NXT<=WDAT0;
when "1100" => NXT<=RADR0;
when others => NXT<=IDLE;
end case;
else
NXT<=IDLE;
end if;
-- TYPE I / Restore command
when REST =>
NXT<=SEEK1;
-- TYPE I / Seek command
when SEEK0 =>
if TRACK=WDATA then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=SEEK1;
end if;
when SEEK1 =>
NXT<=SEEK2;
when SEEK2 =>
if MOVING='0' then
NXT<=SEEK0;
else
NXT<=SEEK2;
end if;
-- TYPE I / Step command
when STEP0 =>
if DIRR='0' and TR00_n='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STEP1;
end if;
when STEP1 =>
NXT<=STEP2;
when STEP2 =>
if MOVING='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STEP2;
end if;
-- TYPE I / Step In command
when STIN0 =>
NXT<=STIN1;
when STIN1 =>
NXT<=STIN2;
when STIN2 =>
if MOVING='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STIN2;
end if;
-- TYPE I / Step Out command
when STOT0 =>
if TR00_n='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STOT1;
end if;
when STOT1 =>
NXT<=STOT2;
when STOT2 =>
if MOVING='0' then
if VFLAG='1' then
NXT<=VTRK0;
else
NXT<=CMDQ;
end if;
else
NXT<=STOT2;
end if;
-- Verify Track Number(TYPE I)
when VTRK0 =>
NXT<=VTRK1;
when VTRK1 =>
if CMPT='0' then
NXT<=VTRK1;
else
if TFND='0' then
NXT<=VTRK_ER;
else
NXT<=CMDQ;
end if;
end if;
when VTRK_ER =>
NXT<=CMDQ;
-- TYPE II / Read Data command
when RDAT0 =>
NXT<=RDAT1;
when RDAT1 =>
if CUR2=GAP1 then
NXT<=RDAT2;
else
NXT<=RDAT1;
end if;
when RDAT2 =>
if RFND='1' then
NXT<=RDAT3;
else
if IDXC="0110" then
NXT<=RNF_ER;
else
NXT<=RDAT2;
end if;
end if;
when RDAT3 =>
if E_RLOST='1' then
NXT<=CMDQ;
else
if CUR2=CRC2 then
NXT<=RDAT4;
else
NXT<=RDAT3;
end if;
end if;
when RDAT4 =>
if MFLAG='0' then
NXT<=CMDQ;
else
NXT<=RDAT5;
end if;
when RDAT5 =>
NXT<=RDAT0;
-- TYPE II / Write Data command
when WDAT0 =>
NXT<=WDAT1;
when WDAT1 =>
if CUR2=GAP1 then
NXT<=WDAT2;
else
NXT<=WDAT1;
end if;
when WDAT2 =>
if RFND='1' then
NXT<=WDAT3;
else
if IDXC="0110" then
NXT<=RNF_ER;
else
NXT<=WDAT2;
end if;
end if;
when WDAT3 =>
if E_WLOST='1' then
NXT<=CMDQ;
else
if CUR2=CRC2 then
NXT<=WDAT4;
else
NXT<=WDAT3;
end if;
end if;
when WDAT4 =>
if MFLAG='0' then
NXT<=CMDQ;
else
NXT<=WDAT5;
end if;
when WDAT5 =>
NXT<=WDAT0;
-- Record Not Found(TYPE II)
when RNF_ER =>
NXT<=CMDQ;
-- TYPE III / Read Address command
when RADR0 =>
NXT<=RADR1;
when RADR1 =>
if CUR2=GAP1 then
NXT<=RADR2;
else
NXT<=RADR1;
end if;
when RADR2 =>
if E_RLOST='1' then
NXT<=CMDQ;
else
-- if CUR2=CRC1_2 then
if CUR2=GAP2_2 then
-- NXT<=RADR3;
NXT<=CMDQ;
else
NXT<=RADR2;
end if;
end if;
-- when RADR3 =>
-- NXT<=RADR0;
when CMDQ =>
NXT<=IDLE;
when others =>
NXT<=IDLE;
end case;
end process;
--
-- State Action
--
-- Busy
BUSY<='0' when CUR=IDLE else '1';
-- Step Direction
process( CUR, TRACK, WDATA, DIRR ) begin
case CUR is
when SEEK0|SEEK1|SEEK2 =>
if TRACK>WDATA then
DIRC0<='0';
elsif TRACK<WDATA then
DIRC0<='1';
else
DIRC0<=DIRR;
end if;
when STEP0|STEP1|STEP2 =>
DIRC0<=DIRR;
when STIN0|STIN1|STIN2 =>
DIRC0<='1';
when STOT0|STOT1|STOT2 =>
DIRC0<='0';
when others=>
DIRC0<=DIRR;
end case;
end process;
-- Write Gate
WG<='1' when CUR=WDAT3 and (CUR2=DATA or CUR2=DATA_1 or (CUR2=SYNC2 and (FDI=X"FB" or FDR=X"FB"))) else '0';
DALO<= -- TYPE I Status
(not READY)&(not WPRT_n)&'1'&E_SEEK&'0'&(not TR00_n)&(not IP_n)&BUSY when A="00" and CS_n='0' and RE_n='0' and STS(7)='0' else
-- TYPE II Status
(not READY)&"00"&E_RNF&'0'&E_RLOST&RDRQ&BUSY when A="00" and CS_n='0' and RE_n='0' and (STS(7 downto 5)="100" or STS(7 downto 4)="1100") else
(not READY)&(not WPRT_n)&'0'&E_RNF&'0'&E_WLOST&WDRQ&BUSY when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 5)="101" else
-- TYPE III Status
-- (not READY)&"00"&E_RNF&'0'&E_RLOST&RDRQ&BUSY when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 4)="1100" else
-- TYPE IV Status
(not READY)&(not WPRT_n)&"100"&(not TR00_n)&(not IP_n)&'0' when A="00" and CS_n='0' and RE_n='0' and STS(7 downto 4)="1101" else
-- Registers
TRACK when A="01" and CS_n='0' and RE_n='0' else
SECTOR when A="10" and CS_n='0' and RE_n='0' else
FDR when A="11" and CS_n='0' and RE_n='0' and RDRQ='1' else
WDATA when A="11" and CS_n='0' and RE_n='0' else
-- Not Access
"00000000";
DIRC<=DIRC0;
end RTL;

183
mz80b/mz1e05.vhd Normal file
View File

@@ -0,0 +1,183 @@
--
-- mz1e05.vhd
--
-- Floppy Disk Interface Emulation module
-- for MZ-80B/2000 on FPGA
--
-- Nibbles Lab. 2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mz1e05 is
Port (
-- CPU Signals
ZRST_n : in std_logic;
ZCLK : in std_logic;
ZADR : in std_logic_vector(7 downto 0); -- CPU Address Bus(lower)
ZRD_n : in std_logic; -- CPU Read Signal
ZWR_n : in std_logic; -- CPU Write Signal
ZIORQ_n : in std_logic; -- CPU I/O Request
ZDI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
ZDO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
SCLK : in std_logic; -- Slow Clock
-- FD signals
DS_n : out std_logic_vector(4 downto 1); -- Drive Select
HS : out std_logic; -- Head Select
MOTOR_n : out std_logic; -- Motor On
INDEX_n : in std_logic; -- Index Hole Detect
TRACK00 : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP_n : out std_logic; -- Head Step In/Out
DIREC : out std_logic; -- Head Step Direction
WGATE_n : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end mz1e05;
architecture RTL of mz1e05 is
--
-- Signals
--
signal CSFDC_n : std_logic;
signal CSDC : std_logic;
signal CSDD : std_logic;
signal CSDE : std_logic;
signal DDEN : std_logic;
signal READY : std_logic;
signal STEP : std_logic;
signal DIRC : std_logic;
signal WG : std_logic;
signal RCOUNT : std_logic_vector(12 downto 0);
--
-- Component
--
component mb8876
Port (
-- CPU Signals
ZCLK : in std_logic;
MR_n : in std_logic;
A : in std_logic_vector(1 downto 0); -- CPU Address Bus
RE_n : in std_logic; -- CPU Read Signal
WE_n : in std_logic; -- CPU Write Signal
CS_n : in std_logic; -- CPU Chip Select
DALI_n : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
DALO_n : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- DALI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
-- DALO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- FD signals
DDEN_n : in std_logic; -- Double Density
IP_n : in std_logic; -- Index Pulse
READY : in std_logic; -- Drive Ready
TR00_n : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP : out std_logic; -- Head Step In/Out
DIRC : out std_logic; -- Head Step Direction
WG : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end component;
begin
--
-- Instantiation
--
FDC0 : mb8876 Port map(
-- CPU Signals
ZCLK => ZCLK,
MR_n => ZRST_n,
A => ZADR(1 downto 0), -- CPU Address Bus
RE_n => ZRD_n, -- CPU Read Signal
WE_n => ZWR_n, -- CPU Write Signal
CS_n => CSFDC_n, -- CPU Chip Select
DALI_n => ZDI, -- CPU Data Bus(in)
DALO_n => ZDO, -- CPU Data Bus(out)
-- DALI => ZDI, -- CPU Data Bus(in)
-- DALO => ZDO, -- CPU Data Bus(out)
-- FD signals
DDEN_n => DDEN, -- Double Density
IP_n => INDEX_n, -- Index Pulse
READY => READY, -- Drive Ready
TR00_n => TRACK00, -- Track 0
WPRT_n => WPRT_n, -- Write Protect
STEP => STEP, -- Head Step In/Out
DIRC => DIRC, -- Head Step Direction
WG => WG, -- Write Gate
DTCLK => DTCLK, -- Data Clock
FDI => FDI, -- Read Data
FDO => FDO -- Write Data
);
--
-- Registers
--
process( ZRST_n, ZCLK ) begin
if ZRST_n='0' then
MOTOR_n<='1';
HS<='0';
DS_n<="1111";
DDEN<='0';
elsif ZCLK'event and ZCLK='0' then
if ZWR_n='0' then
if CSDC='1' then
MOTOR_n<=not ZDI(7);
case ZDI(2 downto 0) is
when "100" => DS_n<="1110";
when "101" => DS_n<="1101";
when "110" => DS_n<="1011";
when "111" => DS_n<="0111";
when others => DS_n<="1111";
end case;
end if;
if CSDD='1' then
HS<=not ZDI(0);
end if;
if CSDE='1' then
DDEN<=ZDI(0);
end if;
end if;
end if;
end process;
CSFDC_n<='0' when ZIORQ_n='0' and ZADR(7 downto 2)="110110" else '1';
CSDC<='1' when ZIORQ_n='0' and ZADR=X"DC" else '0';
CSDD<='1' when ZIORQ_n='0' and ZADR=X"DD" else '0';
CSDE<='1' when ZIORQ_n='0' and ZADR=X"DE" else '0';
--
-- Ready Signal
--
process( ZRST_n, SCLK ) begin
if ZRST_n='0' then
RCOUNT<=(others=>'0');
READY<='0';
elsif SCLK'event and SCLK='0' then
if INDEX_n='0' then
RCOUNT<=(others=>'1');
else
if RCOUNT="0000000000000" then
READY<='0';
else
RCOUNT<=RCOUNT-'1';
READY<='1';
end if;
end if;
end if;
end process;
--
-- FDC signals
--
STEP_n<=not STEP;
DIREC<=not DIRC;
WGATE_n<=not WG;
end RTL;

697
mz80b/mz80b.vhd
View File

@@ -19,22 +19,23 @@
-- The tree is as follows;-
--
-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
-- | -> mz80c_video.vhd
-- | -> pcg.vhd
-- | -> cmt.vhd (this may move to common and be shared with mz80b)
-- |
-- |
-- | -> cmt.vhd (common)
-- | -> keymatrix.vhd (common)
-- | -> pll.v (common)
-- | -> clkgen.vhd (common)
-- | -> T80 (common)
-- | -> i8255 (common)
-- | -> i8253 (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- | -> i8254 (common)
-- | -> dpram.vhd (common)
-- | -> dprom.vhd (common)
-- | -> mctrl.vhd (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- | -> video.vhd (common)
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development)
--
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd
--
--
-- Credits:
@@ -61,6 +62,7 @@ library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.config_pkg.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
@@ -70,12 +72,11 @@ entity mz80b is
CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module.
-- Resets.
COLD_RESET : in std_logic;
SYSTEM_RESET : in std_logic;
-- Z80 CPU
T80_RST_n : in std_logic;
T80_CLK : in std_logic;
T80_CLKEN : out std_logic;
T80_WAIT_n : out std_logic;
T80_INT_n : out std_logic;
T80_NMI_n : out std_logic;
@@ -93,30 +94,38 @@ entity mz80b is
T80_DO : in std_logic_vector(7 downto 0);
-- Chip selects to common resources.
CS_ROM_n : out std_logic;
CS_RAM_n : out std_logic;
CS_ROM_n : out std_logic; -- ROM Select
CS_RAM_n : out std_logic; -- RAM Select
CS_VRAM_n : out std_logic; -- VRAM Select
CS_GRAM_n : out std_logic; -- Colour Graphics GRAM Select
CS_GRAM_80B_n : out std_logic; -- MZ80B GRAM Option Select
CS_IO_GFB_n : out std_logic; -- Graphics Framebuffer IO Select range
CS_IO_G_n : out std_logic; -- Graphics Options IO Select range
CS_SWP_MEMBANK_n : out std_logic; -- Move lower 32K into upper block.
-- Audio.
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
-- Video signals.
R : out std_logic;
G : out std_logic;
B : out std_logic;
HSYNC_n : out std_logic;
VSYNC_n : out std_logic;
HBLANK : out std_logic;
VBLANK : out std_logic;
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- I/O -- I/O down to the core.
PS2_KEY : in std_logic_vector(10 downto 0);
KEYB_SCAN : out std_logic_vector(3 downto 0); -- Keyboard scan lines out.
KEYB_DATA : in std_logic_vector(7 downto 0); -- Keyboard scan data in.
KEYB_STALL : out std_logic; -- Keyboard Stall out.
KEYB_BREAKDETECT : in std_logic; -- Keyboard break detect.
-- Cassette magnetic tape signals.
CMTBUS : out std_logic_vector(CMTBUS_WIDTH);
CMT_BUS_OUT : in std_logic_vector(CMT_BUS_OUT_WIDTH);
CMT_BUS_IN : out std_logic_vector(CMT_BUS_IN_WIDTH);
-- Video signals
VGATE_n : out std_logic; -- Video Gate enable.
INVERSE_n : out std_logic; -- Invert video output.
CONFIG_CHAR80 : out std_logic; -- 40 Char = 0, 80 Char = 1 select.
HBLANK : in std_logic; -- Horizontal Blanking Signal
VBLANK : in std_logic; -- Vertical Blanking Signal
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
@@ -125,8 +134,8 @@ entity mz80b is
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_DOUT : in std_logic_vector(31 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(31 downto 0); -- HPS Data to be read into HPS.
-- Debug Status Leds
DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status.
@@ -134,25 +143,625 @@ entity mz80b is
end mz80b;
architecture rtl of mz80b is
--
-- Decodes, misc
--
signal BOOTSTRAP_n : std_logic; -- Memory select, Low = ROM 0000 - 07FF, High = RAM 0000 - 7FFF
signal SEL_VRAM_ENABLE : std_logic; -- Enable VRAM/GRAM = 1.
signal SEL_VRAM_HIGHADDR : std_logic; -- Select VRAM as High (D000-FFFF) address, Low (5000-7FFF)
signal BST_n : std_logic;
signal NST : std_logic;
signal MZ_GRAM_ENABLE : std_logic;
signal CS_VRAM_ni : std_logic;
signal CS_IO_8255_n : std_logic;
signal CS_IO_8254_n : std_logic;
signal CS_IO_8254_RST_CLK_n : std_logic;
signal CS_IO_Z80PIO_n : std_logic;
signal CS_GRAM_ni : std_logic;
signal CS_GRAM_80B_ni : std_logic;
signal CS_IO_GRAMENABLE_n : std_logic;
signal CS_IO_GRAMDISABLE_n : std_logic;
signal CS_IO_GFB_ni : std_logic;
signal CS_IO_G_ni : std_logic;
signal CS_ROM_ni : std_logic;
signal CS_RAM_ni : std_logic;
signal T80_INT_ni : std_logic;
signal IRQ_CMT : std_logic;
signal IRQ_FDD : std_logic;
--
-- PPI
--
signal PPI_DO : std_logic_vector(7 downto 0);
signal i8255_PA_O : std_logic_vector(7 downto 0);
signal i8255_PA_OE_n : std_logic_vector(7 downto 0);
signal i8255_PB_I : std_logic_vector(7 downto 0);
signal i8255_PB_O : std_logic_vector(7 downto 0);
signal i8255_PC_O : std_logic_vector(7 downto 0);
signal i8255_PC_OE_n : std_logic_vector(7 downto 0);
--
-- PIT
--
signal PIT_DO : std_logic_vector(7 downto 0);
--
-- PIO
--
signal PIO_DO : std_logic_vector(7 downto 0);
signal Z80PIO_INT_n : std_logic;
signal Z80PIO_PA : std_logic_vector(7 downto 0);
signal Z80PIO_PB : std_logic_vector(7 downto 0);
--
-- Clocks
--
signal CASCADE01 : std_logic;
signal CASCADE12 : std_logic;
--
-- Video
--
signal HBLANKi : std_logic;
signal VBLANKi : std_logic;
signal HSYNC_ni : std_logic;
signal VSYNC_ni : std_logic;
signal Ri : std_logic;
signal Gi : std_logic;
signal Bi : std_logic;
signal VGATE_ni : std_logic; -- Video Outpu Enable
signal VRAM_DO : std_logic_vector(7 downto 0);
--
-- Keyboard.
--
signal LED_RVS : std_logic;
signal LED_GRPH : std_logic;
signal LED_SHIFT_LOCK : std_logic;
--
-- Audio
--
signal SOUND : std_logic;
--
-- FDD,FDC
--
signal DOFDC : std_logic_vector(7 downto 0);
signal DS : std_logic_vector(3 downto 0);
signal HS : std_logic;
signal MOTOR_n : std_logic;
signal INDEX_n : std_logic;
signal TRACK00_n : std_logic;
signal WPRT_n : std_logic;
signal STEP_n : std_logic;
signal DIREC : std_logic;
signal FDO : std_logic_vector(7 downto 0);
signal FDI : std_logic_vector(7 downto 0);
signal WGATE_n : std_logic;
signal DTCLK : std_logic;
--
-- Debug
--
signal PULSECPU : std_logic;
--
-- Components
--
component i8255
port (
RESET : in std_logic;
CLK : in std_logic;
ENA : in std_logic; -- (CPU) clk enable
ADDR : in std_logic_vector(1 downto 0); -- A1-A0
DI : in std_logic_vector(7 downto 0); -- D7-D0
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
PA_I : in std_logic_vector(7 downto 0);
PA_O : out std_logic_vector(7 downto 0);
PA_O_OE_n : out std_logic_vector(7 downto 0);
PB_I : in std_logic_vector(7 downto 0);
PB_O : out std_logic_vector(7 downto 0);
PB_O_OE_n : out std_logic_vector(7 downto 0);
PC_I : in std_logic_vector(7 downto 0);
PC_O : out std_logic_vector(7 downto 0);
PC_O_OE_n : out std_logic_vector(7 downto 0)
);
end component;
component i8254
Port (
RST : in std_logic;
CLK : in std_logic;
ENA : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
WR_n : in std_logic;
RD_n : in std_logic;
CLK0 : in std_logic;
GATE0 : in std_logic;
OUT0 : out std_logic;
CLK1 : in std_logic;
GATE1 : in std_logic;
OUT1 : out std_logic;
CLK2 : in std_logic;
GATE2 : in std_logic;
OUT2 : out std_logic
);
end component;
component z8420
Port (
-- System
RST_n : in std_logic; -- Only Power On Reset
-- Z80 Bus Signals
CLK : in std_logic;
ENA : in std_logic;
BASEL : in std_logic;
CDSEL : in std_logic;
CE : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
IORQ_n : in std_logic;
M1_n : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
IEI : in std_logic;
IEO : out std_logic;
INT_n : out std_logic;
-- Port
A : out std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0)
);
end component;
begin
T80_CLKEN <= '1';
T80_WAIT_n <= '1';
T80_INT_n <= '1';
T80_NMI_n <= '1';
T80_BUSRQ_n <= '1';
T80_DI <= (others => '0');
CS_ROM_n <= '1';
CS_RAM_n <= '1';
AUDIO_L <= '1';
AUDIO_R <= '1';
R <= '0';
G <= '0';
B <= '0';
HSYNC_n <= '0';
VSYNC_n <= '0';
HBLANK <= '0';
VBLANK <= '0';
CMTBUS <= (others => '0');
IOCTL_DIN <= (others => '0');
DEBUG_STATUS_LEDS <= (others => '0');
--
-- Instantiation
--
-- 8255 Used for Tape Control and interfacing and system boot control.
--
PPI0B : i8255
port map (
RESET => SYSTEM_RESET,
CLK => CLKBUS(CKMASTER),
ENA => CLKBUS(CKENCPU),
ADDR => T80_A16(1 downto 0),
DI => T80_DO,
DO => PPI_DO,
CS_n => CS_IO_8255_n,
RD_n => T80_RD_n,
WR_n => T80_WR_n,
PA_I => i8255_PA_O,
PA_O => i8255_PA_O,
PA_O_OE_n => i8255_PA_OE_n,
PB_I => i8255_PB_I,
PB_O => open,
PB_O_OE_n => open,
PC_I => i8255_PC_O,
PC_O => i8255_PC_O,
PC_O_OE_n => i8255_PC_OE_n
);
-- 8253 Timer used for the real time clock.
--
PIT0 : i8254
port map (
RST => SYSTEM_RESET,
CLK => CLKBUS(CKMASTER),
ENA => CLKBUS(CKENCPU),
A => T80_A16(1 downto 0),
DI => T80_DO,
DO => PIT_DO,
CS_n => CS_IO_8254_n,
WR_n => T80_WR_n,
RD_n => T80_RD_n,
CLK0 => CLKBUS(CKRTC),
GATE0 => CS_IO_8254_RST_CLK_n,
OUT0 => CASCADE01,
CLK1 => CASCADE01,
GATE1 => CS_IO_8254_RST_CLK_n,
OUT1 => CASCADE12,
CLK2 => CASCADE12,
GATE2 => '1',
OUT2 => open
);
-- Z80 PIO used for keyboard, RAM and Video control.
--
PIO0 : z8420
port map (
-- System
RST_n => T80_RST_n, -- Only Power On Reset
-- Z80 Bus Signals
CLK => CLKBUS(CKMASTER),
ENA => CLKBUS(CKENCPU),
BASEL => T80_A16(1),
CDSEL => T80_A16(0),
CE => CS_IO_Z80PIO_n,
RD_n => T80_RD_n,
WR_n => T80_WR_n,
IORQ_n => T80_IORQ_n,
M1_n => T80_M1_n and T80_RST_n,
DI => T80_DO,
DO => PIO_DO,
IEI => '1',
IEO => open,
INT_n => Z80PIO_INT_n,
A => Z80PIO_PA,
B => Z80PIO_PB
);
-- A1 clocked by C5, if A1 = L when C5 (SEEK) pulses high, then tape rewinds on activation of A0. If A1 is high, then
-- tape will fast forward. A0, when pulsed high, activates the motor to go forward/backward.
-- A2 pulsed high activates the play motor.which cancels a FF/REW event.
-- A3 when High, stops the Play/FF/REW events.
-- B5 when high indicates tape drive present and ready.
-- C4 when Low, ejects the tape.
-- C6 when Low enables record, otherwise whe High enables play.
-- C7 is the data to write to tape.
-- B6 is the data read from tape.
-- BW ehn Low blocks recording.
-- PPI Port A - Output connections.
--
LED_RVS <= i8255_PA_O(7) when i8255_PA_OE_n(7) = '0'
else '0';
LED_GRPH <= i8255_PA_O(6) when i8255_PA_OE_n(6) = '0'
else '0';
LED_SHIFT_LOCK <= i8255_PA_O(5) when i8255_PA_OE_n(5) = '0'
else '0';
INVERSE_n <= i8255_PA_O(4) when i8255_PA_OE_n(4) = '0'
else '1';
CMT_BUS_IN(STOP) <= i8255_PA_O(3) when i8255_PA_OE_n(3) = '0'
else '0';
CMT_BUS_IN(PLAY) <= i8255_PA_O(2) when i8255_PA_OE_n(2) = '0'
else '0';
CMT_BUS_IN(DIRECTION) <= i8255_PA_O(1) when i8255_PA_OE_n(1) = '0'
else '0';
CMT_BUS_IN(REEL_MOTOR) <= i8255_PA_O(0) when i8255_PA_OE_n(0) = '0'
else '0';
-- PPI Port B - Input connections.
--
i8255_PB_I(7) <= KEYB_BREAKDETECT;
i8255_PB_I(6) <= CMT_BUS_OUT(WRITEBIT); -- Tape is loaded in deck when L (0).
i8255_PB_I(5) <= CMT_BUS_OUT(TAPEREADY); -- Tape is loaded in deck when L (0).
i8255_PB_I(4) <= CMT_BUS_OUT(WRITEREADY); -- Prohibit Write when L (0).
i8255_PB_I(3 downto 1) <= (others => '1');
i8255_PB_I(0) <= VBLANK;
-- PPI Port C - Output connections. Feed output to input to be able to read latched value.
--
CMT_BUS_IN(READBIT) <= i8255_PC_O(7) when i8255_PC_OE_n(7) = '0'
else '0';
CMT_BUS_IN(WRITEENABLE) <= i8255_PC_O(6) when i8255_PC_OE_n(6) = '0'
else '0';
CMT_BUS_IN(SEEK) <= i8255_PC_O(5) when i8255_PC_OE_n(5) = '0'
else '0';
CMT_BUS_IN(EJECT) <= i8255_PC_O(4) when i8255_PC_OE_n(4) = '0'
else '0';
BST_n <= i8255_PC_O(3) when i8255_PC_OE_n(3) = '0'
else '1';
SOUND <= i8255_PC_O(2) when i8255_PC_OE_n(2) = '0'
else '0';
NST <= i8255_PC_O(1) when i8255_PC_OE_n(1) = '0'
else '0';
VGATE_ni <= i8255_PC_O(0) when i8255_PC_OE_n(0) = '0'
else '1';
-- Z80 PIO Port A - Output.
--
SEL_VRAM_ENABLE <= Z80PIO_PA(7);
SEL_VRAM_HIGHADDR <= Z80PIO_PA(6);
CONFIG_CHAR80 <= Z80PIO_PA(5);
KEYB_STALL <= Z80PIO_PA(4);
KEYB_SCAN <= Z80PIO_PA(3 downto 0);
-- Z80 PIO Port B - Input - Keyboard data.
--
Z80PIO_PB <= KEYB_DATA;
-- Parent signals onto local wires.
--
T80_BUSRQ_n <= '1';
T80_NMI_n <= '1';
T80_WAIT_n <= '1';
--
-- MZ-80B - Interrupts from the Z80PIO or external sources.
T80_INT_ni <= '0' when Z80PIO_INT_n = '0'
else '1';
T80_INT_n <= T80_INT_ni;
--
-- Data Bus Multiplexing, plex all the output devices onto the Z80 Data Input according to the CS.
--
T80_DI <= PPI_DO when CS_IO_8255_n ='0' and T80_RD_n = '0' -- Read from 8255
else
PIT_DO when CS_IO_8254_n ='0' and T80_RD_n = '0' -- Read from 8254
else
PIO_DO when CS_IO_Z80PIO_n='0' and T80_RD_n = '0' -- Read from Z80PIO
else
(others=>'1');
-- HPS Bus Multiplexing for reads.
IOCTL_DIN <= "00000000111111111100110010101010"; -- Test pattern.
--
-- Chip Select map.
--
-- 0000 - FFFF : MZ80B/2000 unless portion paged out by below selects.
-- 5000 - 5FFF : MZ80B = Alternate VRAM location
-- 6000 - 7FFF : MZ80B = Alternate GRAM location
-- C000 - FFFF : MZ2000 = GRAM
-- D000 - DFFF : MZ80B/2000 = VRAM
-- E000 - FFFF : MZ80B = GRAM
--
--
-- Video RAM Select.
-- 5000 - 5FFF
-- D000 - DFFF
CS_VRAM_ni <= -- D000 - DFFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "1101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
else
-- 5000 - 5FFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "0101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
else
-- D000 - DFFF
'0' when CONFIG(MZ2000) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 12) = "1101" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
else '1';
-- MZ80B/2000 Graphics RAM Select.
--
CS_GRAM_80B_ni <= -- E000 - FFFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 13) = "111" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
else
-- 6000 - 7FFF
'0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 13) = "011" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '1'
else
-- C000 - FFFF
'0' when CONFIG(MZ2000) = '1' and SEL_VRAM_ENABLE = '1' and T80_A16(15 downto 14) = "11" and T80_MREQ_n = '0' and SEL_VRAM_HIGHADDR = '0'
else '1';
-- Colour frame buffer.
-- C000 - FFFF
--
CS_GRAM_ni <= '0' when CONFIG(pkgs.mctrl_pkg.MZ80B) = '1' and MZ_GRAM_ENABLE = '1' and T80_A16(15 downto 14) = "11" and T80_MREQ_n='0'
else '1';
-- Boot ROM. Enabled only at startup when
--
-- 0000 -> 07FF when in IPL mode.
CS_ROM_ni <= '0' when BOOTSTRAP_n = '0' and T80_A16(15 downto 11) = "00000" and T80_MREQ_n = '0'
else '1';
--
CS_RAM_ni <= '0' when BOOTSTRAP_n = '0' and T80_A16(15) = '1' and CS_VRAM_ni = '1' and CS_GRAM_ni = '1' and CS_GRAM_80B_ni = '1' and T80_MREQ_n = '0'
else
'0' when BOOTSTRAP_n = '1' and CS_VRAM_ni = '1' and CS_GRAM_ni = '1' and CS_GRAM_80B_ni = '1' and T80_MREQ_n = '0'
else '1';
--
-- IO Select Map.
-- E0 - EF are used by the MZ80B/2000 to perform memory switching and graphics control.
-- F0-F3 write is used to set the gates of the 8254
-- F4-F7 is used to control the graphics options.
-- F8 is used to write the MSB of the Rom Expansion
-- F9 is used to write the LSB of the Rom Expansion and to read the data byte back.
--
-- IO Range for Graphics enhancements is set by the MCTRL DISPLAY2{7:3] register.
-- x[0|8],<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
-- x[1|9],<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- x[2|A],<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- x[3|B],<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- x[4|C] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. This overrides all MZ700 page switching functions.
-- x[5|D] switches out the graphics ram and returns to previous state.
--
CS_IO_8255_n <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111000" -- IO E0-E3 = 8255
else '1';
CS_IO_8254_n <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111001" -- IO E4-E7 = 8254
else '1';
CS_IO_Z80PIO_n <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111010" -- IO E8-EB = Z80PIO
else '1';
CS_IO_8254_RST_CLK_n<= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111100" and T80_WR_n = '0' -- IO F0-F3 = 8254 Clock reset.
else '1';
CS_IO_G_ni <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 2) = "111101" and T80_WR_n = '0' -- IO Range for Graphics framebuffer register controlled by mctrl register.
else '1';
CS_IO_GFB_ni <= '0' when T80_IORQ_n = '0' and T80_A16(7 downto 3) = CONFIG(GRAMIOADDR) and T80_WR_n = '0' -- IO Range for Graphics framebuffer register controlled by mctrl register.
else '1';
CS_IO_GRAMENABLE_n <= '0' when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "100" -- IO Addr base+4 sets C000 -> FFFF map to Graphics RAM.
else '1';
CS_IO_GRAMDISABLE_n <= '0' when CS_IO_GFB_ni = '0' and T80_A16(2 downto 0) = "101" -- IO Addr base+5 sets C000 -> FFFF revert to previous mode.
else '1';
-- Send signals to module interface.
--
CS_ROM_n <= CS_ROM_ni;
CS_RAM_n <= CS_RAM_ni;
CS_VRAM_n <= CS_VRAM_ni;
CS_GRAM_n <= CS_GRAM_ni;
CS_GRAM_80B_n <= CS_GRAM_80B_ni;
CS_IO_GFB_n <= CS_IO_GFB_ni;
CS_IO_G_n <= CS_IO_G_ni;
CS_SWP_MEMBANK_n <= BOOTSTRAP_n;
VGATE_n <= VGATE_ni;
-- On initial reset, BOOTSTRAP_n is set active, a reset setup and hold takes place, then the processor is set running with the
-- IPL monitor rom at 0000-07ff.
-- If NST goes High (due to the IPL setting it), then a flip flop is clocked setting BOOTSTRAP_n to inactive which places RAM
-- into the normal running state at 0000-7fff and the IPL monitor rom is disabled.
-- BOOT_RESET (external input) or BST_n when Low sets the BOOTSTRAP_n so that IPL mode is entered and the IPL monitor rom
-- is active at 0000.
--
process( COLD_RESET, CONFIG(BOOT_RESET), BST_n, CLKBUS(CKMASTER), NST )
begin
-- A cold reset sets up the initial state, further resets just reset variables as needed.
--
if COLD_RESET = '1' then
BOOTSTRAP_n <= '0';
elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
if CLKBUS(CKENCPU) = '1' then
if CONFIG(BOOT_RESET) = '1' or BST_n = '0' then
-- Only a boot reset or BST_n can set the BOOTSTRAP signal. A system reset just
-- resets the cpu and peripherals.
--
if CONFIG(BOOT_RESET) = '1' or BST_n = '0' then
BOOTSTRAP_n <= '0';
end if;
else
-- If the NST signal goes high, then reset the BOOTSTRAP signal. This signal can only be set
-- by a reset action.
--
if NST = '1' then
BOOTSTRAP_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- Graphics Ram - Latch wether to enable Graphics RAM page from C000 - FFFF.
--
process( SYSTEM_RESET, CLKBUS(CKMASTER), CS_IO_GRAMENABLE_n, CS_IO_GRAMDISABLE_n ) begin
if(SYSTEM_RESET = '1') then
MZ_GRAM_ENABLE <= '0';
elsif(CLKBUS(CKMASTER)'event and CLKBUS(CKMASTER)='1') then
if CLKBUS(CKENCPU) = '1' then
if(CS_IO_GRAMENABLE_n = '0') then
MZ_GRAM_ENABLE <= '0';
elsif(CS_IO_GRAMDISABLE_n = '0') then
MZ_GRAM_ENABLE <= '0';
end if;
end if;
end if;
end process;
-- Audio output. Choose between generated sound and CMT pulse audio.
--
AUDIO_L <= SOUND when CONFIG(AUDIOSRC) = '0' -- Sound Output Left
else
CMT_BUS_OUT(WRITEBIT);
AUDIO_R <= SOUND when CONFIG(AUDIOSRC) = '0' -- Sound Output Right
else
CMT_BUS_OUT(READBIT);
-- Only enable debugging LEDS if enabled in the config package.
--
DEBUG80B: if DEBUG_ENABLE = 1 generate
-- A simple 1*cpufreq second pulse to indicate accuracy of CPU frequency for debug purposes..
--
process (SYSTEM_RESET, CLKBUS(CKMASTER))
variable cnt : integer range 0 to 1999999 := 0;
begin
if SYSTEM_RESET = '1' then
PULSECPU <= '0';
cnt := 0;
elsif rising_edge(CLKBUS(CKMASTER)) then
if CLKBUS(CKENCPU) = '1' then
cnt := cnt + 1;
if cnt = 0 then
PULSECPU <= not PULSECPU;
end if;
end if;
end if;
end process;
-- Debug leds.
--
DEBUG_STATUS_LEDS(0) <= CS_VRAM_ni;
DEBUG_STATUS_LEDS(1) <= CS_GRAM_ni;
DEBUG_STATUS_LEDS(2) <= CS_GRAM_80B_ni;
DEBUG_STATUS_LEDS(3) <= CS_IO_8255_n;
DEBUG_STATUS_LEDS(4) <= CS_IO_8254_n;
DEBUG_STATUS_LEDS(5) <= CS_IO_Z80PIO_n;
DEBUG_STATUS_LEDS(6) <= CS_ROM_ni;
DEBUG_STATUS_LEDS(7) <= CS_RAM_ni;
--
DEBUG_STATUS_LEDS(8) <= '0';
DEBUG_STATUS_LEDS(9) <= CS_IO_8254_RST_CLK_n;
DEBUG_STATUS_LEDS(10) <= CS_IO_GRAMENABLE_n;
DEBUG_STATUS_LEDS(11) <= CS_IO_GRAMDISABLE_n;
DEBUG_STATUS_LEDS(12) <= CS_IO_GFB_ni;
DEBUG_STATUS_LEDS(13) <= CS_IO_G_ni;
DEBUG_STATUS_LEDS(14) <= '0';
DEBUG_STATUS_LEDS(15) <= '0';
--
DEBUG_STATUS_LEDS(16) <= BST_n;
DEBUG_STATUS_LEDS(17) <= NST;
DEBUG_STATUS_LEDS(18) <= MZ_GRAM_ENABLE;
DEBUG_STATUS_LEDS(19) <= BOOTSTRAP_n;
DEBUG_STATUS_LEDS(20) <= SEL_VRAM_ENABLE;
DEBUG_STATUS_LEDS(21) <= SEL_VRAM_HIGHADDR;
DEBUG_STATUS_LEDS(22) <= VGATE_ni;
DEBUG_STATUS_LEDS(23) <= CONFIG(BOOT_RESET);
--
DEBUG_STATUS_LEDS(24) <= PULSECPU;
DEBUG_STATUS_LEDS(25) <= T80_INT_ni;
DEBUG_STATUS_LEDS(26) <= '0';
DEBUG_STATUS_LEDS(27) <= COLD_RESET;
DEBUG_STATUS_LEDS(28) <= SYSTEM_RESET;
DEBUG_STATUS_LEDS(29) <= '0';
DEBUG_STATUS_LEDS(30) <= CONFIG(BOOT_RESET);
DEBUG_STATUS_LEDS(31) <= BST_n;
--
DEBUG_STATUS_LEDS(32) <= LED_RVS;
DEBUG_STATUS_LEDS(33) <= LED_GRPH;
DEBUG_STATUS_LEDS(34) <= LED_SHIFT_LOCK;
DEBUG_STATUS_LEDS(35) <= '0';
DEBUG_STATUS_LEDS(36) <= '0';
DEBUG_STATUS_LEDS(37) <= CASCADE01;
DEBUG_STATUS_LEDS(38) <= CASCADE12;
DEBUG_STATUS_LEDS(39) <= PULSECPU;
--
DEBUG_STATUS_LEDS(40) <= i8255_PA_O(0);
DEBUG_STATUS_LEDS(41) <= i8255_PA_O(1);
DEBUG_STATUS_LEDS(42) <= i8255_PA_O(2);
DEBUG_STATUS_LEDS(43) <= i8255_PA_O(3);
DEBUG_STATUS_LEDS(44) <= i8255_PA_O(4);
DEBUG_STATUS_LEDS(45) <= i8255_PA_O(5);
DEBUG_STATUS_LEDS(46) <= i8255_PA_O(6);
DEBUG_STATUS_LEDS(47) <= i8255_PA_O(7);
--
DEBUG_STATUS_LEDS(48) <= i8255_PB_I(0);
DEBUG_STATUS_LEDS(49) <= i8255_PB_I(1);
DEBUG_STATUS_LEDS(50) <= i8255_PB_I(2);
DEBUG_STATUS_LEDS(51) <= i8255_PB_I(3);
DEBUG_STATUS_LEDS(52) <= i8255_PB_I(4);
DEBUG_STATUS_LEDS(53) <= i8255_PB_I(5);
DEBUG_STATUS_LEDS(54) <= i8255_PB_I(6);
DEBUG_STATUS_LEDS(55) <= i8255_PB_I(7);
--
DEBUG_STATUS_LEDS(56) <= i8255_PC_O(0);
DEBUG_STATUS_LEDS(57) <= i8255_PC_O(1);
DEBUG_STATUS_LEDS(58) <= i8255_PC_O(2);
DEBUG_STATUS_LEDS(59) <= i8255_PC_O(3);
DEBUG_STATUS_LEDS(60) <= i8255_PC_O(4);
DEBUG_STATUS_LEDS(61) <= i8255_PC_O(5);
DEBUG_STATUS_LEDS(62) <= i8255_PC_O(6);
DEBUG_STATUS_LEDS(63) <= i8255_PC_O(7);
-- LEDS 64 .. 112 are available.
DEBUG_STATUS_LEDS(111 downto 64) <= (others => '0');
end generate;
end rtl;

169
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---------------------------------------------------------------------------------------------------------
--
-- Name: mz80b.vhd
-- Created: August 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Business Computer:
-- Models MZ-80B, MZ-2000
--
-- This module is the main (top level) container for the Business MZ Computer
-- Emulation.
--
-- The design tries to work from top-down, where components which are common
-- to the Business and Personal MZ series are at the top (ie. main memory,
-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
-- to the machine specific modules and components. Some components are common
-- by their nature (ie. 8255 PIO) but these are instantiated within the lower
-- tree branch as their design use is less generic.
--
-- The tree is as follows;-
--
-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
-- |
-- |
-- | -> cmt.vhd (common)
-- | -> keymatrix.vhd (common)
-- | -> pll.v (common)
-- | -> clkgen.vhd (common)
-- | -> T80 (common)
-- | -> i8255 (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- | -> i8253 (common)
-- | -> dpram.vhd (common)
-- | -> dprom.vhd (common)
-- | -> mctrl.vhd (common)
-- | -> video.vhd (common)
-- |
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development)
--
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: August 2018 - Initial module created.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
library pkgs;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use pkgs.clkgen_pkg.all;
use pkgs.mctrl_pkg.all;
entity mz80b is
PORT (
-- Clocks
CLKBUS : in std_logic_vector(CLKBUS_WIDTH); -- Clock signals created by clkgen module.
-- Resets.
SYSTEM_RESET : in std_logic;
-- Z80 CPU
T80_RST_n : in std_logic;
T80_CLK : in std_logic;
T80_CLKEN : out std_logic;
T80_WAIT_n : out std_logic;
T80_INT_n : out std_logic;
T80_NMI_n : out std_logic;
T80_BUSRQ_n : out std_logic;
T80_M1_n : in std_logic;
T80_MREQ_n : in std_logic;
T80_IORQ_n : in std_logic;
T80_RD_n : in std_logic;
T80_WR_n : in std_logic;
T80_RFSH_n : in std_logic;
T80_HALT_n : in std_logic;
T80_BUSAK_n : in std_logic;
T80_A16 : in std_logic_vector(15 downto 0);
T80_DI : out std_logic_vector(7 downto 0);
T80_DO : in std_logic_vector(7 downto 0);
-- Chip selects to common resources.
CS_ROM_n : out std_logic; -- ROM Select
CS_RAM_n : out std_logic; -- RAM Select
CS_VRAM_n : out std_logic; -- VRAM Select
CS_MEM_G_n : out std_logic; -- Memory mapped Peripherals Select
CS_GRAM_n : out std_logic; -- GRAM Select
CS_GRAM_80B_n : out std_logic; -- GRAM Select
CS_IO_G_n : out std_logic; -- Graphics FB IO Select range
CS_SWP_MEMBANK_n : out std_logic;
-- Audio.
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
-- Different operations modes.
CONFIG : in std_logic_vector(CONFIG_WIDTH);
-- I/O -- I/O down to the core.
KEYB_SCAN : out std_logic_vector(3 downto 0); -- Keyboard scan lines out.
KEYB_DATA : in std_logic_vector(7 downto 0); -- Keyboard scan data in.
KEYB_STALL : out std_logic; -- Keyboard Stall out.
-- Cassette magnetic tape signals.
CMT_BUS_OUT : in std_logic_vector(CMT_BUS_OUT_WIDTH);
CMT_BUS_IN : out std_logic_vector(CMT_BUS_IN_WIDTH);
-- Video signals
VGATE_n : out std_logic; -- Video Gate enable.
INVERSE : out std_logic; -- Invert video output.
CHAR80 : out std_logic; --
HBLANK : in std_logic; -- Horizontal Blanking Signal
VBLANK : in std_logic; -- Vertical Blanking Signal
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_UPLOAD : in std_logic; -- HPS Uploading from FPGA.
IOCTL_CLK : in std_logic; -- HPS I/O Clock.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
-- Debug Status Leds
DEBUG_STATUS_LEDS : out std_logic_vector(111 downto 0) -- 112 leds to display status.
);
end mz80b;
architecture rtl of mz80b is
begin
T80_CLKEN <= '1';
T80_WAIT_n <= '1';
T80_INT_n <= '1';
T80_NMI_n <= '1';
T80_BUSRQ_n <= '1';
T80_DI <= (others => '0');
CS_ROM_n <= '1';
CS_RAM_n <= '1';
CS_VRAM_n <= '1';
CS_MEM_G_n <= '1';
CS_GRAM_n <= '1';
CS_GRAM_80B_n <= '1';
CS_IO_G_n <= '1';
CS_SWP_MEMBANK_n <= '1';
AUDIO_L <= '1';
AUDIO_R <= '1';
VGATE_n <= '1';
INVERSE <= '0';
CHAR80 <= '0';
CMT_BUS_IN(MOTORON)<= '0';
CMT_BUS_IN(READBIT)<= '0';
IOCTL_DIN <= (others => '0');
DEBUG_STATUS_LEDS <= (others => '0');
end rtl;

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--
-- mz80b_video.vhd
--
-- Video display signal generator
-- for MZ-80B on FPGA
--
-- Nibbles Lab. 2013-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mz80b_video is
Port (
RST_n : in std_logic; -- Reset
BOOTM : in std_logic; -- BOOT Mode
-- Type of machine we are emulating.
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
-- Type of display to emulate.
DISPLAY_NORMAL : in std_logic;
DISPLAY_NIDECOM : in std_logic;
DISPLAY_GAL5 : in std_logic;
DISPLAY_COLOUR : in std_logic;
-- Different operations modes.
CONFIG_PCGRAM : in std_logic; -- PCG Mode Switch, 0 = CGROM, 1 = CGRAM.
-- Clocks
CK16M : in std_logic; -- 15.6kHz Dot Clock(16MHz)
T80_CLK_n : in std_logic; -- Z80 Current Clock
T80_CLK : in std_logic; -- Z80 Current Clock Inverted
-- CPU Signals
T80_A : in std_logic_vector(13 downto 0); -- CPU Address Bus
CSV_n : in std_logic; -- CPU Memory Request(VRAM)
CSG_n : in std_logic; -- CPU Memory Request(GRAM)
T80_RD_n : in std_logic; -- CPU Read Signal
T80_WR_n : in std_logic; -- CPU Write Signal
T80_MREQ_n : in std_logic; -- CPU Memory Request
T80_BUSACK_n : in std_logic; -- CPU Bus Acknowledge
T80_WAIT_n : out std_logic; -- CPU Wait Request
T80_DI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
T80_DO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- Graphic VRAM Access
GCS_n : out std_logic; -- GRAM Request
GADR : out std_logic_vector(20 downto 0); -- GRAM Address
GT80_WR_n : out std_logic; -- GRAM Write Signal
GBE_n : out std_logic_vector(3 downto 0); -- GRAM Byte Enable
GDI : in std_logic_vector(31 downto 0); -- Data Bus Input from GRAM
GDO : out std_logic_vector(31 downto 0); -- Data Bus Output to GRAM
-- Video Control from outside
INV : in std_logic; -- Reverse mode(8255 PA4)
VGATE : in std_logic; -- Video Output Control(8255 PC0)
CH80 : in std_logic; -- Text Character Width(Z80PIO A5)
-- Video Signals
VGATE_n : in std_logic; -- Video Output Control
HBLANK : out std_logic; -- Horizontal Blanking
VBLANK : out std_logic; -- Vertical Blanking
HSYNC_n : out std_logic; -- Horizontal Sync
VSYNC_n : out std_logic; -- Vertical Sync
ROUT : out std_logic; -- Red Output
GOUT : out std_logic; -- Green Output
BOUT : out std_logic; -- Green Output
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0) -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end mz80b_video;
architecture RTL of mz80b_video is
--
-- Registers
--
signal DIV : std_logic_vector(8 downto 0); -- Clock Divider
signal HCOUNT : std_logic_vector(9 downto 0); -- Counter for Horizontal Signals
signal VCOUNT : std_logic_vector(8 downto 0); -- Counter for Vertical Signals
signal VADR : std_logic_vector(10 downto 0); -- VRAM Address(selected)
signal VADRC : std_logic_vector(10 downto 0); -- VRAM Address
signal GADRC : std_logic_vector(13 downto 0); -- GRAM Address
signal GADRi : std_logic_vector(13 downto 0); -- GRAM Address(for GRAM Access)
signal VADRL : std_logic_vector(10 downto 0); -- VRAM Address(latched)
signal SDAT : std_logic_vector(7 downto 0); -- Shift Register to Display
signal SDATB : std_logic_vector(7 downto 0); -- Shift Register to Display
signal SDATR : std_logic_vector(7 downto 0); -- Shift Register to Display
signal SDATG : std_logic_vector(7 downto 0); -- Shift Register to Display
signal S2DAT : std_logic_vector(7 downto 0); -- Shift Register to Display(for 40-char)
signal S2DAT0 : std_logic_vector(7 downto 0); -- Shift Register to Display(for 80B)
signal S2DAT1 : std_logic_vector(7 downto 0); -- Shift Register to Display(for 80B)
--
-- CPU Access
--
signal MA : std_logic_vector(11 downto 0); -- Masked Address
signal CSB4_x : std_logic; -- Chip Select (PIO-3039 Color Board)
signal CSF4_x : std_logic; -- Chip Select (Background Color)
signal CSF5_x : std_logic; -- Chip Select (Display Select for C-Monitor)
signal CSF6_x : std_logic; -- Chip Select (Display Select for G-Monitor)
signal CSF7_x : std_logic; -- Chip Select (GRAM Select)
signal GCSi_x : std_logic; -- Chip Select (GRAM)
signal RCSV : std_logic; -- Chip Select (VRAM, NiosII)
signal RCSC : std_logic; -- Chip Select (CGROM, NiosII)
signal VWEN : std_logic; -- WR + MREQ (VRAM)
signal RVWEN : std_logic; -- WR + CS (VRAM, NiosII)
signal RCWEN : std_logic; -- WR + CS (CGROM, NiosII)
signal WAITi_n : std_logic; -- Wait
signal WAITii_n : std_logic; -- Wait(delayed)
signal ZGBE_n : std_logic_vector(3 downto 0); -- Byte Enable by Z80 access
--
-- Internal Signals
--
signal HDISPEN : std_logic; -- Display Enable for Horizontal, almost same as HBLANK
signal HBLANKi : std_logic; -- Horizontal Blanking
signal BLNK : std_logic; -- Horizontal Blanking (for wait)
signal XBLNK : std_logic; -- Horizontal Blanking (for wait)
signal VDISPEN : std_logic; -- Display Enable for Vertical, same as VBLANK
signal MB : std_logic; -- Display Signal (Mono, Blue)
signal MG : std_logic; -- Display Signal (Mono, Green)
signal MR : std_logic; -- Display Signal (Mono, Red)
signal BB : std_logic; -- Display Signal (Color, Blue)
signal BG : std_logic; -- Display Signal (Color, Green)
signal BR : std_logic; -- Display Signal (Color, Red)
signal PBGR : std_logic_vector(2 downto 0); -- Display Signal (Color)
signal POUT : std_logic_vector(2 downto 0); -- Display Signal (Color)
signal VRAMDO : std_logic_vector(7 downto 0); -- Data Bus Output for VRAM
signal DCODE : std_logic_vector(7 downto 0); -- Display Code, Read From VRAM
signal CGDAT : std_logic_vector(7 downto 0); -- Font Data To Display
signal CGADR : std_logic_vector(10 downto 0); -- Font Address To Display
signal CCOL : std_logic_vector(2 downto 0); -- Character Color
signal BCOL : std_logic_vector(2 downto 0); -- Background Color
signal CCOLi : std_logic_vector(2 downto 0); -- Character Color(reg)
signal BCOLi : std_logic_vector(2 downto 0); -- Background Color(reg)
signal GPRI : std_logic;
signal GPAGE : std_logic_vector(2 downto 0);
signal GPAGEi : std_logic_vector(2 downto 0);
signal GDISPEN : std_logic;
signal GDISPENi : std_logic;
signal GBANK : std_logic_vector(1 downto 0);
signal INVi : std_logic;
signal VGATEi : std_logic;
signal GRAMBDI : std_logic_vector(7 downto 0); -- Data from GRAM(Blue)
signal GRAMRDI : std_logic_vector(7 downto 0); -- Data from GRAM(Red)
signal GRAMGDI : std_logic_vector(7 downto 0); -- Data from GRAM(Green)
signal CH80i : std_logic;
signal CDISPEN : std_logic;
signal PALET0 : std_logic_vector(2 downto 0);
signal PALET1 : std_logic_vector(2 downto 0);
signal PALET2 : std_logic_vector(2 downto 0);
signal PALET3 : std_logic_vector(2 downto 0);
signal PALET4 : std_logic_vector(2 downto 0);
signal PALET5 : std_logic_vector(2 downto 0);
signal PALET6 : std_logic_vector(2 downto 0);
signal PALET7 : std_logic_vector(2 downto 0);
--
-- Components
--
component dprom
GENERIC (
init_file : string;
widthad_a : natural;
width_a : natural
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_b : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_b : IN STD_LOGIC;
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
end component;
component dpram
generic (
init_file : string;
widthad_a : natural;
width_a : natural
);
Port (
clock_a : in std_logic ;
clocken_a : in std_logic := '1';
address_a : in std_logic_vector (widthad_a-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0);
wren_a : in std_logic;
q_a : out std_logic_vector (width_a-1 downto 0);
clock_b : in std_logic ;
clocken_b : in std_logic := '1';
address_b : in std_logic_vector (widthad_a-1 downto 0);
data_b : in std_logic_vector (width_a-1 downto 0);
wren_b : in std_logic;
q_b : out std_logic_vector (width_a-1 downto 0)
);
end component;
component cgrom
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
component dpram2k
PORT
(
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
VRAM0 : dpram
GENERIC MAP (
init_file => "./roms/MZFONT.mif",
widthad_a => 11,
width_a => 8
)
PORT MAP (
clock_a => CK8M,
clocken_a => CK16M,
address_a => VADR,
data_a => T80_DI,
wren_a => VWEN,
q_a => VRAMDO,
clock_b => CK16M,
clocken_b => IOCTL_CSVVRAM_n,
address_b => IOCTL_ADDR(10 DOWNTO 0),
data_b => IOCTL_DOUT(7 DOWNTO 0),
wren_b => RVWEN, --IOCTL_WR,
q_b => open
);
CGROM0 : dprom
GENERIC MAP (
init_file => "./roms/MZ80K_cgrom.mif",
widthad_a => 11,
width_a => 8
)
PORT MAP (
address_a => CGADR,
clock_a => CK16M,
data_a => IOCTL_DOUT(7 DOWNTO 0),
wren_a => '0',
q_a => CGDAT,
address_b => IOCTL_ADDR(10 DOWNTO 0),
clock_b => IOCTL_CSCGROM_n,
data_b => IOCTL_DOUT(7 DOWNTO 0),
wren_b => ROWEN,--IOCTL_WR
q_b => open
);
--
-- Blank & Sync Generation
--
process( RST_n, CK16M ) begin
if RST_n='0' then
HCOUNT <= "1111111000";
HBLANKi <= '0';
HDISPEN <= '0';
BLNK <= '0';
HSYNC_n <= '1';
VDISPEN <= '1';
VSYNC_n <= '1';
GCSi_x <= '1';
VADRC <= (others=>'0');
GADRC <= (others=>'0');
VADRL <= (others=>'0');
elsif CK16M'event and CK16M='1' then
-- Counters
if HCOUNT=1015 then
--HCOUNT<=(others=>'0');
HCOUNT <= "1111111000";
VADRC <= VADRL; -- Return to Most-Left-Column Address
if VCOUNT=259 then
VCOUNT <= (others=>'0');
VADRC <= (others=>'0'); -- Home Position
GADRC <= (others=>'0'); -- Home Position
VADRL <= (others=>'0');
else
VCOUNT <= VCOUNT+'1';
end if;
else
HCOUNT <= HCOUNT+'1';
end if;
-- Horizontal Signals Decode
if HCOUNT=0 then
HDISPEN <= VDISPEN; -- if V-DISP is Enable then H-DISP Start
elsif HCOUNT=632 then
HBLANKi <= '1'; -- H-Blank Start
BLNK <= '1';
elsif HCOUNT=640 then
HDISPEN <= '0'; -- H-DISP End
elsif HCOUNT=768 then
HSYNC_n <= '0'; -- H-Sync Pulse Start
elsif HCOUNT=774 and VCOUNT(2 downto 0)="111" then
VADRL <= VADRC; -- Save Most-Left-Column Address
elsif HCOUNT=859 then
HSYNC_n <= '1'; -- H-Sync Pulse End
elsif HCOUNT=992 then
BLNK <= '0';
elsif HCOUNT=1015 then
HBLANKi <= '0'; -- H-Blank End
end if;
-- VRAM Address counter(per 8dot)
if HBLANKi='0' then
if (HCOUNT(2 downto 0)="111" and CH80i='1') or (HCOUNT(3 downto 0)="1111" and CH80i='0') then
VADRC <= VADRC+'1';
end if;
if (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
GADRC <= GADRC+'1';
end if;
end if;
-- Graphics VRAM Access signal
if HBLANKi='0' then
if (HCOUNT(2 downto 0)="000" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1000" and MODE_MZ80B='1') then
GCSi_x <= '0';
elsif (HCOUNT(2 downto 0)="111" and MODE_MZ2000='1') or (HCOUNT(3 downto 0)="1111" and MODE_MZ80B='1') then
GCSi_x <= '1';
end if;
else
GCSi_x <= '1';
end if;
-- Get Font/Pattern data and Shift
if HCOUNT(3 downto 0)="0000" then
if CH80i='1' then
SDAT <= CGDAT;
else
SDAT <= CGDAT(7)&CGDAT(7)&CGDAT(6)&CGDAT(6)&CGDAT(5)&CGDAT(5)&CGDAT(4)&CGDAT(4);
S2DAT <= CGDAT(3)&CGDAT(3)&CGDAT(2)&CGDAT(2)&CGDAT(1)&CGDAT(1)&CGDAT(0)&CGDAT(0);
end if;
if MODE_MZ2000='1' then
SDATB <= GRAMBDI;
SDATR <= GRAMRDI;
SDATG <= GRAMGDI;
else
SDATB <= GRAMBDI(3)&GRAMBDI(3)&GRAMBDI(2)&GRAMBDI(2)&GRAMBDI(1)&GRAMBDI(1)&GRAMBDI(0)&GRAMBDI(0);
S2DAT0 <= GRAMBDI(7)&GRAMBDI(7)&GRAMBDI(6)&GRAMBDI(6)&GRAMBDI(5)&GRAMBDI(5)&GRAMBDI(4)&GRAMBDI(4);
SDATR <= GRAMRDI(3)&GRAMRDI(3)&GRAMRDI(2)&GRAMRDI(2)&GRAMRDI(1)&GRAMRDI(1)&GRAMRDI(0)&GRAMRDI(0);
S2DAT1 <= GRAMRDI(7)&GRAMRDI(7)&GRAMRDI(6)&GRAMRDI(6)&GRAMRDI(5)&GRAMRDI(5)&GRAMRDI(4)&GRAMRDI(4);
end if;
elsif HCOUNT(3 downto 0)="1000" then
if CH80i='1' then
SDAT <= CGDAT;
else
SDAT <= S2DAT;
end if;
if MODE_MZ2000='1' then
SDATB <= GRAMBDI;
SDATR <= GRAMRDI;
SDATG <= GRAMGDI;
else
SDATB <= S2DAT0;
SDATR <= S2DAT1;
end if;
else
SDAT <= SDAT(6 downto 0)&'0';
SDATB <= '0'&SDATB(7 downto 1);
SDATR <= '0'&SDATR(7 downto 1);
SDATG <= '0'&SDATG(7 downto 1);
end if;
-- Vertical Signals Decode
if VCOUNT=0 then
VDISPEN <= '1'; -- V-DISP Start
elsif VCOUNT=200 then
VDISPEN <= '0'; -- V-DISP End
elsif VCOUNT=219 then
VSYNC_n <= '0'; -- V-Sync Pulse Start
elsif VCOUNT=223 then
VSYNC_n <= '1'; -- V-Sync Pulse End
end if;
end if;
end process;
--
-- Control Registers
--
process( RST_n, T80_CLK ) begin
if RST_n='0' then
BCOLi <= (others=>'0');
CCOLi <= (others=>'1');
GPRI <= '0';
GPAGEi <= "000";
GDISPENi <= '0';
CDISPEN <= '1';
GBANK <= "00";
PALET0 <= "000";
PALET1 <= "111";
PALET2 <= "111";
PALET3 <= "111";
PALET4 <= "111";
PALET5 <= "111";
PALET6 <= "111";
PALET7 <= "111";
elsif T80_CLK'event and T80_CLK='0' then
if T80_WR_n='0' then
if MODE_MZ2000='1' then -- MZ-2000
-- Background Color
if CSF4_x='0' then
BCOLi <= T80_DI(2 downto 0);
end if;
-- Character Color and Priority
if CSF5_x='0' then
CCOLi <= T80_DI(2 downto 0);
GPRI <= T80_DI(3);
end if;
-- Display Graphics and Pages
if CSF6_x='0' then
GPAGEi <= T80_DI(2 downto 0);
GDISPENi <= not T80_DI(3);
end if;
-- Select Accessable Graphic Banks
if CSF7_x='0' then
GBANK <= T80_DI(1 downto 0);
end if;
else -- MZ-80B
-- Color Control(PIO-3039)
if CSB4_x='0' then
if T80_DI(6)='1' then
CDISPEN <= T80_DI(7);
else
case T80_DI(2 downto 0) is
when "000" => PALET0<=T80_DI(5 downto 3);
when "001" => PALET1<=T80_DI(5 downto 3);
when "010" => PALET2<=T80_DI(5 downto 3);
when "011" => PALET3<=T80_DI(5 downto 3);
when "100" => PALET4<=T80_DI(5 downto 3);
when "101" => PALET5<=T80_DI(5 downto 3);
when "110" => PALET6<=T80_DI(5 downto 3);
when "111" => PALET7<=T80_DI(5 downto 3);
when others => PALET0<=T80_DI(5 downto 3);
end case;
end if;
end if;
-- Select Accessable Graphic Banks and Outpu Pages
if CSF4_x='0' then
GBANK <= T80_DI(0)&(not T80_DI(0));
GPAGEi(1 downto 0)<=T80_DI(2 downto 1);
end if;
end if;
end if;
end if;
end process;
--
-- Timing Conditioning and Wait
--
process( T80_MREQ_n ) begin
if T80_MREQ_n'event and T80_MREQ_n='0' then
XBLNK<=BLNK;
end if;
end process;
process( T80_CLK ) begin
if T80_CLK'event and T80_CLK='1' then
WAITii_n<=WAITi_n;
end if;
end process;
WAITi_n<='0' when (CSV_n='0' or CSG_n='0') and XBLNK='0' and BLNK='0' else '1';
T80_WAIT_n<=WAITi_n and WAITii_n;
--
-- Mask by Mode
--
ZGBE_n <= "1110" when GBANK="01" else
"1101" when GBANK="10" else
"1011" when GBANK="11" else "1111";
GBE_n <= ZGBE_n when BLNK='1' else "1000";
GT80_WR_n <= T80_WR_n when BLNK='1' else '1';
GCS_n <= CSG_n when BLNK='1' else GCSi_x;
RCSV <= '0' when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11010" else '1';
RCSC <='0' when IOCTL_INDEX="01000000" and IOCTL_ADDR(15 downto 11)="11001" else '1';
VWEN <='1' when T80_WR_n='0' and CSV_n='0' and BLNK='1' else '0';
RVWEN <= not(IOCTL_WR='1' or RCSV);
RCWEN <= not(IOCTL_WR='1' or RCSC);
CSB4_x <= '0' when T80_A(7 downto 0)=X"B4" and T80_IORQ_n='0' else '1';
CSF4_x <= '0' when T80_A(7 downto 0)=X"F4" and T80_IORQ_n='0' else '1';
CSF5_x <= '0' when T80_A(7 downto 0)=X"F5" and T80_IORQ_n='0' else '1';
CSF6_x <= '0' when T80_A(7 downto 0)=X"F6" and T80_IORQ_n='0' else '1';
CSF7_x <= '0' when T80_A(7 downto 0)=X"F7" and T80_IORQ_n='0' else '1';
CCOL <= CCOLi when T80_BUSACK_n='1' else "111";
BCOL <= BCOLi when T80_BUSACK_n='1' else "000";
INVi <= INV when BOOTM='0' and T80_BUSACK_n='1' else '1';
VGATEi <= VGATE when BOOTM='0' and T80_BUSACK_n='1' else '0';
GPAGE <= GPAGEi when BOOTM='0' and T80_BUSACK_n='1' else "000";
GDISPEN <= '0' when BOOTM='1' or T80_BUSACK_n='0' else
'1' when MODE_MZ80B='1' else GDISPENi;
CH80i <= CH80 when BOOTM='0' and T80_BUSACK_n='1' else '0';
--
-- Bus Select
--
VADR <= T80_A(10 downto 0) when CSV_n='0' and BLNK='1' else VADRC;
GADRi <= T80_A(13 downto 0) when CSG_n='0' and BLNK='1' and MODE_MZ2000='1' else
'0'&T80_A(12 downto 0) when CSG_n='0' and BLNK='1' and MODE_MZ80B='1' else GADRC;
GADR <= "1111101"&GADRi; -- 0x7D0000
DCODE <= T80_DI when CSV_n='0' and BLNK='1' and T80_WR_n='0' else VRAMDO;
T80_DO <= VRAMDO when T80_RD_n='0' and CSV_n='0' else
GDI(7 downto 0) when T80_RD_n='0' and CSG_n='0' and GBANK="01" else
GDI(15 downto 8) when T80_RD_n='0' and CSG_n='0' and GBANK="10" else
GDI(23 downto 16) when T80_RD_n='0' and CSG_n='0' and GBANK="11" else (others=>'0');
CGADR <= DCODE&VCOUNT(2 downto 0);
GRAMBDI <= GDI(7 downto 0) when GPAGE(0)='1' else (others=>'0');
GRAMRDI <= GDI(15 downto 8) when GPAGE(1)='1' else (others=>'0');
GRAMGDI <= GDI(23 downto 16) when GPAGE(2)='1' else (others=>'0');
GDO <= "00000000"&T80_DI&T80_DI&T80_DI;
--
-- Color Decode
--
-- Monoclome Monitor
-- MB<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
-- MR<=SDAT(7) when HDISPEN='1' and VGATEi='0' else '0';
MB <= '0';
MR <= '0';
MG <= not (SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0)))) when HDISPEN='1' and VGATEi='0' and INVi='0' else
SDAT(7) or (GDISPEN and (SDATB(0) or SDATR(0) or SDATG(0))) when HDISPEN='1' and VGATEi='0' and INVi='1' else '0';
-- Color Monitor(MZ-2000)
process( HDISPEN, VGATEi, GPRI, SDAT(7), SDATB(0), SDATR(0), SDATG(0), CCOL, BCOL ) begin
if HDISPEN='1' and VGATEi='0' then
if SDAT(7)='0' and SDATB(0)='0' then
BB<=BCOL(0);
else
if GPRI='0' then
if SDAT(7)='1' then
BB<=CCOL(0);
else
BB<='1'; -- SDATB(0)='1'
end if;
else --GPRI='1'
if SDATB(0)='1' then
BB<='1';
else
BB<=CCOL(0); -- SDAT(7)='1'
end if;
end if;
end if;
if SDAT(7)='0' and SDATR(0)='0' then
BR<=BCOL(1);
else
if GPRI='0' then
if SDAT(7)='1' then
BR<=CCOL(1);
else
BR<='1'; -- SDATR(0)='1'
end if;
else --GPRI='1' then
if SDATR(0)='1' then
BR<='1';
else
BR<=CCOL(1); -- SDAT(7)='1'
end if;
end if;
end if;
if SDAT(7)='0' and SDATG(0)='0' then
BG<=BCOL(2);
else
if GPRI='0' then
if SDAT(7)='1' then
BG<=CCOL(2);
else
BG<='1'; -- SDATG(0)='1'
end if;
else --GPRI='1' then
if SDATG(0)='1' then
BG<='1';
else
BG<=CCOL(2); -- SDAT(7)='1'
end if;
end if;
end if;
else
BB<='0';
BR<='0';
BG<='0';
end if;
end process;
-- Color Monitor(PIO-3039)
POUT<=(SDAT(7) and CDISPEN)&SDATR(0)&SDATB(0);
process(POUT, PALET0, PALET1, PALET2, PALET3, PALET4, PALET5, PALET6, PALET7) begin
case POUT is
when "000" => PBGR<=PALET0;
when "001" => PBGR<=PALET1;
when "010" => PBGR<=PALET2;
when "011" => PBGR<=PALET3;
when "100" => PBGR<=PALET4;
when "101" => PBGR<=PALET5;
when "110" => PBGR<=PALET6;
when "111" => PBGR<=PALET7;
when others => PBGR<=PALET7;
end case;
end process;
--
-- Output
--
CK16M <= CK16M;
VBLANK <= VDISPEN;
HBLANK <= HBLANKi;
ROUT <= MR when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
BR when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(0);
GOUT <= MG when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
BG when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(1);
BOUT <= MB when MODE_NORMAL='1' or BOOTM='1' or T80_BUSACK_n='0' else
BB when MODE_COLOUR='1' and MODE_MZ2000='1' else PBGR(2);
end RTL;

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---------------------------------------------------------------------------------------------------------
--
-- Name: mz80b.vhd
-- Created: August 2018
-- Author(s): Philip Smart
-- Description: Sharp MZ series Business Computer:
-- Models MZ-80B, MZ-2000
--
-- This module is the main (top level) container for the Business MZ Computer
-- Emulation.
--
-- The design tries to work from top-down, where components which are common
-- to the Business and Personal MZ series are at the top (ie. main memory,
-- ROM, CPU), drilling down two trees, MZ-80B (Business), MZ-80C (Personal)
-- to the machine specific modules and components. Some components are common
-- by their nature (ie. 8255 PIO) but these are instantiated within the lower
-- tree branch as their design use is less generic.
--
-- The tree is as follows;-
--
-- (emu) sharpmz.vhd (mz80c) -> mz80c.vhd
-- | -> mz80c_video.vhd
-- | -> pcg.vhd
-- | -> cmt.vhd (this may move to common and be shared with mz80b)
-- | -> keymatrix.vhd (common)
-- | -> pll.v (common)
-- | -> clkgen.vhd (common)
-- | -> T80 (common)
-- | -> i8255 (common)
-- | -> i8253 (common)
-- | -> dpram.vhd (common)
-- | -> dprom.vhd (common)
-- | -> mctrl.vhd (common)
-- sys_top.sv (emu) -> (emu) sharpmz.vhd (hps_io) -> hps_io.sv
-- |
-- (emu) sharpmz.vhd (mz80b) -> mz80b.vhd (under development)
--
--
--
-- Credits:
-- Copyright: (c) 2018 Philip Smart <philip.smart@net2net.org>
--
-- History: August 2018 - Initial module created.
--
---------------------------------------------------------------------------------------------------------
-- This source file is free software: you can redistribute it and-or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
---------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mz80b is
PORT (
-- Clocks
CK50M : in std_logic; -- Master Clock(50MHz)
CK25M : in std_logic; -- VGA Clock MZ80B (25MHz)
CK16M : in std_logic; -- MZ80B CPU Clock (16MHz)
CK12M5 : in std_logic; -- VGA Clock MZ80C (12.5MHz)
CK8M : in std_logic; -- 15.6kHz Dot Clock(8MHz)
CK4M : in std_logic; -- CPU Turbo Clock MZ80C (4MHz)
CK3M125 : in std_logic; -- Music Base Clock(31.25kHz)
CK2M : in std_logic; -- Z80 Original Clock MZ80C
CLKVIDEO : out std_logic; -- Base clock for video.
-- Resets.
COLD_RESET : in std_logic;
WARM_RESET : in std_logic;
-- Z80 CPU
T80_RST_n : in std_logic;
T80_CLK_n : in std_logic;
T80_CLKEN : out std_logic;
T80_WAIT_n : out std_logic;
T80_INT_n : out std_logic;
T80_NMI_n : out std_logic;
T80_BUSRQ_n : out std_logic;
T80_M1_n : in std_logic;
T80_MREQ_n : in std_logic;
T80_IORQ_n : in std_logic;
T80_RD_n : in std_logic;
T80_WR_n : in std_logic;
T80_RFSH_n : in std_logic;
T80_HALT_n : in std_logic;
T80_BUSAK_n : in std_logic;
T80_A16 : in std_logic_vector(15 downto 0);
T80_DI : out std_logic_vector(7 downto 0);
T80_DO : in std_logic_vector(7 downto 0);
-- Chip selects to common resources.
CSROM_n : out std_logic;
CSRAM_n : out std_logic;
-- Audio.
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
-- Video signals.
R : out std_logic;
G : out std_logic;
B : out std_logic;
HSYNC_n : out std_logic;
VSYNC_n : out std_logic;
HBLANK : out std_logic;
VBLANK : out std_logic;
-- Type of machine we are emulating.
MODE_MZ80K : in std_logic;
MODE_MZ80C : in std_logic;
MODE_MZ1200 : in std_logic;
MODE_MZ80A : in std_logic;
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
MODE_MZ700 : in std_logic;
MODE_MZ800 : in std_logic;
MODE_MZ_KC : in std_logic;
MODE_MZ_A : in std_logic;
MODE_MZ_B : in std_logic;
MODE_MZ_80C : in std_logic;
MODE_MZ_80B : in std_logic;
-- Type of display to emulate.
DISPLAY_NORMAL : in std_logic;
DISPLAY_NIDECOM : in std_logic;
DISPLAY_GAL5 : in std_logic;
DISPLAY_COLOUR : in std_logic;
-- Buttons to emulate.
BUTTON_PLAYSW : in std_logic; -- Tape Play Switch, 1 = Play.
-- Different operations modes
CONFIG_TURBO : in std_logic; -- CPU Speed, 0 = Normal, 1 = Turbo
-- I/O -- I/O down to the core.
PS2_KEY : in std_logic_vector(10 downto 0);
PS2_MOUSE : in std_logic_vector(24 downto 0);
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic; -- HPS Interrupt.
-- Debug Status Leds
DEBUG_STATUS_LEDS : out std_logic_vector(23 downto 0) -- 24 leds to display status.
);
end mz80b;
-- Switch
SW : in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
-- PS2
PS2_KBDAT : in std_logic; -- PS2 Keyboard Data
PS2_KBCLK : in std_logic; -- PS2 Keyboard Clock
);
end mz80b_core;
architecture rtl of mz80b_core is
DEBUG_STATUS_LEDS : out std_logic_vector(23 downto 0) -- 24 leds to display status.
--
-- T80
--
signal MREQ_n : std_logic;
signal IORQ_n : std_logic;
signal RD_n : std_logic;
--signal MWR : std_logic;
--signal MRD : std_logic;
signal IWR : std_logic;
signal ZWAIT_n : std_logic;
signal M1 : std_logic;
signal RFSH_n : std_logic;
signal ZDTO : std_logic_vector(7 downto 0);
signal ZDTI : std_logic_vector(7 downto 0);
--signal RAMCS_n : std_logic;
signal RAMDI : std_logic_vector(7 downto 0);
signal BAK_n : std_logic;
signal BREQ_n : std_logic;
--
-- Clocks
--
signal CK4M : std_logic;
signal CK16M : std_logic;
signal CK25M : std_logic;
signal CK3125 : std_logic;
--signal SCLK : std_logic;
--signal HCLK : std_logic;
signal CASCADE01 : std_logic;
signal CASCADE12 : std_logic;
--
-- Decodes, misc
--
--signal CSE_n : std_logic;
--signal CSE2_n : std_logic;
--signal BUF : std_logic_vector(9 downto 0);
signal CSHSK : std_logic;
signal MZMODE : std_logic;
signal DMODE : std_logic;
signal KBEN : std_logic;
signal KBDT : std_logic_vector(7 downto 0);
signal BOOTM : std_logic;
signal F_BTN : std_logic;
signal IRQ_CMT : std_logic;
signal C_LEDG : std_logic_vector(9 downto 0);
signal IRQ_FDD : std_logic;
signal F_LEDG : std_logic_vector(9 downto 0);
--
-- Video
--
signal HBLANKi : std_logic;
signal VBLANKi : std_logic;
signal HSYNC_ni : std_logic;
signal VSYNC_ni : std_logic;
signal Ri : std_logic;
signal Gi : std_logic;
signal Bi : std_logic;
--signal VGATE : std_logic;
signal CSV_n : std_logic;
signal CSG_n : std_logic;
signal VRAMDO : std_logic_vector(7 downto 0);
--
-- PPI
--
signal CSE0_n : std_logic;
signal PPI_DO : std_logic_vector(7 downto 0);
signal PPIPA : std_logic_vector(7 downto 0);
signal PPIPB : std_logic_vector(7 downto 0);
signal PPIPC : std_logic_vector(7 downto 0);
signal BST_n : std_logic;
--
-- PIT
--
signal CSE4_n : std_logic;
signal DOPIT : std_logic_vector(7 downto 0);
signal RST8253_n : std_logic;
--
-- PIO
--
signal CSE8_n : std_logic;
signal PIO_DO : std_logic_vector(7 downto 0);
signal INT_n : std_logic;
signal PIOPA : std_logic_vector(7 downto 0);
signal PIOPB : std_logic_vector(7 downto 0);
--
-- FDD,FDC
--
signal DOFDC : std_logic_vector(7 downto 0);
signal DS : std_logic_vector(3 downto 0);
signal HS : std_logic;
signal MOTOR_n : std_logic;
signal INDEX_n : std_logic;
signal TRACK00_n : std_logic;
signal WPRT_n : std_logic;
signal STEP_n : std_logic;
signal DIREC : std_logic;
signal FDO : std_logic_vector(7 downto 0);
signal FDI : std_logic_vector(7 downto 0);
signal WGATE_n : std_logic;
signal DTCLK : std_logic;
--
-- for Debug
--
--
-- Components
--
component i8255
Port (
RST : in std_logic;
CLK : in std_logic;
A : in std_logic_vector(1 downto 0);
CS : in std_logic;
RD : in std_logic;
WR : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
-- Port
PA : out std_logic_vector(7 downto 0);
PB : in std_logic_vector(7 downto 0);
PC : out std_logic_vector(7 downto 0);
-- Mode
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic
);
end component;
component i8253
Port (
RST : in std_logic;
CLK_n : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_n : in std_logic;
WR_n : in std_logic;
RD_n : in std_logic;
CLK0 : in std_logic;
GATE0 : in std_logic;
OUT0 : out std_logic;
CLK1 : in std_logic;
GATE1 : in std_logic;
OUT1 : out std_logic;
CLK2 : in std_logic;
GATE2 : in std_logic;
OUT2 : out std_logic
);
end component;
component z8420
Port (
-- System
RST_n : in std_logic; -- Only Power On Reset
-- Z80 Bus Signals
CLK : in std_logic;
BASEL : in std_logic;
CDSEL : in std_logic;
CE : in std_logic;
RD_n : in std_logic;
WR_n : in std_logic;
IORQ_n : in std_logic;
M1_n : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
IEI : in std_logic;
IEO : out std_logic;
INT_n : out std_logic;
-- Port
A : out std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
);
end component;
component keymatrix
Port (
RST_n : in std_logic;
CLK : in std_logic; -- System Clock
-- Operating mode of emulator
MZ_MODE_B : in std_logic;
-- i8255
PA : in std_logic_vector(3 downto 0);
PB : out std_logic_vector(7 downto 0);
STALL : in std_logic;
-- PS/2 Keyboard Data
PS2_KEY : in std_logic_vector(10 downto 0); -- PS2 Key data.
PS2_MOUSE : in std_logic_vector(24 downto 0); -- PS2 Mouse data.
-- Type of machine we are emulating.
MODE_MZ80K : in std_logic;
MODE_MZ80C : in std_logic;
MODE_MZ1200 : in std_logic;
MODE_MZ80A : in std_logic;
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
MODE_MZ700 : in std_logic;
MODE_MZ_KC : in std_logic;
MODE_MZ_A : in std_logic;
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable to FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
component mz80b_videoout
Port (
RST_n : in std_logic; -- Reset
BOOTM : in std_logic; -- BOOT Mode
-- Type of machine we are emulating.
MODE_MZ80B : in std_logic;
MODE_MZ2000 : in std_logic;
-- Type of display to emulate.
DISPLAY_NORMAL : in std_logic;
DISPLAY_NIDECOM : in std_logic;
DISPLAY_GAL5 : in std_logic;
DISPLAY_COLOUR : in std_logic;
-- Different operations modes.
CONFIG_PCGRAM : in std_logic; -- PCG Mode Switch, 0 = CGROM, 1 = CGRAM.
-- Clocks
CK16M : in std_logic; -- 15.6kHz Dot Clock(16MHz)
T80_CLK_n : in std_logic; -- Z80 Current Clock
T80_CLK : in std_logic; -- Z80 Current Clock Inverted
-- CPU Signals
T80_A : in std_logic_vector(13 downto 0); -- CPU Address Bus
CSV_n : in std_logic; -- CPU Memory Request(VRAM)
CSG_n : in std_logic; -- CPU Memory Request(GRAM)
T80_RD_n : in std_logic; -- CPU Read Signal
T80_WR_n : in std_logic; -- CPU Write Signal
T80_MREQ_n : in std_logic; -- CPU Memory Request
T80_BUSACK_n : in std_logic; -- CPU Bus Acknowledge
T80_WAIT_n : out std_logic; -- CPU Wait Request
T80_DI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
T80_DO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
-- Video Control from outside
INV : in std_logic; -- Reverse mode(8255 PA4)
VGATE : in std_logic; -- Video Output Control(8255 PC0)
CH80 : in std_logic; -- Text Character Width(Z80PIO A5)
-- Video Signals
VGATE_n : in std_logic; -- Video Output Control
HBLANK : out std_logic; -- Horizontal Blanking
VBLANK : out std_logic; -- Vertical Blanking
HSYNC_n : out std_logic; -- Horizontal Sync
VSYNC_n : out std_logic; -- Vertical Sync
ROUT : out std_logic; -- Red Output
GOUT : out std_logic; -- Green Output
BOUT : out std_logic; -- Green Output
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0) -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
component cmt
Port (
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Interrupt
INTO : out std_logic; -- Tape action interrupt
-- Z80 Bus
ZCLK : in std_logic;
-- ZA8 : in std_logic_vector(7 downto 0);
-- ZIWR_n : in std_logic;
-- ZDI : in std_logic_vector(7 downto 0);
-- ZDO : out std_logic_vector(7 downto 0);
-- Tape signals
T_END : out std_logic; -- Sense CMT(Motor on/off)
OPEN_n : in std_logic; -- Open
PLAY_n : in std_logic; -- Play
STOP_n : in std_logic; -- Stop
FF_n : in std_logic; -- Fast Foward
REW_n : in std_logic; -- Rewind
APSS_n : in std_logic; -- APSS
FFREW : in std_logic; -- FF/REW mode
FMOTOR : in std_logic; -- FF/REW start
FLATCH : in std_logic; -- FF/REW latch
WREADY : out std_logic; -- Write enable
TREADY : out std_logic; -- Tape exist
-- EXIN : in std_logic; -- CMT IN from I/O board
RDATA : out std_logic; -- to 8255
-- Status Signal
SCLK : in std_logic; -- Slow Clock(31.25kHz)
MZMODE : in std_logic; -- Hardware Mode
DMODE : in std_logic -- Display Mode
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end component;
component mz1e05
Port (
-- CPU Signals
ZRST_n : in std_logic;
ZCLK : in std_logic;
ZADR : in std_logic_vector(7 downto 0); -- CPU Address Bus(lower)
ZRD_n : in std_logic; -- CPU Read Signal
ZWR_n : in std_logic; -- CPU Write Signal
ZIORQ_n : in std_logic; -- CPU I/O Request
ZDI : in std_logic_vector(7 downto 0); -- CPU Data Bus(in)
ZDO : out std_logic_vector(7 downto 0); -- CPU Data Bus(out)
SCLK : in std_logic; -- Slow Clock
-- FD signals
DS_n : out std_logic_vector(4 downto 1); -- Drive Select
HS : out std_logic; -- Head Select
MOTOR_n : out std_logic; -- Motor On
INDEX_n : in std_logic; -- Index Hole Detect
TRACK00 : in std_logic; -- Track 0
WPRT_n : in std_logic; -- Write Protect
STEP_n : out std_logic; -- Head Step In/Out
DIREC : out std_logic; -- Head Step Direction
WGATE_n : out std_logic; -- Write Gate
DTCLK : in std_logic; -- Data Clock
FDI : in std_logic_vector(7 downto 0); -- Read Data
FDO : out std_logic_vector(7 downto 0) -- Write Data
);
end component;
-- PDS : needs buffer ram and an interface to HPS to write into buffer memory.
--component fdunit
-- Port (
-- RST_n : in std_logic; -- Reset
-- CLK : in std_logic; -- System Clock
-- -- Interrupt
-- INTO : out std_logic; -- Step Pulse interrupt
-- -- FD signals
-- FCLK : in std_logic;
-- DS_n : in std_logic_vector(4 downto 1); -- Drive Select
-- HS : in std_logic; -- Head Select
-- MOTOR_n : in std_logic; -- Motor On
-- INDEX_n : out std_logic; -- Index Hole Detect
-- TRACK00 : out std_logic; -- Track 0
-- WPRT_n : out std_logic; -- Write Protect
-- STEP_n : in std_logic; -- Head Step In/Out
-- DIREC : in std_logic; -- Head Step Direction
-- WG_n : in std_logic; -- Write Gate
-- DTCLK : out std_logic; -- Data Clock
-- FDI : in std_logic_vector(7 downto 0); -- Write Data
-- FDO : out std_logic_vector(7 downto 0); -- Read Data
-- -- Buffer RAM I/F
-- BCS_n : out std_logic; -- RAM Request
-- BADR : out std_logic_vector(22 downto 0); -- RAM Address
-- BWR_n : out std_logic; -- RAM Write Signal
-- BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
-- BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
-- -- HPS Interface
-- IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
-- IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
-- IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
-- IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
-- IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
-- IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
-- IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
-- IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
-- );
--end component;
begin
--
-- Instantiation
--
CPU0 : T80se
generic map(
Mode => 0, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write => 1, -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait => 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
)
port map (
RESET_n => T80_RST_n,
CLK_n => CK4M,
CLKEN => '1',
WAIT_n => ZWAIT_n,
INT_n => INT_n,
-- INT_n => '1',
NMI_n => '1',
BUSRQ_n => BREQ_n,
M1_n => M1,
MREQ_n => MREQ_n,
IORQ_n => IORQ_n,
RD_n => RD_n,
WR_n => T80_WR_n,
RFSH_n => RFSH_n,
HALT_n => open,
BUSAK_n => BAK_n,
A => T80_A16,
DI => ZDTI,
DO => ZDTO
);
PPI0 : i8255 port map (
RST => T80_RST,
CLK => CK4M,
A => T80_A16(1 downto 0),
CS => CSE0_n,
RD => RD_n,
WR => T80_WR_n,
DI => ZDTO,
DO => PPI_DO,
-- Port
PA => PPIPA,
PB => PPIPB,
PC => PPIPC,
-- Mode
MODE_MZ80B => MODE_MZ80B,
MODE_MZ2000 => MODE_MZ2000
);
PPIPB(7)<=PIOPB(7);
-- WDATA<=PPIPC(7);
-- REC_n<=PPIPC(6);
-- WRIT_n<=PPIPC(6);
-- KINH<=PPIPC(5);
-- L_FR<=PPIPC(5);
BST_n<=PPIPC(3);
-- NST<=PPIPC(1);
CMT0 : cmt port map (
-- Interrupt
INTO => IRQ_CMT, -- Tape action interrupt
-- Z80 Bus
ZCLK => CK4M,
-- Tape signals
T_END => PPIPB(3), -- Sense CMT(Motor on/off)
OPEN_n => PPIPC(4), -- Open
PLAY_n => PPIPA(2), -- Play
STOP_n => PPIPA(3), -- Stop
FF_n => PPIPA(1), -- Fast Foward
REW_n => PPIPA(0), -- Rewind
APSS_n => PPIPA(7), -- APSS
FFREW => PPIPA(1), -- FF/REW mode
FMOTOR => PPIPA(0), -- FF/REW start
FLATCH => PPIPC(5), -- FF/REW latch
WREADY => PPIPB(4), -- Write enable
TREADY => PPIPB(5), -- Tape exist
RDATA => PPIPB(6), -- to 8255
-- Status Signal
SCLK => CK3125, -- Slow Clock(31.25kHz)
MZMODE => MZMODE,
DMODE => DMODE
);
PIT0 : i8253 port map (
RST => T80_RST,
CLK => CK4M,
A => T80_A16(1 downto 0),
DI => ZDTO,
DO => DOPIT,
CS => CSE4_n,
WR => T80_WR_n,
RD => RD_n,
CLK0 => CK3125,
GATE0 => RST8253_n,
OUT0 => CASCADE01,
CLK1 => CASCADE01,
GATE1 => RST8253_n,
OUT1 => CASCADE12,
CLK2 => CASCADE12,
GATE2 => '1',
OUT2 => open
);
PIO0 : z8420 port map (
-- System
RST_n => T80_RST_n, -- Only Power On Reset
-- Z80 Bus Signals
CLK => CK4M,
BASEL => T80_A16(1),
CDSEL => T80_A16(0),
CE => CSE8_n,
RD_n => RD_n,
WR_n => T80_WR_n,
IORQ_n => IORQ_n,
M1_n => M1,
DI => ZDTO,
DO => PIO_DO,
IEI => '1',
IEO => open,
-- INT_n => open,
INT_n => INT_n,
-- Port
A => PIOPA,
B => PIOPB,
);
KEYS : keymatrix
port map (
RST_n => T80_RST_n,
CLK => T80_CLK, -- System clock.
-- Operating mode of emulator
MZ_MODE_B => MODE_MZ_B,
-- i8255
PA => i8255_PA_O(3 downto 0),
PB => i8255_PB_I,
STALL => i8255_PA_O(4),
-- PS/2 Keyboard Data
PS2_KEY => PS2_KEY, -- PS2 Key data.
PS2_MOUSE => PS2_MOUSE, -- PS2 Mouse data.
-- Type of machine we are emulating.
MODE_MZ80K => MODE_MZ80K,
MODE_MZ80C => MODE_MZ80C,
MODE_MZ1200 => MODE_MZ1200,
MODE_MZ80A => MODE_MZ80A,
MODE_MZ80B => MODE_MZ80B,
MODE_MZ2000 => MODE_MZ2000,
MODE_MZ700 => MODE_MZ700,
MODE_MZ_KC => MODE_MZ_KC,
MODE_MZ_A => MODE_MZ_A,
-- HPS Interface
IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
IOCTL_DIN => IOCTL_DIN_KEY, -- HPS Data to be sent to HPS.
IOCTL_INTERRUPT => IOCTL_INTERRUPT -- Interrupt to HPS.
);
VIDEO0 : mz80b_videoout Port map (
RST => T80_RST_n -- Reset
MZMODE => MZMODE, -- Hardware Mode
DMODE => DMODE, -- Display Mode
-- Clocks
CK50M => CK50M, -- Master Clock(50MHz)
CK25M => CK25M, -- VGA Clock(25MHz)
CK16M => CK16M, -- 15.6kHz Dot Clock(16MHz)
CK4M => CK4M, -- CPU/CLOCK Clock(4MHz)
CK3125 => CK3125, -- Time Base Clock(31.25kHz)
-- CPU Signals
A => T80_A16(13 downto 0), -- CPU Address Bus
CSV_n => CSV_n, -- CPU Memory Request(VRAM)
CSG_n => CSG_n, -- CPU Memory Request(GRAM)
RD_n => RD_n, -- CPU Read Signal
WR_n => T80_WR_n, -- CPU Write Signal
MREQ_n => MREQ_n, -- CPU Memory Request
IORQ_n => IORQ_n, -- CPU I/O Request
WAIT_n => ZWAIT_n, -- CPU Wait Request
DI => ZDTO, -- CPU Data Bus(in)
DO => VRAMDO, -- CPU Data Bus(out)
-- Video Control from outside
INV => PPIPA(4), -- Reverse mode(8255 PA4)
VGATE => PPIPC(0), -- Video Output Control
CH80 => PIOPA(5),
-- Video Signals
VGATE_n => VGATE_n, -- Video Output Control
HBLANK => HBLANKi, -- Horizontal Blanking
VBLANK => VBLANKi, -- Vertical Blanking
HSYNC_n => HSYNC_ni, -- Horizontal Sync
VSYNC_n => VSYNC_ni, -- Vertical Sync
ROUT => Ri, -- Red Output
GOUT => Gi, -- Green Output
BOUT => Bi, -- Blue Output
HBLANK => HBLANKi, -- Horizontal Blanking
VBLANK => VBLANKi, -- Vertical Blanking
-- Control Signal
BOOTM => BOOTM, -- BOOT Mode
BACK => BAK_n -- Z80 Bus Acknowlegde
);
PDS :- Need BOOTM
FDIF0 : mz1e05 Port map(
-- CPU Signals
ZRST_n => T80_RST_n,
ZCLK => CK4M,
ZADR => T80_A16(7 downto 0), -- CPU Address Bus(lower)
ZRD_n => RD_n, -- CPU Read Signal
ZWR_n => T80_WR_n, -- CPU Write Signal
ZIORQ_n => IORQ_n, -- CPU I/O Request
ZDI => ZDTO, -- CPU Data Bus(in)
ZDO => DOFDC, -- CPU Data Bus(out)
SCLK => CK3125, -- Slow Clock
-- FD signals
DS_n => DS, -- Drive Select
HS => HS, -- Head Select
MOTOR_n => MOTOR_n, -- Motor On
INDEX_n => INDEX_n, -- Index Hole Detect
TRACK00 => TRACK00_n, -- Track 0
WPRT_n => WPRT_n, -- Write Protect
STEP_n => STEP_n, -- Head Step In/Out
DIREC => DIREC, -- Head Step Direction
WGATE_n => WGATE_n, -- Write Gate
DTCLK => DTCLK, -- Data Clock
FDI => FDI, -- Read Data
FDO => FDO -- Write Data
);
-- FDU0 : fdunit Port map(
-- -- Interrupt
-- INTO => IRQ_FDD, -- Step Pulse interrupt
-- -- FD signals
-- FCLK => CK4M,
-- DS_n => DS, -- Drive Select
-- HS => HS, -- Head Select
-- MOTOR_n => MOTOR_n, -- Motor On
-- INDEX_n => INDEX_n, -- Index Hole Detect
-- TRACK00 => TRACK00_n, -- Track 0
-- WPRT_n => WPRT_n, -- Write Protect
-- STEP_n => STEP_n, -- Head Step In/Out
-- DIREC => DIREC, -- Head Step Direction
-- WG_n => WGATE_n, -- Write Gate
-- DTCLK => DTCLK, -- Data Clock
-- FDO => FDI, -- Read Data
-- FDI => FDO, -- Write Data
-- -- Buffer RAM I/F
-- BCS_n => BCS_n, -- RAM Request
-- BADR => BADR, -- RAM Address
-- BWR_n => BWR_n, -- RAM Write Signal
-- BDI => BDI, -- Data Bus Input from RAM
-- BDO => BDO -- Data Bus Output to RAM
-- );
--
-- Control Signals
--
IWR <= IORQ_n or T80_WR_n;
--
-- Data Bus
--
ZDTI <= PPI_DO or DOPIT or PIO_DO or VRAMDO or RAMDI or DOFDC;
RAMDI <= T80_DO when RD_n='0' and MREQ_n='0' and CSV_n='1' and CSG_n='1' else (others=>'0');
-- HSKDI when CSHSK='0' else T80_DO;
--
-- Chip Select
--
CSV_n <= '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 12)="1101" and MREQ_n='0' and PIOPA(6)='0' else -- $D000 - $DFFF (80B)
'0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 12)="0101" and MREQ_n='0' and PIOPA(6)='1' else -- $5000 - $5FFF (80B)
'0' when MZMODE='1' and PIOPA(7)='1' and T80_A16(15 downto 12)="1101" and MREQ_n='0' and PIOPA(6)='1' else '1'; -- $D000 - $DFFF (2000)
CSG_n <= '0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 13)="111" and MREQ_n='0' and PIOPA(6)='0' else -- $E000 - $FFFF (80B)
'0' when MZMODE='0' and PIOPA(7)='1' and T80_A16(15 downto 13)="011" and MREQ_n='0' and PIOPA(6)='1' else -- $6000 - $7FFF (80B)
'0' when MZMODE='1' and PIOPA(7)='1' and T80_A16(15 downto 14)="11" and MREQ_n='0' and PIOPA(6)='0' else '1'; -- $C000 - $FFFF (2000)
CSHSK <= '0' when T80_A16(7 downto 3)="10001" and IORQ_n='0' else '1'; -- HandShake Port
CSE0_n <= '0' when T80_A16(7 downto 2)="111000" and IORQ_n='0' else '1'; -- 8255
CSE4_n <= '0' when T80_A16(7 downto 2)="111001" and IORQ_n='0' else '1'; -- 8253
CSE8_n <= '0' when T80_A16(7 downto 2)="111010" and IORQ_n='0' else '1'; -- PIO
--
-- Video Output.
--
HSYNC_n <= HSYNC_ni;
VSYNC_n <= VSYNC_ni;
R <= Ri;
G <= Gi;
B <= Bi;
VBLANK <= VBLANKi;
HBLANK <= HBLANKi;
VBLANKi <= PPIPB(0); -- Vertical Blanking
--
-- Ports
--
CSRAM_n <= MREQ_n when CSV_n='1' and CSG_n='1' and RFSH_n='1' else '1';
T80_DI <= ZDTO;
ZWR_n <= T80_WR_n;
--
-- Misc
--
MZMODE <= SW(9);
DMODE <= SW(8);
T80_RST <= not T80_RST_n;
RST8253_n <= '0' when T80_A16(7 downto 2)="111100" and IWR='0' else '1';
GPIO1_D(15)<=PPIPC(2); -- Sound Output
GPIO1_D(14)<=PPIPC(2);
end rtl;

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--
-- sysctrl.vhd
--
-- SHARP MZ-80B/2000 series compatible logic, system control module
-- for Altera DE0
--
-- Nibbles Lab. 2014
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sysctrl is
port(
RST_n : in std_logic; -- Reset
CLK : in std_logic; -- System Clock
-- Push Button
BUTTON : in std_logic_vector(2 downto 0); -- Pushbutton[2:0]
-- Switch
SW : in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
-- PS/2 Keyboard Data
KBEN : in std_logic; -- PS/2 Keyboard Data Valid
KBDT : in std_logic_vector(7 downto 0); -- PS/2 Keyboard Data
-- Interrupt
INTL : out std_logic; -- Interrupt Signal Output
I_CMT : in std_logic; -- from CMT
I_FDD : in std_logic; -- from FD unit
-- Others
URST_n : out std_logic; -- Universal Reset
ARST_n : out std_logic; -- All Reset
ZRST : out std_logic; -- Z80 Reset
CLK50 : in std_logic; -- 50MkHz
SCLK : in std_logic; -- 31.25kHz
ZBREQ : out std_logic; -- Z80 Bus Request
ZBACK : in std_logic; -- Z80 Bus Acknowridge
BST_n : in std_logic; -- BOOT start request from Z80
BOOTM : out std_logic; -- BOOT mode
F_BTN : out std_logic -- Function Button
-- HPS Interface
IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
IOCTL_DOUT : in std_logic_vector(15 downto 0) -- HPS Data to be written into FPGA.
IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
);
end sysctrl;
architecture rtl of sysctrl is
--
-- Reset & Filters
--
signal URSTi : std_logic; -- Universal Reset
signal BUF : std_logic_vector(7 downto 0) := "00000000";
signal CNT5 : std_logic_vector(4 downto 0);
signal SR_BTN : std_logic_vector(7 downto 0);
signal ZR_BTN : std_logic_vector(7 downto 0);
signal F_BTNi : std_logic;
--
-- Interrupt
--
signal IRQ_KB : std_logic;
signal IE_KB : std_logic;
signal IKBBUF : std_logic_vector(2 downto 0);
signal IRQ_FB : std_logic;
signal IE_FB : std_logic;
signal IFBBUF : std_logic_vector(2 downto 0);
signal IRQ_CT : std_logic;
signal IE_CT : std_logic;
signal ICTBUF : std_logic_vector(2 downto 0);
signal IRQ_FD : std_logic;
signal IE_FD : std_logic;
signal IFDBUF : std_logic_vector(2 downto 0);
--
-- Control for Z80
--
signal ZRSTi : std_logic;
signal BOOTMi : std_logic := '1';
begin
--
-- Avalon Bus
--
process( RST_n, CLK ) begin
if RST_n='0' then
IRQ_KB <= '0';
IRQ_FB <= '0';
IRQ_CT <= '0';
IRQ_FD <= '0';
IKBBUF <= (others=>'0');
IFBBUF <= (others=>'0');
ICTBUF <= (others=>'0');
IFDBUF <= (others=>'0');
IE_KB <= '0';
IE_FB <= '0';
IE_CT <= '0';
IE_FD <= '0';
ZBREQ <= '1';
BOOTMi <= '1';
ZRSTi <= '0';
elsif CLK'event and CLK='1' then
-- Edge Sense
IKBBUF<=IKBBUF(1 downto 0)&(KBEN and ((not ZBACK) or BOOTMi));
if IKBBUF(2 downto 1)="01" then
IRQ_KB <= IE_KB;
end if;
IFBBUF <= IFBBUF(1 downto 0)&F_BTNi;
if IFBBUF(2 downto 1)="01" then
IRQ_FB <= IE_FB;
end if;
ICTBUF <= ICTBUF(1 downto 0)&I_CMT;
if ICTBUF(2 downto 1)="01" then
IRQ_CT <= IE_CT;
end if;
IFDBUF <= IFDBUF(1 downto 0)&I_FDD;
if IFDBUF(2 downto 1)="01" then
IRQ_FD <= IE_FD;
end if;
-- Register
if IOCTL_RD='1' and IOCTL_WR='1' then
if IOCTL_ADDR=X"0005" then -- MZ_SYS_IREQ
IRQ_KB <= IRQ_KB and (not IOCTL_DOUT(0)); -- I_KBD 0x01
IRQ_FB <= IRQ_FB and (not IOCTL_DOUT(1)); -- I_FBTN 0x02
IRQ_CT <= IRQ_CT and (not IOCTL_DOUT(2)); -- I_CMT 0x04
IRQ_FD <= IRQ_FD and (not IOCTL_DOUT(3)); -- I_FDD 0x08
end if;
if IOCTL_ADDR=X"0006" then -- MZ_SYS_IENB
IE_KB <= IOCTL_DOUT(0); -- I_KBD 0x01
IE_FB <= IOCTL_DOUT(1); -- I_FBTN 0x02
IE_CT <= IOCTL_DOUT(2); -- I_CMT 0x04
IE_FD <= IOCTL_DOUT(3); -- I_FDD 0x08
end if;
if IOCTL_ADDR=X"0007" then -- MZ_SYS_CTRL (Control for Z80)
ZBREQ <= IOCTL_DOUT(0);
ZRSTi <= IOCTL_DOUT(1);
BOOTMi <= IOCTL_DOUT(2);
end if;
end if;
end if;
end process;
IOCTL_DIN <= "00000"&BUTTON when IOCTL_RD='1' and IOCTL_ADDR=X"0000" else -- MZ_SYS_BUTTON
SW(7 downto 0) when IOCTL_RD='1' and IOCTL_ADDR=X"0002" else -- MZ_SYS_SW70
"000000"&SW(9)&SW(8) when IOCTL_RD='1' and IOCTL_ADDR=X"0003" else -- MZ_SYS_SW98
KBDT when IOCTL_RD='1' and IOCTL_ADDR=X"0004" else -- MZ_SYS_KBDT
"0000"&IRQ_FD&IRQ_CT&IRQ_FB&IRQ_KB when IOCTL_RD='1' and IOCTL_ADDR=X"0005" else -- MZ_SYS_IREQ
"0000"&IE_FD&IE_CT&IE_FB&IE_KB when IOCTL_RD='1' and IOCTL_ADDR=X"0006" else -- MZ_SYS_IENB
"000000"&(not BST_n)&ZBACK when IOCTL_RD='1' and IOCTL_ADDR=X"0007" else -- MZ_SYS_STATUS
"00000000";
INTL <= IRQ_KB or IRQ_FB or IRQ_CT or IRQ_FD;
--
-- Filter and Asynchronous Reset with automatic
--
URST_n <= URSTi;
process( CLK50 ) begin
if( CLK50'event and CLK50='1' ) then
if BUF=X"80" then
URSTi <= '1';
else
BUF <= BUF+'1';
URSTi <= '0';
end if;
end if;
end process;
process( URSTi, SCLK ) begin
if URSTi='0' then
CNT5 <= (others=>'0');
SR_BTN <= (others=>'1');
ZR_BTN <= (others=>'1');
elsif SCLK'event and SCLK='1' then
if CNT5="11111" then
SR_BTN <= SR_BTN(6 downto 0)&(BUTTON(1) or (not BUTTON(0))); -- only BUTTON1
ZR_BTN <= ZR_BTN(6 downto 0)&((not BUTTON(1)) or BUTTON(0)); -- only BUTTON0
CNT5 <= (others=>'0');
else
CNT5<=CNT5+'1';
end if;
end if;
end process;
F_BTNi <= '1' when SR_BTN="00000000" else '0';
F_BTN <= F_BTNi;
ARST_n <= URSTi ;
ZRST <= '0' when (ZR_BTN="00000000" and ZBACK='1') or ZRSTi='0' or URSTi='0' else '1';
BOOTM <= BOOTMi;
end rtl;

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sharpmz-lite-div_assignment_defaults.qdf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 17:23:05 October 20, 2018
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL Enable
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

459
sharpmz-lite-pll.sdc Normal file
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@@ -0,0 +1,459 @@
## Generated SDC file "sharpmz-lite-pll.out.sdc"
## Copyright (C) 2017 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel MegaCore Function License Agreement, or other
## applicable license agreement, including, without limitation,
## that your use is for the sole purpose of programming logic
## devices manufactured by Intel and sold by Intel or its
## authorized distributors. Please refer to the applicable
## agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition"
## DATE "Tue Oct 09 16:54:46 2018"
##
## DEVICE "5CSEBA6U23I7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}]
create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 5243 -divide_by 512 -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 16 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 64 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 256 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 32 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 128 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 8 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 1135 -divide_by 256 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 5 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 64 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 32 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 160 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 80 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 40 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 20 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 10 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.110
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.110
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}] 0.110
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}] 0.110
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.110
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.110
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {FPGA_CLK2_50}] 0.110
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {FPGA_CLK2_50}] 0.110
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.110
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.230
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.220
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[6].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.220
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.330
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[7].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[5].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.260
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN2|pll_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN1|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
set_false_path -to [get_ports {VGA_*}]
set_false_path -to [get_ports {AUDIO_SPDIF}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
# Decouple different clock groups (to simplify routing)
# -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
# -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
set_clock_groups -asynchronous \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]

807
sharpmz-lite-pll_assignment_defaults.qdf Normal file
View File

@@ -0,0 +1,807 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 17:23:11 October 20, 2018
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL Enable
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

397
sharpmz-lite.qsf
View File

@@ -23,37 +23,39 @@
#
# -------------------------------------------------------------------------- #
set_global_assignment -name VERILOG_MACRO "LITE=1"
set_global_assignment -name VERILOG_MACRO "LITE=1"
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
#set_global_assignment -name TOP_LEVEL_ENTITY emu
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SEED 1
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH POWER EFFORT"
set_global_assignment -name SEED 1
#set_global_assignment -name SDC_FILE sharpmz.sdc
set_global_assignment -name SDC_FILE "sharpmz-lite.sdc"
#============================================================
# ADC
@@ -100,62 +102,62 @@ set_global_assignment -name SEED 1
#============================================================
# SDIO
#============================================================
#set_location_assignment PIN_AF25 -to SDIO_DAT[0]
#set_location_assignment PIN_AF23 -to SDIO_DAT[1]
#set_location_assignment PIN_AD26 -to SDIO_DAT[2]
#set_location_assignment PIN_AF28 -to SDIO_DAT[3]
#set_location_assignment PIN_AF27 -to SDIO_CMD
#set_location_assignment PIN_AH26 -to SDIO_CLK
#set_location_assignment PIN_AH7 -to SDIO_CD
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
#
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
#
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
@@ -216,27 +218,27 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
@@ -315,30 +317,30 @@ set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
@@ -352,82 +354,183 @@ set_location_assignment PIN_AA23 -to LED[7]
#set_location_assignment PIN_W21 -to SW[2]
#set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VHDL_FILE jtag_uart_0.vhd
set_global_assignment -name SYSTEMVERILOG_FILE emu.sv
set_global_assignment -name VHDL_FILE sharpmz.vhd
#============================================================
# Original MZ80C T80 CPU
#============================================================
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_Reg.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_Pack.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_MCode.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80_ALU.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80.vhd
#set_global_assignment -name VHDL_FILE common/T80.orig/T80s.vhd
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VHDL_FILE jtag_uart_0.vhd
set_global_assignment -name SYSTEMVERILOG_FILE emu.sv
set_global_assignment -name VHDL_FILE common/config_pkg.vhd
set_global_assignment -name VHDL_FILE bridge.vhd
set_global_assignment -name VHDL_FILE sharpmz.vhd
#============================================================
# Latest T80 CPU
#============================================================
set_global_assignment -name VHDL_FILE common/T80/T80.vhd
set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE common/T80/T80a.vhd
set_global_assignment -name VHDL_FILE common/T80/T80se.vhd
set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd
set_global_assignment -name VHDL_FILE common/T80/T80.vhd
set_global_assignment -name VHDL_FILE common/T80/T8080se.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE common/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE common/T80/T80a.vhd
set_global_assignment -name VHDL_FILE common/T80/T80se.vhd
set_global_assignment -name VHDL_FILE common/T80/T80sed.vhd
#============================================================
# i8253 Programmable Interval Timer
#============================================================
set_global_assignment -name VHDL_FILE common/i8253/i8253.vhd
set_global_assignment -name VHDL_FILE common/i8253/counter0.vhd
set_global_assignment -name VHDL_FILE common/i8253/counter1.vhd
set_global_assignment -name VHDL_FILE common/i8253/counter2.vhd
set_global_assignment -name VHDL_FILE common/i8254/i8254_counter.vhd
set_global_assignment -name VHDL_FILE common/i8254/i8254.vhd
#============================================================
# i8255 Programmable Peripheral Interface
#============================================================
set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd
set_global_assignment -name VHDL_FILE common/i8255/i8255.vhd
#set_global_assignment -name VHDL_FILE mz80b/i8255/i8255.vhd
#============================================================
# MZ80C specific modules.
#============================================================
set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd
set_global_assignment -name VHDL_FILE mz80c/cmt.vhd
set_global_assignment -name VHDL_FILE mz80c/mz80c_video.vhd
set_global_assignment -name VHDL_FILE mz80c/mz80c.vhd
#============================================================
# MZ80B specific modules.
#============================================================
set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd
#set_global_assignment -name VHDL_FILE mz80b/mz80b_dummy.vhd
set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd
#============================================================
# NEO430
#============================================================
#set_global_assignment -name VHDL_FILE neo430/neo430.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_addr_gen.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_alu.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_application_image.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_boot_rom.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_bootloader_image.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_cfu.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_control.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_cpu.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_crc.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_dmem.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_gpio.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_imem.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_muldiv.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_package.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_pwm.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_reg_file.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_sysconfig.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_timer.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_top.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_uart.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_spi.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_twi.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_wb_interface.vhd
#set_global_assignment -name VHDL_FILE neo430/neo430_wdt.vhd
#============================================================
# STORM
#============================================================
#set_global_assignment -name VHDL_FILE storm/STORM_SoC.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/ALU.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/BARREL_SHIFTER.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/BUS_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/CACHE.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/CORE.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/CORE_PKG.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/FLOW_CTRL.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/LOAD_STORE_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/MC_SYS.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/MS_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/MULTIPLY_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/OPCODE_DECODER.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/OPERAND_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/REG_FILE.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/STORM_TOP.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/WB_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/components/boot_rom/rtl/BOOT_ROM_FILE.vhd
#set_global_assignment -name VHDL_FILE storm/components/seven_segment_controller/rtl/SEVEN_SEG_CTRL.vhd
#set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2_wb.vhd
#set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2.vhd
#set_global_assignment -name VHDL_FILE storm/components/reset_protector/rtl/RST_PROTECT.vhd
#set_global_assignment -name VHDL_FILE storm/components/timer/rtl/TIMER.vhd
#set_global_assignment -name VHDL_FILE storm/components/io_controller/rtl/GP_IO_CTRL.vhd
#set_global_assignment -name VHDL_FILE storm/components/vector_interrupt_controller/rtl/VIC.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/MINI_UART.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Txunit.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Rxunit.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/utils.vhd
#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_top.vhd
#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_byte_ctrl.vhd
#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_bit_ctrl.vhd
#set_global_assignment -name VHDL_FILE storm/components/pwm_controller/rtl/PWM_CTRL.vhd
#set_global_assignment -name VHDL_FILE storm/components/sram_memory/rtl/MEMORY.vhd
#set_global_assignment -name VHDL_FILE storm/components/ioctl/rtl/ioctl.vhd
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_top.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_defines.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_clgen.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_shift.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/timescale.v
#============================================================
# PLL
#============================================================
set_global_assignment -name QIP_FILE common/pll.qip
set_global_assignment -name VHDL_FILE common/clkgen.vhd
set_global_assignment -name QIP_FILE common/pll.qip
set_global_assignment -name VHDL_FILE common/clkgen.vhd
#set_global_assignment -name QIP_FILE common/pll_1.qip
#set_global_assignment -name QIP_FILE common/pll_2.qip
#set_global_assignment -name QIP_FILE common/pll_4.qip
#============================================================
# Common modules
#============================================================
set_global_assignment -name VHDL_FILE common/dprom.vhd
set_global_assignment -name VHDL_FILE common/clk_div.vhd
set_global_assignment -name VHDL_FILE common/mctrl.vhd
set_global_assignment -name VHDL_FILE common/dpram.vhd
set_global_assignment -name VHDL_FILE common/keymatrix.vhd
set_global_assignment -name VHDL_FILE common/dprom.vhd
set_global_assignment -name VHDL_FILE common/clk_div.vhd
set_global_assignment -name VHDL_FILE common/mctrl.vhd
set_global_assignment -name VHDL_FILE common/dpram.vhd
set_global_assignment -name VHDL_FILE common/keymatrix.vhd
set_global_assignment -name VHDL_FILE common/video.vhd
set_global_assignment -name VHDL_FILE common/cmt.vhd
set_global_assignment -name VHDL_FILE common/z8420/z8420.vhd
set_global_assignment -name VHDL_FILE common/z8420/Interrupt.vhd
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
set_global_assignment -name ALLOW_REGISTER_RETIMING ON
#============================================================
# Functions
#============================================================
set_global_assignment -name VHDL_FILE common/functions.vhd
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
set_global_assignment -name ALLOW_REGISTER_RETIMING ON
set_location_assignment PIN_AA13 -to UART_TX
set_location_assignment PIN_AA11 -to UART_RX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX
#
#set_location_assignment PIN_AF25 -to SPI_MISO
#set_location_assignment PIN_AF28 -to SPI_CS[0]
#set_location_assignment PIN_AF27 -to SPI_MOSI
#set_location_assignment PIN_AH26 -to SPI_SCLK
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MISO
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_CS[0]
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_MOSI
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SPI_SCLK
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MISO
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CS[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_MOSI
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCLK
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SPI_MISO
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

206
sharpmz-lite.sdc Normal file
View File

@@ -0,0 +1,206 @@
## Generated SDC file "sharpmz-lite-div.out.sdc"
## Copyright (C) 2017 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel MegaCore Function License Agreement, or other
## applicable license agreement, including, without limitation,
## that your use is for the sole purpose of programming logic
## devices manufactured by Intel and sold by Intel or its
## authorized distributors. Please refer to the applicable
## agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition"
## DATE "Wed Oct 31 10:26:38 2018"
##
## DEVICE "5CSEBA6U23I7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}]
create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks -create_base_clocks -use_tan_name
# create_generated_clock -name <name> -source <source> -divide_by <ratio: 2,4,8, ....> -duty_cycle 50.00 <generated_clk>
# <name> a name assigned to the generate clock to be used in TQ analysis
# <source> the reference to your master clock
# <generated_clk> in your case this is the lpm_counter port where you pick the generated clock from
# create_generated_clock -name divclk_16mhz -divide_by 2 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[0]}
#set all_enabled_registers ]
#set clock_enable_divide_by_n 4
#set_multicycle_path -setup $clock_enable_divide_by_n -from $all_enabled_registers -to $all_enabled_registers
#set_multicycle_path -hold -from $all_enabled_registers -to $all_enabled_registers
#create_generated_clock -name {CK96M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 192 -divide_by 100 \
# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
#create_generated_clock -name {CK64M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 128 -divide_by 100 \
# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}]
#create_generated_clock -name {CK32M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 64 -divide_by 100 \
# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}]
#create_generated_clock -name {CK16M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 32 -divide_by 100 \
# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}]
#create_generated_clock -name {CK8M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 16 -divide_by 100 \
# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}]
#create_generated_clock -name {CK4M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 8 -divide_by 100 \
# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[5]}]
#create_generated_clock -name {CK2M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 4 -divide_by 100 \
# -master_clock {FPGA_CLK3_50} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[6]}]
#
#create_generated_clock -name {CK56M75} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 591146 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
#create_generated_clock -name {CK28M375} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 295573 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}]
#create_generated_clock -name {CK14M1875} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 147786 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}]
#create_generated_clock -name {CK7M09375} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 73893 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}]
#create_generated_clock -name {CK3M546875} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 36947 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN02|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}]
#
#create_generated_clock -name {CK85M86} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 894375 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
#create_generated_clock -name {CK65M} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 67708 -divide_by 100000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1]}]
#create_generated_clock -name {CK25M175} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 26224 -divide_by 100000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2]}]
#create_generated_clock -name {CK17M734475} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 184734 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3]}]
#create_generated_clock -name {CK8M867237} \
# -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
# -duty_cycle 50/1 -multiply_by 92367 -divide_by 1000000 \
# -master_clock {CK96M} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN03|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4]}]
#
# {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN01|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
#create_generated_clock -name {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 8 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
#create_generated_clock -name {clk_2M} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -duty_cycle 50/1 -multiply_by 1 -divide_by 224 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_registers {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK2Mi}]
#create_generated_clock -name {clk_15611} -source [get_pins {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -duty_cycle 50/1 -multiply_by 1 -divide_by 28698 -master_clock {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_registers {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK15611i}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#set_clock_groups -asynchronous -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] -group [get_clocks {emu|sharp_mz|CLKGEN0|PLLMAIN|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -group [get_clocks { }]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
set_false_path -to [get_ports {VGA_*}]
set_false_path -to [get_ports {AUDIO_SPDIF}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

28
sharpmz.qpf
View File

@@ -1,11 +1,29 @@
# -------------------------------------------------------------------------- #
#
# please keep this file read-only!
# Quartus changes this file everytime revision is switched,
# and it will be marked as changed with every commit.
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 15:03:54 April 29, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.1"
DATE = "23:13:02 April 27, 2017"
QUARTUS_VERSION = "17.1"
DATE = "15:03:54 April 29, 2020"
# Revisions

535
sharpmz.qsf
View File

@@ -23,335 +23,336 @@
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SEED 1
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

113
sharpmz.sdc
View File

@@ -1,30 +1,4 @@
## Generated SDC file "sharpmz.sdc"
## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition"
## DATE "Mon Jul 16 23:49:03 2012"
##
## DEVICE "EP3C16F484C6"
##
## SDC file "sharpmz.sdc"
#**************************************************************
# Time Information
@@ -38,13 +12,24 @@ set_time_format -unit ns -decimal_places 3
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
#create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
#create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
#create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
#create_clock -name {MCLK} -period 10.000 -waveform { 0.000 5.000 } [get_ports {SDRAM_CLK}]
#create_clock -name {SDCLK} -period 100.000 -waveform { 0.000 50.000 } [get_ports {SDIO_CLK}]
#create_clock -name {VMCLK} -period 10.000 -waveform { 0.000 5.000 }
#create_clock -name {CK32Mi} -period 31.250 -waveform { 0.000 15.625 }
#create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
# -name HDMI_CLK [get_ports HDMI_TX_CLK]
#create_generated_clock -source [get_pins -compatibility_mode {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK32Mi}] -name CK32Mi
#create_generated_clock -source {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|CK8Mi} -name CK8Mi
#create_generated_clock -source [get_pins -compatibility_mode {emu:emu|sharpmz:sharp_mz|clkgen:CLKGEN0|pll:PLLMAIN|pll_0002:pll_inst|altera_pll:altera_pll_i|outclk_wire[0]}] -name {CK32Mi} -period 31.250
#-waveform { 0.000 15.625 }
#**************************************************************
# Create Generated Clock
@@ -141,52 +126,52 @@ create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get
#set_output_delay -add_delay -clock [get_clocks {MCLK}] 0.000 [get_ports {SDRAM_nWE}]
#set_output_delay -add_delay -clock [get_clocks {SDCLK}] 0.000 [get_ports {SDIO_CMD}]
#set_output_delay -add_delay -clock [get_clocks {SDCLK}] 0.000 [get_ports {SDIO_DAT[3]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 0.000 [get_ports {altera_reserved_tdo}]
#set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 0.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|*resetlatch}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[33]}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[0]}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_error}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[34]}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|*MonDReg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|*jdo*}]
set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|ir*}]
set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go}]
set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_writedata_d1*|*}] -to [get_registers *]
set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_nativeaddress_d1*|*}] -to [get_registers *]
set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
set_false_path -from [get_keepers -nocase {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
#set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
#set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
#set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
#set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|*resetlatch}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[33]}]
#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_ready}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[0]}]
#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_error}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr[34]}]
#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|*MonDReg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}]
#set_false_path -from [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|*sr*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|*jdo*}]
#set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_sysclk:the_cpu_0_jtag_debug_module_sysclk|ir*}]
#set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*cpu_0:*|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|monitor_go}]
#set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_writedata_d1*|*}] -to [get_registers *]
#set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_nativeaddress_d1*|*}] -to [get_registers *]
#set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
#set_false_path -from [get_keepers -nocase {*the*clock*|slave_readdata_p1*}] -to [get_registers *]
#**************************************************************

1388
sharpmz.vhd
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BIN
software/asm/.sharpmz-test.asm.swo Normal file
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0
asm/1Z-013A.asm → software/asm/1Z-013A.asm
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0
asm/1Z-013A_80c.asm → software/asm/1Z-013A_80c.asm
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897
software/asm/IPL.asm Normal file
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@@ -0,0 +1,897 @@
ORG 0000H
;****************************************************************
;
; Personal Computer
; MZ-80B
;
; Initial Program Loader
;****************************************************************
;
JR START
;
; NST RESET
;
NST: LD A,03H
OUT (PPICTL),A ;Set PC1 NST=1
;
START: LD A,82H ;8255 A=OUT B=IN C=OUT
OUT (PPICTL),A
LD A,0FH ;PIO A=OUT
OUT (PIOCTLA),A
LD A,0CFH ;PIO B=IN
OUT (PIOCTLB),A
LD A,0FFH
OUT (PIOCTLB),A
LD A,58H ;BST=1 NST=0 OPEN=1 WRITE=1
OUT (PPIC),A
LD A,12H
OUT (PPIA),A
XOR A
OUT (GRPHCTL),A ;Set Graphics VRAM to default, input to GRPH I, no output.
LD SP,0FFE0H
LD HL,0D000H
LD A,0B3H
OUT (PIOA),A
CLEAR: LD (HL),00H ;DISPLAY CLEAR
INC HL
LD A,H
OR L
JR NZ,CLEAR
LD A,13H
OUT (PIOA),A
XOR A
LD (DRINO),A
LD (MTFG),A
KEYIN: CALL KEYS1
BIT 3,A ;C - Cassette.
JR Z,CMT
BIT 0,A ;/ - Boot external rom.
JP Z,EXROMT
JR NKIN ;No selection, so standard startup, try FDC then CMT.
;
KEYS1: LD B,14H ;Preserve A4-A7, set A4 to prevent all strobes low, the select line 5 (0-4).
KEYS: IN A,(PIOA)
AND 0F0H
OR B
OUT (PIOA),A
IN A,(PIOB) ;Read the strobed key.
RET
;
;
NKIN: CALL FDCC
JP Z,FD
JR CMT
;
FDCC: LD A,0A5H
LD B,A
OUT (0D9H),A
CALL DLY80U
IN A,(0D9H)
CP B
RET
;
; ;
; CMT CONTROL ;
; ;
;
CMT: CALL MSTOP
CALL DEL6
CALL KYEMES
CALL ?RDI
JR C,ST1
CALL LDMSG
LD HL,NAME
LD E,010H
LD C,010H
CALL DISP2
LD A,(ATRB)
CP 01H
JR NZ,MISMCH
CALL ?RDD
ST1: PUSH AF
CALL DEL6
CALL REW
POP AF
JP C,TRYAG
JP NST
;
MISMCH: LD HL,MES16
LD E,0AH
LD C,0FH
CALL DISP
CALL MSTOP
SCF
JR ST1
;
;READ INFORMATION
; CF=1:ERROR
RDINF:
?RDI: DI
LD D,04H
LD BC,0080H
LD HL,IBUFE
RD1: CALL MOTOR
JR C,STPEIR
CALL TMARK
JR C,STPEIR
CALL RTAPE
JR C,STPEIR
RET2S: BIT 3,D
JR Z,EIRTN
STPEIR: CALL MSTOP
EIRTN: EI
RET
;
;
;READ DATA
RDDAT:
?RDD: DI
LD D,08H
LD BC,(SIZE)
LD HL,8000H
JR RD1
;
;
;READ TAPE
; BC=SIZE
; DE=LOAD ADDRSS
RTAPE: PUSH DE
PUSH BC
PUSH HL
LD H,02H
RTP2: CALL SPDIN
JR C,TRTN1 ;BREAK
JR Z,RTP2
LD D,H
LD HL,0000H
LD (SUMDT),HL
POP HL
POP BC
PUSH BC
PUSH HL
RTP3: CALL RBYTE
JR C,TRTN1
LD (HL),A
INC HL
DEC BC
LD A,B
OR C
JR NZ,RTP3
LD HL,(SUMDT)
CALL RBYTE
JR C,TRTN1
LD E,A
CALL RBYTE
JR C,TRTN1
CP L
JR NZ,RTP5
LD A,E
CP H
JR Z,TRTN1
RTP5: DEC D
JR Z,RTP6
LD H,D
JR RTP2
RTP6: CALL BOOTER
SCF
TRTN1: POP HL
POP BC
POP DE
RET
;EDGE
EDGE: IN A,(PPIB)
CPL
RLCA
RET C ;BREAK
RLCA
JR NC,EDGE ;WAIT ON LOW
EDGE1: IN A,(PPIB)
CPL
RLCA
RET C ;BREAK
RLCA
JR C,EDGE1 ;WAIT ON HIGH
RET
; 1 BYTE READ
; DATA=A
; SUMDT STORE
RBYTE: PUSH HL
LD HL,0800H ; 8 BITS
RBY1: CALL SPDIN
JR C,RBY3 ;BREAK
JR Z,RBY2 ;BIT=0
PUSH HL
LD HL,(SUMDT) ;CHECKSUM
INC HL
LD (SUMDT),HL
POP HL
SCF
RBY2: RL L
DEC H
JR NZ,RBY1
CALL EDGE
LD A,L
RBY3: POP HL
RET
;TAPE MARK DETECT
; E=L:INFORMATION
; E=S:DATA
TMARK: PUSH HL
LD HL,1414H
BIT 3,D
JR NZ,TM0
ADD HL,HL
TM0: LD (TMCNT),HL
TM1: LD HL,(TMCNT)
TM2: CALL SPDIN
JR C,RBY3
JR Z,TM1
DEC H
JR NZ,TM2
TM3: CALL SPDIN
JR C,RBY3
JR NZ,TM1
DEC L
JR NZ,TM3
CALL EDGE
JR RBY3
;READ 1 BIT
SPDIN: CALL EDGE ;WAIT ON HIGH
RET C ;BREAK
CALL DLY2
IN A,(PPIB) ;READ BIT
AND 40H
RET
;
;
;MOTOR ON
MOTOR: PUSH DE
PUSH BC
PUSH HL
IN A,(PPIB)
AND 20H
JR Z,MOTRD
LD HL,MES6
LD E,0AH
LD C,0EH
CALL DISP
CALL OPEN
MOT1: IN A,(PIOB)
CPL
RLCA
JR C,MOTR
IN A,(PPIB)
AND 20H
JR NZ,MOT1
CALL KYEMES
CALL DEL1M
MOTRD: CALL PLAY
MOTR: POP HL
POP BC
POP DE
RET
;
;
;MOTOR STOP
MSTOP: LD A,0DH
OUT (PPICTL),A ;Set PC6 - READ MODE
LD A,1AH
OUT (PPIA),A
CALL DEL6
JR BLK3
;EJECT
OPEN: LD A,08H ;Reset PC4 - EJECT activate
OUT (PPICTL),A
CALL DEL6
LD A,09H
OUT (PPICTL),A ;Set PC4 - Deactivate EJECT
RET
;
;
KYEMES: LD HL,MES3
LD E,04H
LD C,1CH
CALL DISP
RET
;
;PLAY
PLAY: CALL FR
CALL DEL6
LD A,16H
OUT (PPIA),A
JR BLK3
BLK1: CALL DEL6
CALL BLK3
LD A,13H
BLK2: OUT (PPIA),A
BLK3: LD A,12H
OUT (PPIA),A
RET
;
;
FR: LD A,12H
FR1: OUT (PPIA),A
CALL DEL6
LD A,0BH
OUT (PPICTL),A ;Set PC5
CALL DEL6
LD A,0AH
OUT (PPICTL),A ;Reset PC5
RET
RRW: LD A,010H
JR FR1
;REWIND
REW: CALL RRW
JR BLK1
;
;TIMING DEL
DM1: PUSH AF
L0211: XOR A
L0212: DEC A
JR NZ,L0212
DEC BC
LD A,B
OR C
JR NZ,L0211
POP AF
POP BC
RET
DEL6: PUSH BC
LD BC,00E9H ;233D
JR DM1
DEL1M: PUSH BC
LD BC,060FH ;1551D
JR DM1
;
;TAPE DELAY TIMING
;
;
DLY2: LD A,31H
L022B: DEC A
JP NZ,L022B
RET
;
;
;
;
;
LDMSG: LD HL,MES1
LD E,00H
LD C,0EH
JR DISP
;
DISP2: LD A,93H
OUT (PIOA),A
JR DISP1
;
BOOTER: LD HL,MES8
LD E,0AH
LD C,0DH
;
DISP: LD A,93H
OUT (PIOA),A
EXX
LD HL,0D000H
DISP3: LD (HL),00H
INC HL
LD A,H
OR L
JR NZ,DISP3
EXX
DISP1: XOR A
LD B,A
LD D,0D0H
LDIR
LD A,13H
OUT (PIOA),A
RET
;
;
MES1: DB "IPL is loading"
MES3: DB "IPL is looking for a program"
MES6: DB "Make ready CMT"
MES8: DB "Loading error"
MES9: DB "Make ready FD"
MES10: DB "Press F or C"
MES11: DB "F:Floppy diskette"
MES12: DB "C:Cassette tape"
MES13: DB "Drive No? (1-4)"
MES14: DB "This diskette is not master"
MES15: DB "Pressing S key starts the CMT"
MES16: DB "File mode error"
;
IPLMC: DB 01H
DB "IPLPRO"
;
;
;FD
FD: LD IX,IBADR1
XOR A
LD (0CF1EH),A
LD (0CF1FH),A
LD IY,0FFE0H
LD HL,0100H
LD (IY+2),L
LD (IY+3),H
CALL BREAD ;INFORMATION INPUT
LD HL,0CF00H ;MASTER CHECK
LD DE,IPLMC
LD B,06H
MCHECK: LD C,(HL)
LD A,(DE)
CP C
JP NZ,NMASTE
INC HL
INC DE
DJNZ MCHECK
CALL LDMSG
LD HL,0CF07H
LD E,010H
LD C,0AH
CALL DISP2
LD IX,IBADR2
LD HL,(0CF14H)
LD (IY+2),L
LD (IY+3),H
CALL BREAD
CALL MOFF
JP NST
;
;
NODISK: LD HL,MES9
LD E,0AH
LD C,0DH
CALL DISP
JP ERR1
;
; READY CHECK
;
READY: LD A,(MTFG)
RRCA
CALL NC,MTON
LD A,(DRINO) ;DRIVE NO GET
OR 84H
OUT (DM),A ;DRIVE SELECT MOTON
XOR A
CALL DLY60M
LD HL,0000H
REDY0: DEC HL
LD A,H
OR L
JR Z,NODISK
IN A,(CR) ;STATUS GET
CPL
RLCA
JR C,REDY0
LD A,(DRINO)
LD C,A
LD HL,CLBF0
LD B,00H
ADD HL,BC
BIT 0,(HL)
RET NZ
CALL RCLB
SET 0,(HL)
RET
;
; MOTOR ON
;
MTON: LD A,80H
OUT (DM),A
LD B,0AH ;1SEC DELAY
MTD1: LD HL,3C19H
MTD2: DEC HL
LD A,L
OR H
JR NZ,MTD2
DJNZ MTD1
LD A,01H
LD (MTFG),A
RET
;
;SEEK TREATMENT
;
SEEK: LD A,1BH
CPL
OUT (CR),A
CALL BUSY
CALL DLY60M
IN A,(CR)
CPL
AND 99H
RET
;
;MOTOR OFF
;
MOFF: CALL DLY1M
XOR A
OUT (DM),A
LD (CLBF0),A
LD (CLBF1),A
LD (CLBF2),A
LD (CLBF3),A
LD (MTFG),A
RET
;
;RECALIBRATION
;
RCLB: PUSH HL
LD A,0BH
CPL
OUT (CR),A
CALL BUSY
CALL DLY60M
IN A,(CR)
CPL
AND 85H
XOR 04H
POP HL
RET Z
JP ERR
;
;BUSY AND WAIT
;
BUSY: PUSH DE
PUSH HL
CALL DLY80U
LD E,07H
BUSY2: LD HL,0000H
BUSY0: DEC HL
LD A,H
OR L
JR Z,BUSY1
IN A,(CR)
CPL
RRCA
JR C,BUSY0
POP HL
POP DE
RET
;
BUSY1: DEC E
JR NZ,BUSY2
JP ERR
;
;DATA CHECK
;
CONVRT: LD B,00H
LD DE,0010H
LD HL,(0CF1EH)
XOR A
TRANS: SBC HL,DE
JR C,TRANS1
INC B
JR TRANS
TRANS1: ADD HL,DE
LD H,B
INC L
LD (IY+4),H
LD (IY+5),L
DCHK: LD A,(DRINO)
CP 04H
JR NC,DTCK1
LD A,(IY+4)
CP 46H ;70D
JR NC,DTCK1
LD A,(IY+5)
OR A
JR Z,DTCK1
CP 11H ;17D
JR NC,DTCK1
LD A,(IY+2)
OR (IY+3)
RET NZ
DTCK1: JP ERR
;
;SEQUENTIAL READ
;
BREAD: DI
CALL CONVRT
LD A,0AH
LD (RETRY),A
READ1: CALL READY
LD D,(IY+3)
LD A,(IY+2)
OR A
JR Z,RE0
INC D
RE0: LD A,(IY+5)
LD (IY+1),A
LD A,(IY+4)
LD (IY+0),A
PUSH IX
POP HL
RE8: SRL A
CPL
OUT (DR),A
JR NC,RE1
LD A,01H
JR RE2
RE1: LD A,00H
RE2: CPL
OUT (HS),A
CALL SEEK
JR NZ,REE
LD C,0DBH
LD A,(IY+0)
SRL A
CPL
OUT (TR),A
LD A,(IY+1)
CPL
OUT (SCR),A
EXX
LD HL,RE3
PUSH HL
EXX
LD A,94H
CPL
OUT (CR),A
CALL WAIT
RE6: LD B,00H
RE4: IN A,(CR)
RRCA
RET C
RRCA
JR C,RE4
INI
JR NZ,RE4
INC (IY+1)
LD A,(IY+1)
CP 11H ;17D
JR Z,RETS
DEC D
JR NZ,RE6
JR RE5
RETS: DEC D
RE5: LD A,0D8H ;FORCE INTERRUPT
CPL
OUT (CR),A
CALL BUSY
RE3: IN A,(CR)
CPL
AND 0FFH
JR NZ,REE
EXX
POP HL
EXX
LD A,(IY+1)
CP 11H ;17D
JR NZ,REX
LD A,01H
LD (IY+1),A
INC (IY+0)
REX: LD A,D
OR A
JR NZ,RE7
LD A,80H
OUT (DM),A
RET
RE7: LD A,(IY+0)
JR RE8
REE: LD A,(RETRY)
DEC A
LD (RETRY),A
JR Z,ERR
CALL RCLB
JP READ1
;
; WAIT AND BUSY OFF
;
WAIT: PUSH DE
PUSH HL
CALL DLY80U
LD E,08H
WAIT2: LD HL,0000H
WAIT0: DEC HL
LD A,H
OR L
JR Z,WAIT1
IN A,(CR)
CPL
RRCA
JR NC,WAIT0
POP HL
POP DE
RET
WAIT1: DEC E
JR NZ,WAIT2
JR ERR
;
NMASTE: LD HL,MES14
LD E,07H
LD C,1BH ;27D
CALL DISP
JR ERR1
;
; ;
; ERRROR OR BREAK ;
; ;
;
ERR: CALL BOOTER
ERR1: CALL MOFF
TRYAG2: LD SP,0FFE0H
;
;TRYAG
;
TRYAG: CALL FDCC
JR NZ,TRYAG3
LD HL,MES10
LD E,5AH
LD C,0CH ;12D
CALL DISP2
LD E,0ABH
LD C,11H ;17D
CALL DISP2
LD E,0D3H
LD C,0FH ;15D
CALL DISP2
TRYAG1: CALL KEYS1
BIT 3,A
JP Z,CMT
BIT 6,A
JR Z,DNO
JR TRYAG1
DNO: LD HL,MES13 ;DRIVE NO SELECT
LD E,0AH
LD C,0FH
CALL DISP
DNO10: LD D,12H
CALL DNO0
JR NC,DNO3
LD D,18H
CALL DNO0
JR NC,DNO3
JR DNO10
DNO3: LD A,B
LD (DRINO),A
JP FD
;
TRYAG3: LD HL,MES15
LD E,54H
LD C,1DH ;29D
CALL DISP2
TRYAG4: LD B,06H
TRYAG5: CALL KEYS
BIT 3,A
JP Z,CMT
JR TRYAG5
;
DNO0: IN A,(PIOA)
AND 0F0H
OR D
OUT (PIOA),A
IN A,(PIOB)
LD B,00H
LD C,04H
RRCA
DNO1: RRCA
RET NC
INC B
DEC C
JR NZ,DNO1
RET
;
; TIME DELAY (1M &60M &80U )
;
DLY80U: PUSH DE
LD DE,000DH ;13D
JP DLYT
DLY1M: PUSH DE
LD DE,0082H ;130D
JP DLYT
DLY60M: PUSH DE
LD DE,1A2CH ;6700D
DLYT: DEC DE
LD A,E
OR D
JR NZ,DLYT
POP DE
RET
;
;
; ;
; INTRAM EXROM ;
; ;
;
EXROMT: LD HL,8000H
LD IX,EROM1
JR SEROMA
EROM1: IN A,(0F9H)
CP 00H
JP NZ,NKIN
LD IX,EROM2
ERMT1: JR SEROMA
EROM2: IN A,(0F9H)
LD (HL),A
INC HL
LD A,L
OR H
JR NZ,ERMT1
OUT (0F8H),A
JP NST
;
SEROMA: LD A,H
OUT (0F8H),A
LD A,L
OUT (0F9H),A
LD D,04H
SEROMD: DEC D
JR NZ,SEROMD
JP (IX)
;----------------------------------------------------------
; Variables/Work area
;----------------------------------------------------------
IBUFE: EQU 0CF00H
ATRB: EQU 0CF00H
NAME: EQU 0CF01H
SIZE: EQU 0CF12H
DTADR: EQU 0CF14H
SUMDT: EQU 0FFE0H
TMCNT: EQU 0FFE2H
;
;
;INPUT BUFFER ADDRESS
;
IBADR1: EQU 0CF00H
IBADR2: EQU 8000H
;
; SUBROUTINE WORK
;
NTRACK: EQU 0FFE0H
NSECT: EQU 0FFE1H
BSIZE: EQU 0FFE2H
STTR: EQU 0FFE4H
STSE: EQU 0FFE5H
MTFG: EQU 0FFE6H
CLBF0: EQU 0FFE7H
CLBF1: EQU 0FFE8H
CLBF2: EQU 0FFE9H
CLBF3: EQU 0FFEAH
RETRY: EQU 0FFEBH
DRINO: EQU 0FFECH
;
;
;
;
;
; MFM MINIFLOPPY CONTROL
;
;
;
; CASE OF DISK INITIALIZE
; DRIVE NO=DRINO (0-3)
;
; CASE OF SEQUENTIAL READ
; DRIVE NO=DRINO (0-3)
; BYTE SIZE =IY+2,3
; ADDRESS =IX+0,1
; NEXT TRACK =IY+0
; NEXT SECTOR =IY+1
; START TRACK =IY+4
; START SECTOR =IY+5
;
;
; I/O PORT ADDRESS
;
CR: EQU 0D8H ;STATUS/COMMAND PORT
TR: EQU 0D9H ;TRACK REG PORT
SCR: EQU 0DAH ;SECTOR REG PORT
DR: EQU 0DBH ;DATA REG PORT
DM: EQU 0DCH ;MOTOR/DRIVE PORT
HS: EQU 0DDH ;HEAD SIDE SELECT PORT
PPIA: EQU 0E0H
PPIB: EQU 0E1H
PPIC: EQU 0E2H
PPICTL: EQU 0E3H
PIOA: EQU 0E8H
PIOCTLA:EQU 0E9H
PIOB: EQU 0EAH
PIOCTLB:EQU 0EBH
GRPHCTL:EQU 0F4H

0
asm/MZ700.LST → software/asm/MZ700.LST
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0
asm/hi-ramcheck.asm → software/asm/hi-ramcheck.asm
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0
asm/monitor_1Z-013A.asm → software/asm/monitor_1Z-013A.asm
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0
asm/monitor_80c_1Z-013A.asm → software/asm/monitor_80c_1Z-013A.asm
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0
asm/monitor_80c_SA1510.asm → software/asm/monitor_80c_SA1510.asm
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0
asm/monitor_SA1510.asm → software/asm/monitor_SA1510.asm
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0
asm/monitor_mz-1r12.asm → software/asm/monitor_mz-1r12.asm
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0
asm/mz-1e14.asm → software/asm/mz-1e14.asm
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0
asm/mz80kfdif.asm → software/asm/mz80kfdif.asm
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0
asm/quickdisk_mz-1e05.asm → software/asm/quickdisk_mz-1e05.asm
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0
asm/quickdisk_mz-1e14.asm → software/asm/quickdisk_mz-1e14.asm
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0
asm/ramcheck.asm → software/asm/ramcheck.asm
View File

8
asm/sa1510.asm → software/asm/sa1510.asm
View File

@@ -602,15 +602,15 @@ TIMIN: PUSH AF
LD HL,(DSPXY)
RET
LD C,H
PRTHL: LD C,H
POP AF
LD A,H
CALL L03C3
CALL PRTHX
LD A,L
JR L03C3
JR PRTHX
LD B,E
LD B,E
L03C3: PUSH AF
PRTHX: PUSH AF
RRCA
RRCA
RRCA

1780
software/asm/sharpmz-test.asm Normal file
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File diff suppressed because it is too large Load Diff

38
software/mif/ascii_conv.mif Normal file
View File

@@ -0,0 +1,38 @@
DEPTH = 512;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 0D 00 00;
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0020: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F;
0030: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F;
0040: 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F;
0050: 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F;
0060: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
0070: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
0080: 7D 20 20 20 20 20 20 20 20 20 20 5E 20 20 20 20;
0090: 20 20 65 88 7E 20 74 20 68 20 62 78 64 72 70 63;
00a0: 71 61 7A 77 73 75 69 20 D6 6B 66 76 20 FC DF 6A;
00b0: 6E 20 DC 6D 20 20 20 6F 6C C4 F6 E4 20 79 7B 20;
00c0: 7C 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
00d0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
00e0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
00f0: 20 20 20 20 20 20 20 20 20 20 20 A3 20 20 20 20;
0100: 00 00 00 00 00 00 00 00 00 00 00 00 00 0D 00 00;
0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0120: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F;
0130: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F;
0140: 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F;
0150: 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 8B 20;
0160: 93 A1 9A 9F 9C 92 AA 97 98 A6 AF A9 B8 B3 B0 B7;
0170: 9E A0 9D A4 96 A5 AB A3 98 BD A2 BE C0 80 94 20;
0180: 20 20 20 20 20 20 20 20 8B 20 20 20 20 20 20 20;
0190: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
01a0: 20 20 20 FB 20 20 20 20 20 20 20 20 20 20 20 20;
01b0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
01c0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
01d0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
01e0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
01f0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20;
END;

514
mif/combined_cgrom.mif → software/mif/combined_cgrom.mif
View File

@@ -1,4 +1,4 @@
DEPTH = 12288;
DEPTH = 20480;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
@@ -771,4 +771,516 @@ CONTENT BEGIN
2fd0: 00 00 3f 38 fe c6 7c 00 ff 81 a5 81 81 a5 81 ff;
2fe0: e7 81 81 00 00 81 81 e7 00 04 08 fe 10 fe 20 40;
2ff0: 18 24 24 20 10 10 10 10 08 08 08 08 04 24 24 18;
3000: 00 00 00 00 00 00 00 00 18 24 42 7e 42 42 42 00;
3010: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
3020: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
3030: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
3040: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
3050: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
3060: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
3070: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
3080: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
3090: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
30a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
30b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
30c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
30d0: 7e 02 04 18 20 40 7e 00 0c 12 10 38 10 10 3e 00;
30e0: 08 08 08 08 0f 00 00 00 08 08 08 08 f8 00 00 00;
30f0: 08 08 08 08 0f 08 08 08 08 08 08 08 ff 00 00 00;
3100: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
3110: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
3120: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
3130: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
3140: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
3150: 00 00 00 7e 00 00 00 00 00 00 7e 00 7e 00 00 00;
3160: 00 00 08 00 00 08 08 10 00 02 04 08 10 20 40 00;
3170: 00 00 00 00 00 18 18 00 00 00 00 00 00 08 08 10;
3180: 00 ff 00 00 00 00 00 00 40 40 40 40 40 40 40 40;
3190: 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01 ff;
31a0: 00 00 00 ff 00 00 00 00 10 10 10 10 10 10 10 10;
31b0: ff ff 00 00 00 00 00 00 c0 c0 c0 c0 c0 c0 c0 c0;
31c0: 00 00 00 00 00 ff 00 00 04 04 04 04 04 04 04 04;
31d0: 00 00 00 00 ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f;
31e0: 00 00 00 00 00 00 00 ff 01 01 01 01 01 01 01 01;
31f0: 00 00 00 00 00 00 ff ff 03 03 03 03 03 03 03 03;
3200: 10 08 08 04 08 08 10 00 08 1c 3e 7f 7f 1c 3e 00;
3210: ff 7f 3f 1f 0f 07 03 01 ff ff ff ff ff ff ff ff;
3220: 08 1c 3e 7f 3e 1c 08 00 00 00 10 20 7f 20 10 00;
3230: 1c 1c 6b 7f 6b 08 1c 00 00 3c 7e 7e 7e 7e 3c 00;
3240: 00 3c 42 42 42 42 3c 00 3c 42 02 0c 10 00 10 00;
3250: ff c3 81 81 81 81 c3 ff 00 00 00 00 03 04 08 08;
3260: 00 00 00 00 c0 20 10 10 80 c0 e0 f0 f8 fc fe ff;
3270: 01 03 07 0f 1f 3f 7f ff 00 00 08 00 00 08 00 00;
3280: 00 08 1c 2a 08 08 08 00 0e 18 30 60 30 18 0e 00;
3290: 3c 20 20 20 20 20 3c 00 36 7f 7f 7f 3e 1c 08 00;
32a0: 3c 04 04 04 04 04 3c 00 1c 22 4a 56 4c 20 1e 00;
32b0: ff fe fc f8 f0 e0 c0 80 70 18 0c 06 0c 18 70 00;
32c0: 00 08 08 08 2a 1c 08 00 00 40 20 10 08 04 02 00;
32d0: 00 00 04 02 7f 02 04 00 f0 f0 f0 f0 0f 0f 0f 0f;
32e0: 00 00 00 00 0f 08 08 08 00 00 00 00 f8 08 08 08;
32f0: 08 08 08 08 f8 08 08 08 00 00 00 00 ff 08 08 08;
3300: 00 00 01 3e 54 14 14 00 08 08 08 08 00 00 08 00;
3310: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
3320: 08 1e 28 1c 0a 1c 08 00 00 62 64 08 10 26 46 00;
3330: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
3340: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
3350: 00 08 08 3e 08 08 00 00 08 2a 1c 3e 1c 2a 08 00;
3360: 0f 0f 0f 0f f0 f0 f0 f0 81 42 24 18 18 24 42 81;
3370: 10 10 20 c0 00 00 00 00 08 08 04 03 00 00 00 00;
3380: ff 00 00 00 00 00 00 00 80 80 80 80 80 80 80 80;
3390: ff 80 80 80 80 80 80 80 ff 01 01 01 01 01 01 01;
33a0: 00 00 ff 00 00 00 00 00 20 20 20 20 20 20 20 20;
33b0: 01 02 04 08 10 20 40 80 80 40 20 10 08 04 02 01;
33c0: 00 00 00 00 ff 00 00 00 08 08 08 08 08 08 08 08;
33d0: ff ff ff ff 00 00 00 00 f0 f0 f0 f0 f0 f0 f0 f0;
33e0: 00 00 00 00 00 00 ff 00 02 02 02 02 02 02 02 02;
33f0: 00 00 00 00 00 ff ff ff 07 07 07 07 07 07 07 07;
3400: 18 18 18 18 18 18 18 00 00 00 38 04 3c 44 3a 00;
3410: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
3420: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
3430: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
3440: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
3450: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
3460: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
3470: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
3480: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
3490: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
34a0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 46 3a 00;
34b0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
34c0: 00 00 44 28 10 28 44 00 00 00 42 42 46 3a 02 3c;
34d0: 00 00 7e 04 18 20 7e 00 24 00 38 04 3c 44 3a 00;
34e0: 00 00 00 01 02 04 08 10 03 1c 60 80 00 00 00 00;
34f0: c0 38 06 01 00 00 00 00 00 00 00 80 40 20 10 08;
3500: 00 00 00 00 c0 30 0c 03 00 ff 00 00 00 ff 00 00;
3510: 44 44 44 44 44 44 44 44 44 ff 44 44 44 ff 44 44;
3520: 20 10 08 00 00 00 00 00 00 00 00 32 4c 00 00 00;
3530: aa 44 aa 11 aa 44 aa 11 00 00 00 00 03 0c 30 c0;
3540: 03 0c 30 c0 00 00 00 00 c0 30 0c 03 00 00 00 00;
3550: 38 44 44 4a 42 52 4c 00 00 22 00 22 22 26 1a 00;
3560: 00 22 00 1c 22 22 1c 00 42 00 42 42 42 42 3c 00;
3570: 42 18 24 42 7e 42 42 00 42 18 24 42 42 24 18 00;
3580: 10 20 20 40 40 40 80 80 01 06 18 20 20 40 40 80;
3590: 80 60 18 04 04 02 02 01 08 04 04 02 02 02 01 01;
35a0: 80 80 40 40 40 20 20 10 80 40 40 20 20 18 06 01;
35b0: 01 02 02 04 04 18 60 80 01 01 02 02 02 04 04 08;
35c0: 10 08 04 02 01 00 00 00 00 00 00 00 80 60 1c 03;
35d0: 00 00 00 00 01 06 38 c0 08 10 20 40 80 00 00 00;
35e0: 08 10 10 20 10 10 08 00 08 08 08 08 ff 08 08 08;
35f0: 08 14 22 00 00 00 00 00 00 00 00 00 00 00 7e 00;
3600: 1c 1c 3e 1c 08 00 3e 00 ff f7 f7 f7 d5 e3 f7 ff;
3610: ff f7 e3 d5 f7 f7 f7 ff ff ff f7 fb 81 fb f7 ff;
3620: ff ff ef df 81 df ef ff bd bd bd 81 bd bd bd ff;
3630: e3 dd bf bf bf dd e3 ff 18 24 7e ff 5a 24 00 00;
3640: e0 47 42 7e 42 47 e0 00 22 3e 2a 08 08 49 7f 41;
3650: 1c 1c 08 3e 08 08 14 22 00 11 d2 fc d2 11 00 00;
3660: 00 88 4b 3f 4b 88 00 00 22 14 08 08 3e 08 1c 1c;
3670: 3c 7e ff db ff e7 7e 3c 3c 42 81 a5 81 99 42 3c;
3680: aa 55 aa 55 aa 55 aa 55 0a 05 0a 05 0a 05 0a 05;
3690: a0 50 a0 50 a0 50 a0 50 aa 55 aa 55 00 00 00 00;
36a0: 00 00 00 00 aa 55 aa 55 aa 54 a8 50 a0 40 80 00;
36b0: aa 55 2a 15 0a 05 02 01 80 40 a0 50 a8 54 aa 55;
36c0: 00 01 02 05 0a 15 2a 55 80 80 40 40 20 20 10 10;
36d0: 08 08 04 04 02 02 01 01 38 28 38 00 00 00 00 00;
36e0: 00 54 2a 54 2a 54 2a 00 01 01 02 02 04 04 08 08;
36f0: 10 10 20 20 40 40 80 80 00 c0 c8 54 54 55 22 00;
3700: 00 00 00 00 00 02 ff 02 02 02 02 02 02 02 07 02;
3710: 02 02 02 02 02 02 ff 02 00 00 20 50 88 05 02 00;
3720: 00 0e 11 22 c4 04 02 01 11 22 44 88 11 22 44 88;
3730: 00 70 88 44 23 20 40 80 00 c4 a4 94 8f 94 a4 c4;
3740: 00 23 25 29 f1 29 25 23 88 90 a0 c0 c0 a8 98 b8;
3750: a8 b0 b8 c0 c0 a0 90 88 80 40 20 10 1f 20 40 80;
3760: 00 00 24 24 e7 24 24 00 08 08 3e 00 00 3e 08 08;
3770: 08 10 20 10 08 04 02 04 55 aa 55 aa 55 aa 55 aa;
3780: 00 00 00 00 00 00 00 00 00 70 70 70 00 00 00 00;
3790: 00 07 07 07 00 00 00 00 00 77 77 77 00 00 00 00;
37a0: 00 00 00 00 00 70 70 70 00 70 70 70 00 70 70 70;
37b0: 00 07 07 07 00 70 70 70 00 77 77 77 00 70 70 70;
37c0: 00 00 00 00 00 07 07 07 00 70 70 70 00 07 07 07;
37d0: 00 07 07 07 00 07 07 07 00 77 77 77 00 07 07 07;
37e0: 00 00 00 00 00 77 77 77 00 70 70 70 00 77 77 77;
37f0: 00 07 07 07 00 77 77 77 00 77 77 77 00 77 77 77;
3800: 00 00 00 00 00 00 00 00 7c c6 ba ba 82 ba aa ee;
3810: fc 86 ba 84 ba ba 86 fc 7e c2 be a0 a0 be c2 7e;
3820: f8 8c b6 aa aa b6 8c f8 fe 82 be 88 88 be 82 fe;
3830: fe 82 be 88 b8 a0 a0 e0 7e 82 be a0 ae ba 82 7e;
3840: ee aa ba 82 ba aa aa ee fe 82 ee 28 28 ee 82 fe;
3850: 1f 11 1b 0a ea ba c6 7c e6 aa b4 88 88 b4 aa e6;
3860: e0 a0 a0 a0 a0 be 82 fe fe 82 aa aa ba aa aa ee;
3870: ee 9a 8a a2 b2 aa aa ee 7c c6 ba aa aa ba c6 7c;
3880: fc 86 ba ba 86 bc a0 e0 7c c6 ba ba aa b2 c2 7c;
3890: fc 86 ba ba 84 b4 aa e6 7e c2 be c4 7a fa 86 fc;
38a0: fe 82 ee 28 28 28 28 38 ee aa aa aa aa ba c6 7c;
38b0: ee aa aa aa aa 54 28 10 ee aa aa ba aa aa 82 fe;
38c0: c6 aa 54 28 28 54 aa c6 ee aa 92 44 28 28 28 38;
38d0: fe 82 fa 14 28 5e 82 fe 00 40 a0 90 ff 7e 00 00;
38e0: 00 02 05 09 ff 7e 00 00 00 7c d6 7c 38 54 92 00;
38f0: 92 54 38 fe 38 54 92 00 00 00 38 54 fe 00 00 00;
3900: 7c 82 b2 aa aa 9a 82 7c 38 48 68 28 28 6c 44 7c;
3910: 7c 82 ba ca 14 2e 42 fe fc 82 fa 22 22 fa 82 fc;
3920: 0c 14 24 54 b6 82 f6 1c fe 82 be 84 7a fa 86 fc;
3930: 7e 82 be bc 82 ba 82 7c fe 82 fa 14 28 50 50 70;
3940: 7c 82 ba 7c 82 ba 82 7c 7c 82 ba 82 7a fa 82 fc;
3950: f8 88 be aa fa 22 3e 00 1f 11 7d 55 5f 44 7c 00;
3960: 3c 5a ff e7 7e 24 42 81 3c 5a ff e7 7e 24 24 66;
3970: 08 1c 2a 7f 77 3e 36 63 08 1c 2a 7f 77 3e 36 14;
3980: 41 a2 3c 5a 7e ff 42 63 82 45 3c 5a 7e ff 42 c6;
3990: 00 5a bd 99 24 42 24 00 81 a5 5a 18 18 24 c3 00;
39a0: 00 24 7e bd 7e 24 24 e7 24 7e bd 7e 24 42 42 c3;
39b0: 3c 5a ff ab d5 ff dd 89 3c 5a ff ab d5 ff 77 22;
39c0: 3c 42 a5 81 99 81 d5 aa 3c 42 a5 81 99 81 ab 55;
39d0: 42 42 66 e7 ff ff 7e 3c 1c fe 3f 0f 0f 3f fe 1c;
39e0: 3c 7e ff ff e7 66 42 42 38 7f fc f0 f0 fc 7f 38;
39f0: 3c 7e ff ff ff ff 7e 3c 10 38 28 28 28 7c fe d6;
3a00: 00 03 07 7e c7 7e 07 03 6b 7f 3e 14 14 14 1c 08;
3a10: 00 c0 e0 7e e3 7e e0 c0 3c 0c 3c 18 3c 76 76 46;
3a20: 3c 24 3c 18 3c 5a 5a 7e 3c 30 3c 18 3c 6e 6e 62;
3a30: 7e 7e 24 24 24 24 24 6c 7e 7e 24 24 24 24 24 66;
3a40: 7e 7e 24 24 24 24 24 36 22 63 f7 b7 ff 7e 3c 3c;
3a50: 38 6c ff 3f 0f 3f fc 38 3c 3c 7e ff ed ef c6 44;
3a60: 1c 36 ff fc f0 fc 3f 1e 3c 7e ff bf ff 7e 3c 3c;
3a70: 3c 3c 7e ff fd ff 7e 3c 1c 36 ff ff ff ff 3e 1c;
3a80: 38 6c ff ff ff ff 7c 38 18 3c 3c 3c 3c 18 3c 3c;
3a90: 00 00 7b ff ff 7b 00 00 3c 3c 18 3c 3c 3c 3c 18;
3aa0: 00 00 de ff ff de 00 00 20 60 20 20 30 28 3c 3c;
3ab0: 00 40 ff 0b 07 03 00 00 3c 3c 14 0c 04 04 06 04;
3ac0: 00 02 ff d0 e0 c0 00 00 10 10 38 7c 92 10 10 38;
3ad0: 00 08 10 31 ff 31 10 08 38 10 10 92 7c 38 10 10;
3ae0: 00 10 08 8c ff 8c 08 10 00 78 60 50 48 04 02 00;
3af0: 00 02 04 48 50 60 78 00 00 40 20 12 0a 06 1e 00;
3b00: 00 1e 06 0a 12 20 40 00 18 7e 7e ff c3 81 81 81;
3b10: 1f 78 70 f0 f0 70 78 1f 81 81 81 c3 ff 7e 7e 18;
3b20: f8 1e 0e 0f 0f 0e 1e f8 bf a1 ad a5 a5 bd 81 ff;
3b30: ff 81 bd a5 85 fd 01 ff ff 81 bd a5 a5 b5 85 fd;
3b40: ff 80 bf a1 a5 bd 81 ff 00 18 00 3c 00 7e 00 ff;
3b50: 01 05 15 55 55 15 05 01 ff 00 7e 00 3c 00 18 00;
3b60: 80 a0 a8 aa aa a8 a0 80 00 08 1c 3e 00 08 1c 3e;
3b70: 00 00 11 33 77 33 11 00 00 3e 1c 08 00 3e 1c 08;
3b80: 00 00 44 66 77 66 44 00 00 00 e7 a5 e7 00 00 00;
3b90: 10 38 54 10 10 54 38 10 00 00 24 42 ff 42 24 00;
3ba0: 7f 41 22 1c 08 08 08 7f 55 55 55 55 55 55 55 55;
3bb0: ff 00 ff 00 ff 00 ff 00 a5 42 a5 00 00 a5 42 a5;
3bc0: 24 42 81 00 00 81 42 24 ff 80 9f a0 a0 a0 a0 a0;
3bd0: ff 01 e5 11 15 11 15 11 00 00 00 ff a0 af a0 ff;
3be0: 00 00 00 ff 41 41 55 ff a0 9f 80 ff 30 30 30 78;
3bf0: 11 e1 01 ff 0c 0c 0c 1e 80 aa 80 95 80 8f 80 ff;
3c00: 01 a9 01 51 01 e1 01 ff 3c 42 ab d5 10 10 14 08;
3c10: 00 00 18 24 24 18 00 00 00 18 24 42 42 24 18 00;
3c20: 3c 42 81 81 81 81 42 3c 00 00 00 18 18 00 00 00;
3c30: 00 00 3c 3c 3c 3c 00 00 00 7e 7e 7e 7e 7e 7e 00;
3c40: 3c 42 9d a1 a1 9d 42 3c ff ff ff e7 e7 ff ff ff;
3c50: ff ff c3 c3 c3 c3 ff ff ff 81 81 81 81 81 81 ff;
3c60: 20 30 20 20 ff 7e 3c 00 3c 42 81 ff ff 81 42 3c;
3c70: 3c 5a 99 99 99 99 5a 3c 3c 5a 99 ff ff 99 5a 3c;
3c80: 00 28 fe aa fe 54 38 10 0f 30 40 4e 8a 8e 80 81;
3c90: f0 0c 02 72 51 71 01 81 0f 30 40 40 8e 80 80 81;
3ca0: f0 0c 02 02 71 01 01 81 81 80 88 84 43 40 30 0f;
3cb0: 81 01 11 21 c2 02 0c f0 81 80 80 87 40 40 30 0f;
3cc0: 81 01 01 e1 02 02 0c f0 81 80 83 84 43 40 30 0f;
3cd0: 81 01 c1 21 c2 02 0c f0 81 80 87 88 48 40 30 0f;
3ce0: 81 01 e1 11 12 02 0c f0 08 10 54 fe fe fe fe 7c;
3cf0: 00 06 08 10 30 78 78 30 00 52 34 06 60 2c 4a 00;
3d00: 91 52 00 03 c0 00 4a 89 80 c0 e0 f0 ff ff ff ff;
3d10: 00 00 01 02 ff c3 c3 ff 00 00 80 40 ff c3 c3 ff;
3d20: 00 c0 20 10 fc fe ff fc 01 03 07 0f ff ff ff ff;
3d30: 02 14 28 08 14 14 08 00 00 fe 42 20 10 20 42 fe;
3d40: 00 03 04 08 3f 7f ff 3f 00 20 10 10 10 28 48 86;
3d50: 00 3c 42 42 42 24 a5 e7 00 44 82 82 92 6c 00 00;
3d60: 00 00 6c 92 92 6c 00 00 00 02 6c 90 90 6e 00 00;
3d70: 00 1e 10 50 50 b0 10 00 00 00 10 00 7c 00 10 00;
3d80: 00 f1 5b 55 55 51 51 00 ff 89 91 c5 a3 89 91 ff;
3d90: ff c3 a5 99 99 a5 c3 ff 00 92 54 38 ee 38 54 92;
3da0: ff 99 99 ff ff 99 99 ff 92 54 38 10 10 10 10 10;
3db0: 38 10 38 10 38 10 38 10 00 00 00 aa ff aa 00 00;
3dc0: 00 10 10 7c 10 10 00 7c 7e 42 7e 42 7e 42 7e 42;
3dd0: 00 ff 55 55 55 55 ff 00 00 00 00 c0 b0 8c 83 ff;
3de0: 00 00 00 03 0d 31 c1 ff 00 00 00 00 3c 7e ff ff;
3df0: ff ff 7e 3c 00 00 00 00 c0 e0 f0 f0 f0 f0 e0 c0;
3e00: 03 07 0f 0f 0f 0f 07 03 03 0c 3f 3f ff 7f 37 1f;
3e10: c0 30 b8 dc ee f6 fb fb 0e 0e 0a 04 01 01 03 0f;
3e20: 7a 74 f4 f4 f4 fa fd fd 04 4e e4 46 6f 7f 60 3f;
3e30: 20 72 27 62 f6 fe 06 fc 3b 31 1b 1f 10 1f 0f 07;
3e40: dc 8c d8 f8 08 f8 f0 e0 01 03 07 06 0e 3e 70 30;
3e50: 80 c0 e0 60 70 7c 0e 0c 1e 0e 06 07 03 37 7f 8b;
3e60: 78 70 60 e0 c0 ec fe d1 01 33 7b 59 8c df 7f 3f;
3e70: 80 cc de 9a 31 fb fe fc 3f 1f 1f 0f 0f 7f 00 ff;
3e80: fc f8 f8 f0 f0 fe 00 ff 00 01 02 04 02 01 1f 1f;
3e90: 00 80 40 20 40 80 f8 f8 02 02 02 02 1f 20 7f 00;
3ea0: 40 40 40 40 f8 04 fe 00 73 73 73 7f 3f 1f 0f 0f;
3eb0: ce ce ce fe fc f8 f0 f0 0f 0f 0f 18 7f 40 7f ff;
3ec0: f0 f0 f0 18 fe 02 fe ff f8 44 42 21 21 42 44 f8;
3ed0: ff 05 07 00 00 07 05 ff fc 86 82 81 81 82 86 fc;
3ee0: 00 00 80 40 7f 80 00 00 00 00 00 00 ff 01 01 01;
3ef0: 01 01 01 01 ff 00 00 00 ff 80 80 80 80 00 00 00;
3f00: 00 00 00 00 80 80 80 ff 00 08 0c 0a f9 0a 0c 08;
3f10: 00 08 0c 3a e9 3a 0c 08 1f 28 48 fe 88 88 8f 00;
3f20: 40 c0 40 e6 09 02 04 0f 40 c0 40 e2 06 0a 1f 02;
3f30: 40 c0 40 ef 01 07 01 0f 40 a0 20 4f e1 07 01 0f;
3f40: c0 60 18 06 18 60 80 fe 01 06 18 60 18 06 01 7f;
3f50: 00 01 06 1d 2a 2a 2a 1f 1b 8f 65 11 c9 a9 b1 f3;
3f60: 4c f7 f0 18 07 02 3e fe 7f 9f 31 41 81 81 f9 fd;
3f70: 88 02 40 00 88 41 00 91 40 01 88 00 40 04 80 11;
3f80: 00 30 58 fd ff 79 30 00 00 0c 1a bf ff 9e 0c 00;
3f90: 00 30 58 fd 3f f9 30 00 00 0c 1a bf fc 9f 0c 00;
3fa0: 10 28 68 bc fc 78 10 38 ba ee aa 38 38 ba fe ba;
3fb0: ba fe ba 38 38 aa ee ba 00 e7 42 ff 9f ff 42 e7;
3fc0: 00 e7 42 ff f9 ff 42 e7 00 00 fc 1c 7f 63 3e 00;
3fd0: 00 00 3f 38 fe c6 7c 00 ff 81 a5 81 81 a5 81 ff;
3fe0: e7 81 81 00 00 81 81 e7 00 04 08 fe 10 fe 20 40;
3ff0: 18 24 24 20 10 10 10 10 08 08 08 08 04 24 24 18;
4000: 00 00 00 00 00 00 00 00 1c 14 14 77 22 14 08 00;
4010: 08 14 22 77 14 14 1c 00 08 0c 7a 41 7a 0c 08 00;
4020: 08 18 2f 41 2f 18 08 00 77 55 5d 41 5d 55 77 00;
4030: 1e 21 4f 50 4f 21 1e 00 00 00 00 00 00 00 00 00;
4040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
40a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
40b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
40c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
40d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
40e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
40f0: 00 00 00 00 00 00 00 00 aa 55 aa 55 aa 55 aa 55;
4100: 00 00 00 00 00 00 00 00 08 08 08 08 00 00 08 00;
4110: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
4120: 08 1e 28 1c 0a 3c 08 00 00 62 64 08 10 26 46 00;
4130: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
4140: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
4150: 08 2a 1c 3e 1c 2a 08 00 00 08 08 3e 08 08 00 00;
4160: 00 00 00 00 00 08 08 10 00 00 00 7e 00 00 00 00;
4170: 00 00 00 00 00 18 18 00 00 02 04 08 10 20 40 00;
4180: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
4190: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
41a0: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
41b0: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
41c0: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
41d0: 00 00 08 00 00 08 00 00 00 00 08 00 00 08 08 10;
41e0: 0e 18 30 60 30 18 0e 00 00 00 7e 00 7e 00 00 00;
41f0: 70 18 0c 06 0c 18 70 00 3c 42 02 0c 10 00 10 00;
4200: 1c 22 4a 56 4c 20 1e 00 18 24 42 7e 42 42 42 00;
4210: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
4220: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
4230: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
4240: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
4250: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
4260: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
4270: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
4280: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
4290: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
42a0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
42b0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
42c0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
42d0: 7e 02 04 18 20 40 7e 00 3c 20 20 20 20 20 3c 00;
42e0: 00 40 20 10 08 04 02 00 3c 04 04 04 04 04 3c 00;
42f0: 08 14 22 00 00 00 00 00 ff 00 00 00 00 00 00 00;
4300: 20 10 08 00 00 00 00 00 00 00 3c 04 3c 44 3a 00;
4310: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
4320: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
4330: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
4340: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
4350: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
4360: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
4370: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
4380: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
4390: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
43a0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 46 3a 00;
43b0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
43c0: 00 00 42 24 18 24 42 00 00 00 42 42 46 3a 02 3c;
43d0: 00 00 7e 04 18 20 7e 00 08 10 10 20 10 10 08 00;
43e0: 18 18 18 18 18 18 18 00 10 08 08 04 08 08 10 00;
43f0: 00 00 00 32 4c 00 00 00 00 7c 04 04 15 0e 04 00;
4400: 28 28 28 28 28 28 28 28 00 08 08 08 2a 1c 08 00;
4410: 00 08 1c 2a 08 08 08 00 00 08 04 7e 04 08 00 00;
4420: 00 10 20 7e 20 10 00 00 08 1c 3e 7f 7f 1c 3e 00;
4430: 36 7f 7f 7f 3e 1c 08 00 08 1c 3e 7f 3e 1c 08 00;
4440: 1c 1c 6b 7f 6b 08 1c 00 10 10 10 1f 1f 10 10 10;
4450: 10 10 10 f0 f0 10 10 10 00 00 00 ff 28 28 28 28;
4460: 28 28 28 ff 00 00 00 00 28 28 28 ff ff 28 28 28;
4470: 10 10 10 ff ff 10 10 10 28 28 28 ff 28 28 28 28;
4480: 00 00 00 ff ff 00 00 00 22 14 3e 08 3e 08 08 00;
4490: 0c 12 10 38 10 10 3e 00 00 3c 7e 7e 7e 7e 3c 00;
44a0: 00 3c 42 42 42 42 3c 00 00 00 00 f0 10 10 10 10;
44b0: 10 10 10 f0 00 00 00 00 00 00 00 1f 10 10 10 10;
44c0: 10 10 10 1f 00 00 00 00 10 10 10 ff 10 10 10 10;
44d0: 10 10 10 10 10 10 10 10 00 00 00 ff 00 00 00 00;
44e0: 10 10 10 ff 00 00 00 00 00 00 00 ff 10 10 10 10;
44f0: 10 10 10 f0 10 10 10 10 10 10 10 1f 10 10 10 10;
4500: ff ff ff ff ff ff ff ff f7 f7 f7 f7 ff ff f7 ff;
4510: db db db ff ff ff ff ff db db 81 db 81 db db ff;
4520: f7 e1 d7 e3 f5 c3 f7 ff ff 9d 9b f7 ef d9 b9 ff;
4530: cf b7 b7 cf b5 bb c5 ff fb f7 ef ff ff ff ff ff;
4540: fb f7 ef ef ef f7 fb ff df ef f7 f7 f7 ef df ff;
4550: f7 d5 e3 c1 e3 d5 f7 ff ff f7 f7 c1 f7 f7 ff ff;
4560: ff ff ff ff ff f7 f7 ef ff ff ff 81 ff ff ff ff;
4570: ff ff ff ff ff e7 e7 ff ff fd fb f7 ef df bf ff;
4580: c3 bd b9 a5 9d bd c3 ff f7 e7 d7 f7 f7 f7 c1 ff;
4590: c3 bd fd f3 cf bf 81 ff c3 bd fd c3 fd bd c3 ff;
45a0: fb f3 eb db 81 fb fb ff 81 bf 87 fb fd bb c7 ff;
45b0: e3 df bf 83 bd bd c3 ff 81 bd fb f7 ef ef ef ff;
45c0: c3 bd bd c3 bd bd c3 ff c3 bd bd c1 fd fb c7 ff;
45d0: ff ff f7 ff ff f7 ff ff ff ff f7 ff ff f7 f7 ef;
45e0: f1 e7 cf 9f cf e7 f1 ff ff ff 81 ff 81 ff ff ff;
45f0: 8f e7 f3 f9 f3 e7 8f ff c3 bd fd f3 ef ff ef ff;
4600: e3 dd b5 a9 b3 df e1 ff e7 db bd 81 bd bd bd ff;
4610: 83 dd dd c3 dd dd 83 ff e3 dd bf bf bf dd e3 ff;
4620: 87 db dd dd dd db 87 ff 81 bf bf 87 bf bf 81 ff;
4630: 81 bf bf 87 bf bf bf ff e3 dd bf b1 bd dd e3 ff;
4640: bd bd bd 81 bd bd bd ff e3 f7 f7 f7 f7 f7 e3 ff;
4650: f1 fb fb fb fb bb c7 ff bd bb b7 8f b7 bb bd ff;
4660: bf bf bf bf bf bf 81 ff bd 99 a5 a5 bd bd bd ff;
4670: bd 9d ad b5 b9 bd bd ff e7 db bd bd bd db e7 ff;
4680: 83 bd bd 83 bf bf bf ff e7 db bd bd b5 db e5 ff;
4690: 83 bd bd 83 b7 bb bd ff c3 bd bf c3 fd bd c3 ff;
46a0: c1 f7 f7 f7 f7 f7 f7 ff bd bd bd bd bd bd c3 ff;
46b0: bd bd bd db db e7 e7 ff bd bd bd a5 a5 99 bd ff;
46c0: bd bd db e7 db bd bd ff dd dd dd e3 f7 f7 f7 ff;
46d0: 81 fd fb e7 df bf 81 ff c3 df df df df df c3 ff;
46e0: ff bf df ef f7 fb fd ff c3 fb fb fb fb fb c3 ff;
46f0: f7 eb dd ff ff ff ff ff 00 ff ff ff ff ff ff ff;
4700: df ef f7 ff ff ff ff ff ff ff c3 fb c3 bb c5 ff;
4710: bf bf a3 9d bd 9d a3 ff ff ff c3 bd bf bd c3 ff;
4720: fd fd c5 b9 bd b9 c5 ff ff ff c3 bd 81 bf c3 ff;
4730: f3 ed ef 83 ef ef ef ff ff ff c5 b9 b9 c5 fd c3;
4740: bf bf a3 9d bd bd bd ff f7 ff e7 f7 f7 f7 e3 ff;
4750: fb ff f3 fb fb fb bb c7 bf bf bb b7 af 97 bb ff;
4760: e7 f7 f7 f7 f7 f7 e3 ff ff ff 89 b6 b6 b6 b6 ff;
4770: ff ff a3 9d bd bd bd ff ff ff c3 bd bd bd c3 ff;
4780: ff ff a3 9d 9d a3 bf bf ff ff c5 b9 b9 c5 fd fd;
4790: ff ff a3 9d bf bf bf ff ff ff c1 bf c3 fd 83 ff;
47a0: ef ef 83 ef ef ed f3 ff ff ff bd bd bd b9 c5 ff;
47b0: ff ff bd bd bd db e7 ff ff ff be b6 b6 b6 c9 ff;
47c0: ff ff bd db e7 db bd ff ff ff bd bd b9 c5 fd c3;
47d0: ff ff 81 fb e7 df 81 ff f7 ef ef df ef ef f7 ff;
47e0: e7 e7 e7 e7 e7 e7 e7 ff ef f7 f7 fb f7 f7 ef ff;
47f0: ff ff ff cd b3 ff ff ff 00 00 01 3e 54 14 14 00;
4800: 00 00 00 00 00 00 00 00 1c 14 14 77 22 14 08 00;
4810: 08 14 22 77 14 14 1c 00 08 0c 7a 41 7a 0c 08 00;
4820: 08 18 2f 41 2f 18 08 00 77 55 5d 41 5d 55 77 00;
4830: 1e 21 4f 50 4f 21 1e 00 00 00 00 00 00 00 00 00;
4840: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4870: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
4890: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
48a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
48b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
48c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
48d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
48e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
48f0: 00 00 00 00 00 00 00 00 aa 55 aa 55 aa 55 aa 55;
4900: 00 00 00 00 00 00 00 00 08 08 08 08 00 00 08 00;
4910: 24 24 24 00 00 00 00 00 24 24 7e 24 7e 24 24 00;
4920: 08 1e 28 1c 0a 3c 08 00 00 62 64 08 10 26 46 00;
4930: 30 48 48 30 4a 44 3a 00 04 08 10 00 00 00 00 00;
4940: 04 08 10 10 10 08 04 00 20 10 08 08 08 10 20 00;
4950: 08 2a 1c 3e 1c 2a 08 00 00 08 08 3e 08 08 00 00;
4960: 00 00 00 00 00 08 08 10 00 00 00 7e 00 00 00 00;
4970: 00 00 00 00 00 18 18 00 00 02 04 08 10 20 40 00;
4980: 3c 42 46 5a 62 42 3c 00 08 18 28 08 08 08 3e 00;
4990: 3c 42 02 0c 30 40 7e 00 3c 42 02 3c 02 42 3c 00;
49a0: 04 0c 14 24 7e 04 04 00 7e 40 78 04 02 44 38 00;
49b0: 1c 20 40 7c 42 42 3c 00 7e 42 04 08 10 10 10 00;
49c0: 3c 42 42 3c 42 42 3c 00 3c 42 42 3e 02 04 38 00;
49d0: 00 00 08 00 00 08 00 00 00 00 08 00 00 08 08 10;
49e0: 0e 18 30 60 30 18 0e 00 00 00 7e 00 7e 00 00 00;
49f0: 70 18 0c 06 0c 18 70 00 3c 42 02 0c 10 00 10 00;
4a00: 1c 22 4a 56 4c 20 1e 00 18 24 42 7e 42 42 42 00;
4a10: 7c 22 22 3c 22 22 7c 00 1c 22 40 40 40 22 1c 00;
4a20: 78 24 22 22 22 24 78 00 7e 40 40 78 40 40 7e 00;
4a30: 7e 40 40 78 40 40 40 00 1c 22 40 4e 42 22 1c 00;
4a40: 42 42 42 7e 42 42 42 00 1c 08 08 08 08 08 1c 00;
4a50: 0e 04 04 04 04 44 38 00 42 44 48 70 48 44 42 00;
4a60: 40 40 40 40 40 40 7e 00 42 66 5a 5a 42 42 42 00;
4a70: 42 62 52 4a 46 42 42 00 18 24 42 42 42 24 18 00;
4a80: 7c 42 42 7c 40 40 40 00 18 24 42 42 4a 24 1a 00;
4a90: 7c 42 42 7c 48 44 42 00 3c 42 40 3c 02 42 3c 00;
4aa0: 3e 08 08 08 08 08 08 00 42 42 42 42 42 42 3c 00;
4ab0: 42 42 42 24 24 18 18 00 42 42 42 5a 5a 66 42 00;
4ac0: 42 42 24 18 24 42 42 00 22 22 22 1c 08 08 08 00;
4ad0: 7e 02 04 18 20 40 7e 00 3c 20 20 20 20 20 3c 00;
4ae0: 00 40 20 10 08 04 02 00 3c 04 04 04 04 04 3c 00;
4af0: 08 14 22 00 00 00 00 00 ff 00 00 00 00 00 00 00;
4b00: 20 10 08 00 00 00 00 00 00 00 3c 04 3c 44 3a 00;
4b10: 40 40 5c 62 42 62 5c 00 00 00 3c 42 40 42 3c 00;
4b20: 02 02 3a 46 42 46 3a 00 00 00 3c 42 7e 40 3c 00;
4b30: 0c 12 10 7c 10 10 10 00 00 00 3a 46 46 3a 02 3c;
4b40: 40 40 5c 62 42 42 42 00 08 00 18 08 08 08 1c 00;
4b50: 04 00 0c 04 04 04 44 38 40 40 44 48 50 68 44 00;
4b60: 18 08 08 08 08 08 1c 00 00 00 76 49 49 49 49 00;
4b70: 00 00 5c 62 42 42 42 00 00 00 3c 42 42 42 3c 00;
4b80: 00 00 5c 62 62 5c 40 40 00 00 3a 46 46 3a 02 02;
4b90: 00 00 5c 62 40 40 40 00 00 00 3e 40 3c 02 7c 00;
4ba0: 10 10 7c 10 10 12 0c 00 00 00 42 42 42 46 3a 00;
4bb0: 00 00 42 42 42 24 18 00 00 00 41 49 49 49 36 00;
4bc0: 00 00 42 24 18 24 42 00 00 00 42 42 46 3a 02 3c;
4bd0: 00 00 7e 04 18 20 7e 00 08 10 10 20 10 10 08 00;
4be0: 18 18 18 18 18 18 18 00 10 08 08 04 08 08 10 00;
4bf0: 00 00 00 32 4c 00 00 00 00 7c 04 04 15 0e 04 00;
4c00: 28 28 28 28 28 28 28 28 00 08 08 08 2a 1c 08 00;
4c10: 00 08 1c 2a 08 08 08 00 00 08 04 7e 04 08 00 00;
4c20: 00 10 20 7e 20 10 00 00 08 1c 3e 7f 7f 1c 3e 00;
4c30: 36 7f 7f 7f 3e 1c 08 00 08 1c 3e 7f 3e 1c 08 00;
4c40: 1c 1c 6b 7f 6b 08 1c 00 10 10 10 1f 1f 10 10 10;
4c50: 10 10 10 f0 f0 10 10 10 00 00 00 ff 28 28 28 28;
4c60: 28 28 28 ff 00 00 00 00 28 28 28 ff ff 28 28 28;
4c70: 10 10 10 ff ff 10 10 10 28 28 28 ff 28 28 28 28;
4c80: 00 00 00 ff ff 00 00 00 22 14 3e 08 3e 08 08 00;
4c90: 0c 12 10 38 10 10 3e 00 00 3c 7e 7e 7e 7e 3c 00;
4ca0: 00 3c 42 42 42 42 3c 00 00 00 00 f0 10 10 10 10;
4cb0: 10 10 10 f0 00 00 00 00 00 00 00 1f 10 10 10 10;
4cc0: 10 10 10 1f 00 00 00 00 10 10 10 ff 10 10 10 10;
4cd0: 10 10 10 10 10 10 10 10 00 00 00 ff 00 00 00 00;
4ce0: 10 10 10 ff 00 00 00 00 00 00 00 ff 10 10 10 10;
4cf0: 10 10 10 f0 10 10 10 10 10 10 10 1f 10 10 10 10;
4d00: ff ff ff ff ff ff ff ff f7 f7 f7 f7 ff ff f7 ff;
4d10: db db db ff ff ff ff ff db db 81 db 81 db db ff;
4d20: f7 e1 d7 e3 f5 c3 f7 ff ff 9d 9b f7 ef d9 b9 ff;
4d30: cf b7 b7 cf b5 bb c5 ff fb f7 ef ff ff ff ff ff;
4d40: fb f7 ef ef ef f7 fb ff df ef f7 f7 f7 ef df ff;
4d50: f7 d5 e3 c1 e3 d5 f7 ff ff f7 f7 c1 f7 f7 ff ff;
4d60: ff ff ff ff ff f7 f7 ef ff ff ff 81 ff ff ff ff;
4d70: ff ff ff ff ff e7 e7 ff ff fd fb f7 ef df bf ff;
4d80: c3 bd b9 a5 9d bd c3 ff f7 e7 d7 f7 f7 f7 c1 ff;
4d90: c3 bd fd f3 cf bf 81 ff c3 bd fd c3 fd bd c3 ff;
4da0: fb f3 eb db 81 fb fb ff 81 bf 87 fb fd bb c7 ff;
4db0: e3 df bf 83 bd bd c3 ff 81 bd fb f7 ef ef ef ff;
4dc0: c3 bd bd c3 bd bd c3 ff c3 bd bd c1 fd fb c7 ff;
4dd0: ff ff f7 ff ff f7 ff ff ff ff f7 ff ff f7 f7 ef;
4de0: f1 e7 cf 9f cf e7 f1 ff ff ff 81 ff 81 ff ff ff;
4df0: 8f e7 f3 f9 f3 e7 8f ff c3 bd fd f3 ef ff ef ff;
4e00: e3 dd b5 a9 b3 df e1 ff e7 db bd 81 bd bd bd ff;
4e10: 83 dd dd c3 dd dd 83 ff e3 dd bf bf bf dd e3 ff;
4e20: 87 db dd dd dd db 87 ff 81 bf bf 87 bf bf 81 ff;
4e30: 81 bf bf 87 bf bf bf ff e3 dd bf b1 bd dd e3 ff;
4e40: bd bd bd 81 bd bd bd ff e3 f7 f7 f7 f7 f7 e3 ff;
4e50: f1 fb fb fb fb bb c7 ff bd bb b7 8f b7 bb bd ff;
4e60: bf bf bf bf bf bf 81 ff bd 99 a5 a5 bd bd bd ff;
4e70: bd 9d ad b5 b9 bd bd ff e7 db bd bd bd db e7 ff;
4e80: 83 bd bd 83 bf bf bf ff e7 db bd bd b5 db e5 ff;
4e90: 83 bd bd 83 b7 bb bd ff c3 bd bf c3 fd bd c3 ff;
4ea0: c1 f7 f7 f7 f7 f7 f7 ff bd bd bd bd bd bd c3 ff;
4eb0: bd bd bd db db e7 e7 ff bd bd bd a5 a5 99 bd ff;
4ec0: bd bd db e7 db bd bd ff dd dd dd e3 f7 f7 f7 ff;
4ed0: 81 fd fb e7 df bf 81 ff c3 df df df df df c3 ff;
4ee0: ff bf df ef f7 fb fd ff c3 fb fb fb fb fb c3 ff;
4ef0: f7 eb dd ff ff ff ff ff 00 ff ff ff ff ff ff ff;
4f00: df ef f7 ff ff ff ff ff ff ff c3 fb c3 bb c5 ff;
4f10: bf bf a3 9d bd 9d a3 ff ff ff c3 bd bf bd c3 ff;
4f20: fd fd c5 b9 bd b9 c5 ff ff ff c3 bd 81 bf c3 ff;
4f30: f3 ed ef 83 ef ef ef ff ff ff c5 b9 b9 c5 fd c3;
4f40: bf bf a3 9d bd bd bd ff f7 ff e7 f7 f7 f7 e3 ff;
4f50: fb ff f3 fb fb fb bb c7 bf bf bb b7 af 97 bb ff;
4f60: e7 f7 f7 f7 f7 f7 e3 ff ff ff 89 b6 b6 b6 b6 ff;
4f70: ff ff a3 9d bd bd bd ff ff ff c3 bd bd bd c3 ff;
4f80: ff ff a3 9d 9d a3 bf bf ff ff c5 b9 b9 c5 fd fd;
4f90: ff ff a3 9d bf bf bf ff ff ff c1 bf c3 fd 83 ff;
4fa0: ef ef 83 ef ef ed f3 ff ff ff bd bd bd b9 c5 ff;
4fb0: ff ff bd bd bd db e7 ff ff ff be b6 b6 b6 c9 ff;
4fc0: ff ff bd db e7 db bd ff ff ff bd bd b9 c5 fd c3;
4fd0: ff ff 81 fb e7 df 81 ff f7 ef ef df ef ef f7 ff;
4fe0: e7 e7 e7 e7 e7 e7 e7 ff ef f7 f7 fb f7 f7 ef ff;
4ff0: ff ff ff cd b3 ff ff ff 00 00 01 3e 54 14 14 00;
END;

60
mif/combined_keymap.mif → software/mif/combined_keymap.mif
View File

@@ -1,4 +1,4 @@
DEPTH = 1536;
DEPTH = 2048;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
@@ -83,20 +83,52 @@ CONTENT BEGIN
04d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
04f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0500: ff 10 ff 04 02 00 01 ff ff 11 07 05 03 b0 b3 ff;
0510: ff 30 b2 ff ff 61 81 ff ff ff 72 63 41 67 82 ff;
0520: ff 43 70 44 45 84 83 ff ff 31 66 46 64 62 85 ff;
0530: ff 56 42 50 47 71 86 ff ff ff 55 52 65 87 90 ff;
0540: ff 77 53 51 57 80 91 ff ff 76 40 54 93 60 94 ff;
0550: ff 75 92 ff 95 73 ff ff b1 b2 32 96 ff a0 ff ff;
0560: ff ff ff ff ff ff 37 ff ff 21 74 24 27 ff ff ff;
0570: 20 15 22 25 26 12 ff ff ff 17 23 16 ff 13 ff ff;
0580: ff ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff;
0500: ff ff ff 93 95 97 96 ff ff ff ff ff 94 ff ff ff;
0510: ff 06 80 ff a6 27 57 ff ff ff 16 25 47 21 56 ff;
0520: ff 45 20 44 43 45 55 ff ff 64 22 42 24 26 53 ff;
0530: ff 32 46 40 41 17 52 ff ff ff 33 36 23 51 50 ff;
0540: ff 61 35 37 31 63 62 ff ff 60 70 34 0a 30 75 ff;
0550: ff ff ff ff 14 65 ff ff 04 ff 00 13 ff 67 ff ff;
0560: ff ff ff ff ff ff ff ff ff ff ff 72 ff ff ff ff;
0570: 77 76 74 ff 73 75 87 ff ff ff ff ff ff ff ff ff;
0580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05c0: ff ff ff ff ff ff ff ff ff ff 14 ff ff ff ff ff;
05d0: ff ff ff ff ff ff ff ff ff ff 32 ff ff ff ff ff;
05e0: ff ff ff ff ff ff ff ff ff ff ff 35 ff ff ff ef;
05f0: a2 a3 34 ff 36 33 ff ff ff ff ff ff ff ff ff ff;
05c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
05f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
0600: ff 10 ff 04 02 00 01 ff ff 11 07 05 03 b0 b3 ff;
0610: ff 30 b2 ff ff 61 81 ff ff ff 72 63 41 67 82 ff;
0620: ff 43 70 44 45 84 83 ff ff 31 66 46 64 62 85 ff;
0630: ff 56 42 50 47 71 86 ff ff ff 55 52 65 87 90 ff;
0640: ff 77 53 51 57 80 91 ff ff 76 40 54 93 60 94 ff;
0650: ff 75 92 ff 95 73 ff ff b1 b2 32 96 ff a0 ff ff;
0660: ff ff ff ff ff ff 37 ff ff 21 74 24 27 ff ff ff;
0670: 20 15 22 25 26 12 ff ff ff 17 23 16 ff 13 ff ff;
0680: ff ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff;
0690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
06a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
06b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
06c0: ff ff ff ff ff ff ff ff ff ff 14 ff ff ff ff ff;
06d0: ff ff ff ff ff ff ff ff ff ff 32 ff ff ff ff ff;
06e0: ff ff ff ff ff ff ff ff ff ff ff 35 ff ff ff ef;
06f0: a2 a3 34 ff 36 33 ff ff ff ff ff ff ff ff ff ff;
0700: ff 10 ff 04 02 00 01 ff ff 11 07 05 03 b0 b3 ff;
0710: ff 30 b2 ff ff 61 81 ff ff ff 72 63 41 67 82 ff;
0720: ff 43 70 44 45 84 83 ff ff 31 66 46 64 62 85 ff;
0730: ff 56 42 50 47 71 86 ff ff ff 55 52 65 87 90 ff;
0740: ff 77 53 51 57 80 91 ff ff 76 40 54 93 60 94 ff;
0750: ff 75 92 ff 95 73 ff ff b1 b2 32 96 ff a0 ff ff;
0760: ff ff ff ff ff ff 37 ff ff 21 74 24 27 ff ff ff;
0770: 20 15 22 25 26 12 ff ff ff 17 23 16 ff 13 ff ff;
0780: ff ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff;
0790: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
07a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
07b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff;
07c0: ff ff ff ff ff ff ff ff ff ff 14 ff ff ff ff ff;
07d0: ff ff ff ff ff ff ff ff ff ff 32 ff ff ff ff ff;
07e0: ff ff ff ff ff ff ff ff ff ff ff 35 ff ff ff ef;
07f0: a2 a3 34 ff 36 33 ff ff ff ff ff ff ff ff ff ff;
END;

328
mif/combined_mainmemory.mif → software/mif/combined_mainmemory.mif
View File

@@ -274,8 +274,8 @@ CONTENT BEGIN
10c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
10d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
10e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
10f0: 01 54 41 50 45 20 43 48 45 43 4b 20 56 31 2e 30;
1100: 0d 00 ee 06 00 c0 00 c0 00 00 00 00 00 00 00 00;
10f0: 01 53 48 41 52 50 4d 5a 20 54 45 53 54 20 56 31;
1100: 0d 00 13 0a 00 c0 00 c0 00 00 00 00 00 00 00 00;
1110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
1120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
1130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
@@ -3075,168 +3075,168 @@ bfc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
bfd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
bfe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
bff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
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c030: c0 cd 09 00 11 ca c5 cd 15 00 2a 04 11 cd ba 03;
c040: cd 09 00 11 e1 c5 cd 15 00 2a 06 11 cd ba 03 cd;
c050: 09 00 11 f8 c5 cd 15 00 2a 02 11 cd ba 03 cd 09;
c060: 00 11 b3 c5 cd 18 00 11 f1 10 cd 18 00 cd 09 00;
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c080: cd 09 00 11 26 c6 cd 15 00 2a 04 11 cd ba 03 cd;
c090: 09 00 11 3d c6 cd 15 00 2a 06 11 cd ba 03 cd 09;
c0a0: 00 11 54 c6 cd 15 00 2a 02 11 cd ba 03 cd 09 00;
c0b0: 11 0f c6 cd 18 00 11 f1 10 cd 18 00 cd 09 00 3e;
c0c0: 01 32 f0 10 cd 16 c4 da dc c0 cd 47 c4 da dc c0;
c0d0: cd 09 00 11 49 c5 cd 18 00 c3 95 00 fe 02 ca 95;
c0e0: 00 11 5c c5 cd 15 00 c3 95 00 fe 02 ca 95 00 11;
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c150: 02 e0 cd f9 c1 da f4 c1 cd 70 c3 1a e6 20 ca 52;
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c170: f4 c1 77 23 0b 78 b1 c2 6c c1 2a 97 11 cd 1c c2;
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c1a0: 03 cd 09 00 11 82 c6 cd 18 00 d1 eb cd ba 03 cd;
c1b0: 09 00 d1 e1 e1 c1 d1 cd 17 c3 f5 3a 9c 11 fe f0;
c1c0: 20 01 fb f1 c9 e5 d5 d5 11 99 c6 cd 18 00 cd ba;
c1d0: 03 cd 09 00 11 b0 c6 cd 18 00 d1 eb cd ba 03 cd;
c1e0: 09 00 d1 e1 16 01 15 28 07 62 cd b1 c3 c3 4c c1;
c1f0: 3e 01 18 02 3e 02 37 18 bb 3e f0 32 00 e0 00 0a;
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c220: 00 08 01 01 e0 11 02 e0 cd f9 c1 da 4c c2 cd 70;
c230: c3 1a e6 20 ca 41 c2 e5 2a 97 11 23 22 97 11 e1;
c240: 37 7d 17 6f 25 c2 28 c2 cd f9 c1 7d e1 d1 c1 c9;
c250: cd b1 c3 c5 d5 e5 c5 d5 11 73 c5 cd 15 00 cd 09;
c260: 00 d1 c1 21 28 28 7b fe cc ca 6f c2 21 14 14 22;
c270: 95 11 01 01 e0 11 02 e0 2a 95 11 cd f9 c1 da a4;
c280: c2 cd 70 c3 1a e6 20 ca 78 c2 25 c2 7b c2 cd f9;
c290: c1 da a4 c2 cd 70 c3 1a e6 20 c2 78 c2 2d c2 8e;
c2a0: c2 cd f9 c1 e1 d1 c1 c9 cd 09 00 cd ba 03 3e c4;
c2b0: cd dc 0d cd dc 0d cd dc 0d cd dc 0d cd 09 00 c3;
c2c0: 95 00 c5 d5 e5 c5 d5 11 7d c5 cd 15 00 cd 09 00;
c2d0: d1 c1 06 0a 3a 02 e0 e6 10 28 0a 06 a6 cd 79 c3;
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c310: 11 0d 20 f4 37 18 cc f5 c5 d5 c5 d5 11 8b c5 cd;
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c390: c3 01 f8 2a 11 14 14 cd d8 c3 0b 78 b1 20 fb cd;
c3a0: f1 c3 15 20 fa cd d8 c3 1d 20 fa cd f1 c3 d1 c1;
c3b0: c9 c5 d5 e5 11 a8 c5 cd 15 00 cd 09 00 01 01 e0;
c3c0: 11 02 e0 26 64 cd f9 c1 38 0b cd 70 c3 1a e6 20;
c3d0: 20 f1 25 20 f0 c3 a4 c2 f5 3e 03 32 03 e0 cd 62;
c3e0: c3 cd 62 c3 3e 02 32 03 e0 cd 62 c3 cd 62 c3 f1;
c3f0: c9 f5 3e 03 32 03 e0 cd 62 c3 cd 62 c3 cd 62 c3;
c400: cd 62 c3 3e 02 32 03 e0 cd 62 c3 cd 62 c3 cd 62;
c410: c3 cd 62 c3 f1 c9 f3 d5 c5 e5 16 d7 1e cc 21 f0;
c420: 10 01 80 00 cd 3e c3 cd c2 c2 38 18 7b fe cc 20;
c430: 0d cd 09 00 d5 11 40 c5 df 11 f1 10 df d1 cd 83;
c440: c3 cd 5c c4 c3 b4 c1 f3 d5 c5 e5 16 d7 1e 53 ed;
c450: 4b 02 11 2a 04 11 78 b1 28 4a 18 c8 d5 c5 e5 16;
c460: 02 3e f8 32 00 e0 7e cd 1a c5 3a 01 e0 e6 81 c2;
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c4a0: e5 c3 66 c4 e1 c1 d1 c9 2f 4e f3 d5 c5 e5 ed 4b;
c4b0: 02 11 2a 04 11 16 d2 1e 53 78 b1 ca b4 c1 cd 3e;
c4c0: c3 cd c2 c2 da f4 c1 cd 50 c2 da f4 c1 cd d3 c4;
c4d0: c3 b4 c1 d5 c5 e5 26 02 01 01 e0 11 02 e0 cd f9;
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c4f0: c5 e5 cd 1c c2 da f4 c1 be c2 f0 c1 23 0b 78 b1;
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c190: 15 00 2a 02 11 cd ba 03 cd 09 00 11 08 c7 cd 18;
c1a0: 00 11 f1 10 cd 18 00 cd 09 00 cd 74 c2 da 3b c2;
c1b0: 2a 06 11 7c fe 12 da 4d c0 e9 21 92 c8 11 f0 10;
c1c0: 01 80 00 ed b0 cd 06 00 11 1c c8 cd 15 00 cd 06;
c1d0: 00 cd 06 00 11 7b c7 cd 15 00 2a 04 11 cd ba 03;
c1e0: cd 09 00 11 92 c7 cd 15 00 2a 06 11 cd ba 03 cd;
c1f0: 09 00 11 a9 c7 cd 15 00 2a 02 11 cd ba 03 cd 09;
c200: 00 11 64 c7 cd 18 00 11 f1 10 cd 18 00 cd 09 00;
c210: 3e 01 32 f0 10 cd 67 c5 da 2d c2 cd 9b c5 da 2d;
c220: c2 cd 09 00 11 9e c6 cd 18 00 c3 4d c0 fe 02 ca;
c230: 4d c0 11 b1 c6 cd 15 00 c3 4d c0 fe 02 ca 4d c0;
c240: 11 a2 c6 cd 15 00 c3 4d c0 f3 d5 c5 e5 16 d2 1e;
c250: cc 01 80 00 21 f0 10 cd 13 c4 da 45 c3 cd a1 c3;
c260: da 45 c3 cd 98 c2 e1 c1 d1 f5 3a 9c 11 fe f0 20;
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c290: 11 fe f0 20 01 fb f1 c9 d5 c5 e5 26 02 01 01 e0;
c2a0: 11 02 e0 cd 4a c3 da 45 c3 cd c1 c4 1a e6 20 ca;
c2b0: a3 c2 54 21 00 00 22 97 11 e1 c1 c5 e5 cd 6d c3;
c2c0: da 45 c3 77 23 0b 78 b1 c2 bd c2 2a 97 11 cd 6d;
c2d0: c3 da 45 c3 57 cd 6d c3 da 45 c3 5f bd c2 16 c3;
c2e0: 7a bc c2 16 c3 af e5 d5 d5 11 c0 c7 cd 18 00 cd;
c2f0: ba 03 cd 09 00 11 d7 c7 cd 18 00 d1 eb cd ba 03;
c300: cd 09 00 d1 e1 e1 c1 d1 cd 68 c4 f5 3a 9c 11 fe;
c310: f0 20 01 fb f1 c9 e5 d5 d5 11 ee c7 cd 18 00 cd;
c320: ba 03 cd 09 00 11 05 c8 cd 18 00 d1 eb cd ba 03;
c330: cd 09 00 d1 e1 16 01 15 28 07 62 cd 02 c5 c3 9d;
c340: c2 3e 01 18 02 3e 02 37 18 bb 3e f0 32 00 e0 00;
c350: 0a e6 81 c2 58 c3 37 c9 1a e6 20 c2 50 c3 0a e6;
c360: 81 c2 66 c3 37 c9 1a e6 20 ca 5e c3 c9 c5 d5 e5;
c370: 21 00 08 01 01 e0 11 02 e0 cd 4a c3 da 9d c3 cd;
c380: c1 c4 1a e6 20 ca 92 c3 e5 2a 97 11 23 22 97 11;
c390: e1 37 7d 17 6f 25 c2 79 c3 cd 4a c3 7d e1 d1 c1;
c3a0: c9 cd 02 c5 c5 d5 e5 c5 d5 11 c8 c6 cd 15 00 cd;
c3b0: 09 00 d1 c1 21 28 28 7b fe cc ca c0 c3 21 14 14;
c3c0: 22 95 11 01 01 e0 11 02 e0 2a 95 11 cd 4a c3 da;
c3d0: f5 c3 cd c1 c4 1a e6 20 ca c9 c3 25 c2 cc c3 cd;
c3e0: 4a c3 da f5 c3 cd c1 c4 1a e6 20 c2 c9 c3 2d c2;
c3f0: df c3 cd 4a c3 e1 d1 c1 c9 cd 09 00 cd ba 03 3e;
c400: c4 cd dc 0d cd dc 0d cd dc 0d cd dc 0d cd 09 00;
c410: c3 4d c0 c5 d5 e5 c5 d5 11 d2 c6 cd 15 00 cd 09;
c420: 00 d1 c1 06 0a 3a 02 e0 e6 10 28 0a 06 a6 cd ca;
c430: c4 10 fb af 18 bf 3e 06 21 03 e0 77 3c 77 10 e5;
c440: cd 09 00 7a fe d7 28 05 11 81 c6 18 09 11 89 c6;
c450: cd 18 00 11 83 c6 cd 18 00 3a 02 e0 e6 10 20 cc;
c460: cd 11 0d 20 f4 37 18 cc f5 c5 d5 c5 d5 11 e0 c6;
c470: cd 15 00 cd 09 00 d1 c1 06 0a 3a 02 e0 e6 10 28;
c480: 0b 3e 06 32 03 e0 3c 32 03 e0 10 ee c3 e6 0e c5;
c490: d5 e5 11 00 00 78 b1 20 0b eb 22 97 11 22 99 11;
c4a0: e1 d1 c1 c9 7e c5 06 08 07 30 01 13 10 fa c1 23;
c4b0: 0b 18 e2 3e 0e 3d c2 b5 c4 c9 3e 0d 3d c2 bc c4;
c4c0: c9 ed 44 ed 44 3e 2a c3 bc c4 c5 06 23 cd c1 c4;
c4d0: 10 fb c1 c9 c5 d5 7b 01 f0 55 11 28 20 fe cc ca;
c4e0: e8 c4 01 f8 2a 11 14 14 cd 29 c5 0b 78 b1 20 fb;
c4f0: cd 42 c5 15 20 fa cd 29 c5 1d 20 fa cd 42 c5 d1;
c500: c1 c9 c5 d5 e5 11 fd c6 cd 15 00 cd 09 00 01 01;
c510: e0 11 02 e0 26 64 cd 4a c3 38 0b cd c1 c4 1a e6;
c520: 20 20 f1 25 20 f0 c3 f5 c3 f5 3e 03 32 03 e0 cd;
c530: b3 c4 cd b3 c4 3e 02 32 03 e0 cd b3 c4 cd b3 c4;
c540: f1 c9 f5 3e 03 32 03 e0 cd b3 c4 cd b3 c4 cd b3;
c550: c4 cd b3 c4 3e 02 32 03 e0 cd b3 c4 cd b3 c4 cd;
c560: b3 c4 cd b3 c4 f1 c9 f3 d5 c5 e5 16 d7 1e cc 21;
c570: f0 10 01 80 00 cd 8f c4 cd 13 c4 38 1b 7b fe cc;
c580: 20 10 cd 09 00 d5 11 94 c6 df 11 f1 10 df cd 09;
c590: 00 d1 cd d4 c4 cd b0 c5 c3 05 c3 f3 d5 c5 e5 16;
c5a0: d7 1e 53 ed 4b 02 11 2a 04 11 78 b1 28 4a 18 c5;
c5b0: d5 c5 e5 16 02 3e f8 32 00 e0 7e cd 6e c6 3a 01;
c5c0: e0 e6 81 c2 cb c5 3e 02 37 18 2d 23 0b 78 b1 c2;
c5d0: ba c5 2a 97 11 7c cd 6e c6 7d cd 6e c6 cd 42 c5;
c5e0: 15 c2 e8 c5 b7 c3 f8 c5 06 00 cd 29 c5 05 c2 ea;
c5f0: c5 e1 c1 c5 e5 c3 ba c5 e1 c1 d1 c9 2f 4e f3 d5;
c600: c5 e5 ed 4b 02 11 2a 04 11 16 d2 1e 53 78 b1 ca;
c610: 05 c3 cd 8f c4 cd 13 c4 da 45 c3 cd a1 c3 da 45;
c620: c3 cd 27 c6 c3 05 c3 d5 c5 e5 26 02 01 01 e0 11;
c630: 02 e0 cd 4a c3 da 45 c3 cd c1 c4 1a e6 20 ca 32;
c640: c6 54 e1 c1 c5 e5 cd 6d c3 da 45 c3 be c2 41 c3;
c650: 23 0b 78 b1 20 f0 2a 99 11 cd 6d c3 bc c2 41 c3;
c660: cd 6d c3 bd c2 41 c3 15 ca 14 c3 62 18 be c5 06;
c670: 08 cd 42 c5 07 dc 42 c5 d4 29 c5 05 c2 74 c6 c1;
c680: c9 7f 20 50 4c 41 59 0d 00 7f 20 52 45 43 4f 52;
c690: 44 2e 0d 00 57 52 49 54 49 4e 47 20 0d 00 4f 4b;
c6a0: 0d 00 43 48 45 43 4b 53 55 4d 20 45 52 52 4f 52;
c6b0: 0d 57 52 49 54 45 20 45 52 52 4f 52 0d 52 45 41;
c6c0: 44 20 54 41 50 45 0d 00 54 41 50 45 4d 41 52 4b;
c6d0: 0d 00 4d 4f 54 4f 52 20 54 4f 47 47 4c 45 0d 00;
c6e0: 4d 4f 54 4f 52 20 53 54 4f 50 0d 00 54 41 50 45;
c6f0: 20 4d 41 52 4b 20 53 54 41 52 54 0d 00 47 41 50;
c700: 20 43 48 45 43 4b 0d 00 4c 4f 41 44 20 46 49 4c;
c710: 45 20 20 20 20 20 20 20 20 20 20 3d 20 0d 00 4c;
c720: 4f 41 44 20 41 44 44 52 45 53 53 20 20 20 20 20;
c730: 20 20 3d 20 0d 00 45 58 45 43 20 41 44 44 52 45;
c740: 53 53 20 20 20 20 20 20 20 3d 20 0d 00 4c 4f 41;
c750: 44 20 53 49 5a 45 20 20 20 20 20 20 20 20 20 20;
c760: 3d 20 0d 00 53 41 56 45 20 46 49 4c 45 20 20 20;
c770: 20 20 20 20 20 20 20 3d 20 0d 00 53 41 56 45 20;
c780: 41 44 44 52 45 53 53 20 20 20 20 20 20 20 3d 20;
c790: 0d 00 53 41 56 45 20 45 58 45 43 20 41 44 44 52;
c7a0: 45 53 53 20 20 3d 20 0d 00 53 41 56 45 20 53 49;
c7b0: 5a 45 20 20 20 20 20 20 20 20 20 20 3d 20 0d 00;
c7c0: 20 20 4d 5a 20 43 48 45 43 4b 53 55 4d 20 28 4f;
c7d0: 4b 29 20 3d 20 0d 00 54 41 50 45 20 43 48 45 43;
c7e0: 4b 53 55 4d 20 28 4f 4b 29 20 3d 20 0d 00 20 20;
c7f0: 4d 5a 20 43 48 45 43 4b 53 55 4d 20 28 45 52 29;
c800: 20 3d 20 0d 00 54 41 50 45 20 43 48 45 43 4b 53;
c810: 55 4d 20 28 45 52 29 20 3d 20 0d 00 53 48 41 52;
c820: 50 4d 5a 20 54 45 53 54 45 52 20 28 43 29 20 50;
c830: 2e 20 53 4d 41 52 54 20 32 30 31 38 0d 00 52 3d;
c840: 4c 4f 41 44 2c 20 57 3d 53 41 56 45 2c 20 4d 3d;
c850: 4d 45 4d 2c 20 51 3d 51 55 49 54 0d 00 2c 20 43;
c860: 48 45 43 4b 3a 20 0d 20 4f 4b 2e 0d 11 52 41 4d;
c870: 20 54 45 53 54 20 43 4f 4d 50 4c 45 54 45 2e 0d;
c880: 20 42 49 54 3a 20 20 0d 20 42 41 4e 4b 3a 20 0d;
c890: 00 00 02 54 45 53 54 20 54 41 50 45 20 53 41 56;
c8a0: 45 0d 00 00 01 01 12 c9 12 c9 41 42 43 44 45 46;
c8b0: 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56;
c8c0: 57 58 59 5a 61 62 63 64 65 66 67 68 69 6a 6b 6c;
c8d0: 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 41 42;
c8e0: 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52;
c8f0: 53 54 55 56 57 58 59 5a 61 62 63 64 65 66 67 68;
c900: 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78;
c910: 79 7a 01 00 01 02 03 04 05 06 07 08 09 0a 0b 0c;
c920: 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c;
c930: 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c;
c940: 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c;
c950: 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c;
c960: 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c;
c970: 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c;
c980: 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c;
c990: 7d 7e 7f 80 81 82 83 84 85 86 87 88 89 8a 8b 8c;
c9a0: 8d 8e 8f 90 91 92 93 94 95 96 97 98 99 9a 9b 9c;
c9b0: 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac;
c9c0: ad ae af b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc;
c9d0: bd be bf c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc;
c9e0: cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc;
c9f0: dd de df e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec;
ca00: ed ee ef f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc;
ca10: fd fe ff 00 00 00 00 00 00 00 00 00 00 00 00 00;
ca20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
ca30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
ca40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

1922
mif/combined_mrom.mif → software/mif/combined_mrom.mif
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BIN
software/mzf/3-D MAZE.MZF Normal file
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software/mzf/MYMAZE.mzf Normal file
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0
mzf/hi-ramcheck.mzf → software/mzf/hi-ramcheck.mzf
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0
mzf/ramtest.mzf → software/mzf/ramtest.mzf
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software/mzf/sharpmz-test.mzf Normal file
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software/mzf/tapecheck.mzf Normal file
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software/roms/IPL.rom Normal file
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0
roms/MZ700_cgrom.rom → software/roms/MZ700_cgrom.rom
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0
roms/MZ80B.rom → software/roms/MZ80B.rom
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0
roms/MZ80K_cgrom.rom → software/roms/MZ80K_cgrom.rom
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BIN
software/roms/MZFONT.rom Normal file
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0
roms/NEWMON.rom → software/roms/NEWMON.rom
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0
roms/SP1002.rom → software/roms/SP1002.rom
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BIN
roms/combined_cgrom.rom → software/roms/combined_cgrom.rom
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BIN
roms/combined_keymap.rom → software/roms/combined_keymap.rom
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BIN
roms/combined_mainmemory.rom → software/roms/combined_mainmemory.rom
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BIN
roms/combined_mrom.rom → software/roms/combined_mrom.rom
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0
roms/fdcrom.rom → software/roms/fdcrom.rom
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0
roms/key_1200.rom → software/roms/key_1200.rom
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0
roms/key_700.rom → software/roms/key_700.rom
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0
roms/key_80a.rom → software/roms/key_80a.rom
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0
roms/key_80b.rom → software/roms/key_80b.rom
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0
roms/key_80c.rom → software/roms/key_80c.rom
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0
roms/key_80k.rom → software/roms/key_80k.rom
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0
roms/monitor_1Z-013A.rom → software/roms/monitor_1Z-013A.rom
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0
roms/monitor_80c_1Z-013A.rom → software/roms/monitor_80c_1Z-013A.rom
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0
roms/monitor_80c_SA1510.rom → software/roms/monitor_80c_SA1510.rom
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0
roms/monitor_SA1510.rom → software/roms/monitor_SA1510.rom
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0
roms/monitor_mz-1r12.rom → software/roms/monitor_mz-1r12.rom
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Some files were not shown because too many files have changed in this diff Show More