51 lines
1.7 KiB
VHDL
51 lines
1.7 KiB
VHDL
--Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
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--use of Altera Corporation's design tools, logic functions and other
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--software and tools, and its AMPP partner logic functions, and any
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--output files any of the foregoing (including device programming or
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--simulation files), and any associated documentation or information are
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--expressly subject to the terms and conditions of the Altera Program
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--License Subscription Agreement or other applicable license agreement,
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--including, without limitation, that your use is for the sole purpose
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--of programming logic devices manufactured by Altera and sold by Altera
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--or its authorized distributors. Please refer to the applicable
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--agreement for further details.
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-- turn off superfluous VHDL processor warnings
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-- altera message_level Level1
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-- altera message_off 10034 10035 10036 10037 10230 10240 10030
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library altera;
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use altera.altera_europa_support_lib.all;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity sysid is
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port (
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-- inputs:
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signal address : IN STD_LOGIC;
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signal clock : IN STD_LOGIC;
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signal reset_n : IN STD_LOGIC;
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-- outputs:
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signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
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);
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end entity sysid;
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architecture europa of sysid is
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begin
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--control_slave, which is an e_avalon_slave
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readdata <= A_WE_StdLogicVector((std_logic'(address) = '1'), std_logic_vector'("01011011000101101111000000111011"), std_logic_vector'("00000000000000000000000000000000"));
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end europa;
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