120 lines
4.3 KiB
VHDL
120 lines
4.3 KiB
VHDL
-- pll.vhd
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-- Generated using ACDS version 17.1 593
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity pll is
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port (
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clk_clk : in std_logic := '0'; -- clk.clk
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pll_0_outclk1_clk : out std_logic; -- pll_0_outclk1.clk
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pll_0_outclk2_clk : out std_logic; -- pll_0_outclk2.clk
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pll_0_outclk3_clk : out std_logic; -- pll_0_outclk3.clk
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pll_0_outclk4_clk : out std_logic; -- pll_0_outclk4.clk
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pll_0_outclk5_clk : out std_logic; -- pll_0_outclk5.clk
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pll_0_outclk6_clk : out std_logic; -- pll_0_outclk6.clk
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pll_0_refclk_clk : in std_logic := '0'; -- pll_0_refclk.clk
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pll_0_reset_reset : in std_logic := '0'; -- pll_0_reset.reset
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pll_1_outclk0_clk : out std_logic; -- pll_1_outclk0.clk
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pll_1_outclk1_clk : out std_logic; -- pll_1_outclk1.clk
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pll_1_outclk2_clk : out std_logic; -- pll_1_outclk2.clk
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pll_1_outclk3_clk : out std_logic; -- pll_1_outclk3.clk
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pll_1_outclk4_clk : out std_logic; -- pll_1_outclk4.clk
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pll_1_reset_reset : in std_logic := '0'; -- pll_1_reset.reset
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pll_2_outclk0_clk : out std_logic; -- pll_2_outclk0.clk
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pll_2_outclk1_clk : out std_logic; -- pll_2_outclk1.clk
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pll_2_outclk2_clk : out std_logic; -- pll_2_outclk2.clk
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pll_2_outclk3_clk : out std_logic; -- pll_2_outclk3.clk
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pll_2_reset_reset : in std_logic := '0'; -- pll_2_reset.reset
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reset_reset_n : in std_logic := '0' -- reset.reset_n
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);
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end entity pll;
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architecture rtl of pll is
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component pll_pll_0 is
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port (
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refclk : in std_logic := 'X'; -- clk
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rst : in std_logic := 'X'; -- reset
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outclk_0 : out std_logic; -- clk
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outclk_1 : out std_logic; -- clk
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outclk_2 : out std_logic; -- clk
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outclk_3 : out std_logic; -- clk
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outclk_4 : out std_logic; -- clk
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outclk_5 : out std_logic; -- clk
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outclk_6 : out std_logic; -- clk
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outclk_7 : out std_logic; -- clk
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locked : out std_logic -- export
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);
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end component pll_pll_0;
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component pll_pll_1 is
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port (
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refclk : in std_logic := 'X'; -- clk
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rst : in std_logic := 'X'; -- reset
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outclk_0 : out std_logic; -- clk
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outclk_1 : out std_logic; -- clk
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outclk_2 : out std_logic; -- clk
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outclk_3 : out std_logic; -- clk
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outclk_4 : out std_logic; -- clk
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locked : out std_logic -- export
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);
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end component pll_pll_1;
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component pll_pll_2 is
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port (
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refclk : in std_logic := 'X'; -- clk
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rst : in std_logic := 'X'; -- reset
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outclk_0 : out std_logic; -- clk
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outclk_1 : out std_logic; -- clk
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outclk_2 : out std_logic; -- clk
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outclk_3 : out std_logic; -- clk
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locked : out std_logic -- export
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);
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end component pll_pll_2;
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signal pll_0_outclk0_clk : std_logic; -- pll_0:outclk_0 -> [pll_1:refclk, pll_2:refclk]
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begin
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pll_0 : component pll_pll_0
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port map (
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refclk => pll_0_refclk_clk, -- refclk.clk
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rst => pll_0_reset_reset, -- reset.reset
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outclk_0 => pll_0_outclk0_clk, -- outclk0.clk
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outclk_1 => pll_0_outclk1_clk, -- outclk1.clk
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outclk_2 => pll_0_outclk2_clk, -- outclk2.clk
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outclk_3 => pll_0_outclk3_clk, -- outclk3.clk
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outclk_4 => pll_0_outclk4_clk, -- outclk4.clk
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outclk_5 => pll_0_outclk5_clk, -- outclk5.clk
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outclk_6 => pll_0_outclk6_clk, -- outclk6.clk
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outclk_7 => open, -- outclk7.clk
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locked => open -- (terminated)
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);
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pll_1 : component pll_pll_1
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port map (
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refclk => pll_0_outclk0_clk, -- refclk.clk
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rst => pll_1_reset_reset, -- reset.reset
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outclk_0 => pll_1_outclk0_clk, -- outclk0.clk
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outclk_1 => pll_1_outclk1_clk, -- outclk1.clk
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outclk_2 => pll_1_outclk2_clk, -- outclk2.clk
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outclk_3 => pll_1_outclk3_clk, -- outclk3.clk
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outclk_4 => pll_1_outclk4_clk, -- outclk4.clk
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locked => open -- (terminated)
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);
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pll_2 : component pll_pll_2
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port map (
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refclk => pll_0_outclk0_clk, -- refclk.clk
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rst => pll_2_reset_reset, -- reset.reset
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outclk_0 => pll_2_outclk0_clk, -- outclk0.clk
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outclk_1 => pll_2_outclk1_clk, -- outclk1.clk
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outclk_2 => pll_2_outclk2_clk, -- outclk2.clk
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outclk_3 => pll_2_outclk3_clk, -- outclk3.clk
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locked => open -- (terminated)
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);
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end architecture rtl; -- of pll
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