55 lines
2.9 KiB
Plaintext
55 lines
2.9 KiB
Plaintext
Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --block-symbol-file --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll --family="Cyclone V" --part=5CSEBA6U23I7
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Progress: Loading common/pll.qsys
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Progress: Reading input file
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Progress: Adding clk_0 [clock_source 17.1]
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Progress: Parameterizing module clk_0
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Progress: Adding pll_0 [altera_pll 17.1]
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Progress: Parameterizing module pll_0
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Progress: Adding pll_1 [altera_pll 17.1]
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Progress: Parameterizing module pll_1
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Progress: Adding pll_2 [altera_pll 17.1]
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Progress: Parameterizing module pll_2
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
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Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
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Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
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Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
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Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
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Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
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Info: qsys-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate /srv/dvlp/Projects/dev/github/em/common/pll.qsys --synthesis=VHDL --output-directory=/srv/dvlp/Projects/dev/github/em/common/pll/synthesis --family="Cyclone V" --part=5CSEBA6U23I7
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Progress: Loading common/pll.qsys
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Progress: Reading input file
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Progress: Adding clk_0 [clock_source 17.1]
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Progress: Parameterizing module clk_0
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Progress: Adding pll_0 [altera_pll 17.1]
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Progress: Parameterizing module pll_0
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Progress: Adding pll_1 [altera_pll 17.1]
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Progress: Parameterizing module pll_1
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Progress: Adding pll_2 [altera_pll 17.1]
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Progress: Parameterizing module pll_2
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: pll.pll_0: The legal reference clock frequency is 50.0 MHz..700.0 MHz
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Warning: pll.pll_0: Able to implement PLL - Actual settings differ from Requested settings
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Info: pll.pll_1: The legal reference clock frequency is 5.0 MHz..700.0 MHz
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Warning: pll.pll_1: Able to implement PLL - Actual settings differ from Requested settings
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Info: pll.pll_2: The legal reference clock frequency is 50.0 MHz..700.0 MHz
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Warning: pll.pll_2: Able to implement PLL - Actual settings differ from Requested settings
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Info: pll: Generating pll "pll" for QUARTUS_SYNTH
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Info: pll_0: "pll" instantiated altera_pll "pll_0"
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Info: pll_1: "pll" instantiated altera_pll "pll_1"
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Info: pll_2: "pll" instantiated altera_pll "pll_2"
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Info: pll: Done "pll" with 4 modules, 7 files
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Info: qsys-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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