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Philip Smart
2019-10-29 13:07:32 +00:00
parent 7c8e1c3c92
commit 7a0a4b2aae
28 changed files with 0 additions and 8575 deletions
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133
mz80b/old/ScanConv.vhd
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--
-- ScanConv.vhd
--
-- Up Scan Converter (15.6kHz->VGA)
-- for MZ-80B on FPGA
--
-- Nibbles Lab. 2013
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ScanConv is
Port (
CK16M : in STD_LOGIC; -- MZ Dot Clock
CK25M : in STD_LOGIC; -- VGA Dot Clock
RI : in STD_LOGIC; -- Red Input
GI : in STD_LOGIC; -- Green Input
BI : in STD_LOGIC; -- Blue Input
HSI : in STD_LOGIC; -- H-Sync Input(MZ,15.6kHz)
RO : out STD_LOGIC; -- Red Output
GO : out STD_LOGIC; -- Green Output
BO : out STD_LOGIC; -- Blue Output
HSO : out STD_LOGIC); -- H-Sync Output(VGA, 31kHz)
end ScanConv;
architecture RTL of ScanConv is
--
-- Signals
--
signal CTR12M5 : std_logic_vector(10 downto 0); --
--signal CLK12M5 : std_logic; -- Divider for VGA Sync Signal
signal TS : std_logic_vector(9 downto 0); -- Half of Horizontal
signal OCTR : std_logic_vector(9 downto 0); -- Buffer Output Pointer
signal ICTR : std_logic_vector(9 downto 0); -- Buffer Input Pointer
signal Hi : std_logic_vector(5 downto 0); -- Shift Register for H-Sync Detect(VGA)
signal Si : std_logic_vector(5 downto 0); -- Shift Register for H-Sync Detect(15.6kHz)
signal DO : std_logic_vector(2 downto 0);
--
-- Components
--
component linebuf
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
SBUF : linebuf PORT MAP (
data => RI&GI&BI, -- Input RGB
rdaddress => OCTR, -- Buffer Output Counter
rdclock => CK25M, -- Dot Clock(VGA)
wraddress => ICTR, -- Buffer Input Counter
wrclock => CK16M, -- Dot Clock(15.6kHz)
wren => '1', -- Write only
q => DO -- Output RGB
);
--
-- Buffer Input
--
process( CK16M ) begin
if CK16M'event and CK16M='1' then
-- Filtering HSI
Si<=Si(4 downto 0)&HSI;
-- Counter start
if Si="111000" then
ICTR<="1110000100"; -- X"3B8";
else
ICTR<=ICTR+'1';
end if;
end if;
end process;
--
-- Buffer and Signal Output
--
process( CK25M ) begin
if CK25M'event and CK25M='1' then
-- Filtering HSI
Hi<=Hi(4 downto 0)&HSI;
-- Detect HSYNC
if Hi="111000" then
CTR12M5<=(others=>'0');
TS<=CTR12M5(10 downto 1); -- Half of Horizontal
OCTR<=(others=>'0');
elsif OCTR=TS then
OCTR<=(others=>'0');
CTR12M5<=CTR12M5+'1';
else
OCTR<=OCTR+'1';
CTR12M5<=CTR12M5+'1';
end if;
-- Horizontal Sync genarate
if OCTR=0 then
HSO<='0';
elsif OCTR=96 then
HSO<='1';
end if;
end if;
end process;
--
-- Output
--
RO<=DO(2);
GO<=DO(1);
BO<=DO(0);
end RTL;

1094
mz80b/old/T80/T80.vhd
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194
mz80b/old/T80/T8080se.vhd
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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

371
mz80b/old/T80/T80_ALU.vhd
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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

2029
mz80b/old/T80/T80_MCode.vhd
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220
mz80b/old/T80/T80_Pack.vhd
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@@ -1,220 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

114
mz80b/old/T80/T80_Reg.vhd
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@@ -1,114 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

176
mz80b/old/T80/T80_RegX.vhd
View File

@@ -1,176 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;

262
mz80b/old/T80/T80a.vhd
View File

@@ -1,262 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

192
mz80b/old/T80/T80se.vhd
View File

@@ -1,192 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

179
mz80b/old/T80/T80sed.vhd
View File

@@ -1,179 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

5
mz80b/old/cgrom.qip
View File

@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cgrom.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cgrom_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cgrom.cmp"]

198
mz80b/old/cgrom.vhd
View File

@@ -1,198 +0,0 @@
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: cgrom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY cgrom IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END cgrom;
ARCHITECTURE SYN OF cgrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 2048,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 11,
widthad_b => 11,
width_a => 8,
width_b => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "font.hex"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
-- Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

5
mz80b/old/dpram1kr.qip
View File

@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "11.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dpram1kr.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram1kr_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram1kr.cmp"]

234
mz80b/old/dpram1kr.vhd
View File

@@ -1,234 +0,0 @@
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram1kr.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram1kr IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END dpram1kr;
ARCHITECTURE SYN OF dpram1kr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_b : STRING;
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 8,
width_a => 8,
width_b => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./logic/kmap_80c.hex"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram1kr_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

5
mz80b/old/dpram2k.qip
View File

@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "12.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dpram2k.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram2k_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram2k.cmp"]

270
mz80b/old/dpram2k.vhd
View File

@@ -1,270 +0,0 @@
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram2k.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram2k IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END dpram2k;
ARCHITECTURE SYN OF dpram2k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock1 : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 2048,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
widthad_b => 11,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clock0 => clock_a,
wren_a => wren_a,
address_b => address_b,
clock1 => clock_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "vramtest0.hex"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram2k_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

203
mz80b/old/keymatrix.vhd
View File

@@ -1,203 +0,0 @@
--
-- keymatrix.vhd
--
-- Convert from PS/2 key-matrix to MZ-80B/2000 key-matrix module
-- for MZ-80B on FPGA
--
-- Nibbles Lab. 2005-2014
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keymatrix is
Port (
-- i8255/PIO
ZRST_x : in std_logic;
STROBE : in std_logic_vector(3 downto 0);
STALL : in std_logic;
KDATA : out std_logic_vector(7 downto 0);
-- PS/2 Keyboard Data
KCLK : in std_logic; -- Key controller base clock
KBEN : in std_logic; -- PS/2 Keyboard Data Valid
KBDT : in std_logic_vector(7 downto 0); -- PS/2 Keyboard Data
-- for Debug
LDDAT : out std_logic_vector(7 downto 0);
-- Avalon Bus
RRST_x : in std_logic; -- NiosII Reset
RCLK : in std_logic; -- NiosII Clock
RADR : in std_logic_vector(15 downto 0); -- NiosII Address Bus
RCS_x : in std_logic; -- NiosII Read Signal
RWE_x : in std_logic; -- NiosII Write Signal
RDI : in std_logic_vector(7 downto 0); -- NiosII Data Bus(in)
RDO : out std_logic_vector(7 downto 0) -- NiosII Data Bus(out)
);
end keymatrix;
architecture Behavioral of keymatrix is
--
-- prefix flag
--
signal FLGF0 : std_logic;
signal FLGE0 : std_logic;
--
-- MZ-series matrix registers
--
signal SCAN00 : std_logic_vector(7 downto 0);
signal SCAN01 : std_logic_vector(7 downto 0);
signal SCAN02 : std_logic_vector(7 downto 0);
signal SCAN03 : std_logic_vector(7 downto 0);
signal SCAN04 : std_logic_vector(7 downto 0);
signal SCAN05 : std_logic_vector(7 downto 0);
signal SCAN06 : std_logic_vector(7 downto 0);
signal SCAN07 : std_logic_vector(7 downto 0);
signal SCAN08 : std_logic_vector(7 downto 0);
signal SCAN09 : std_logic_vector(7 downto 0);
signal SCAN10 : std_logic_vector(7 downto 0);
signal SCAN11 : std_logic_vector(7 downto 0);
signal SCAN12 : std_logic_vector(7 downto 0);
signal SCAN13 : std_logic_vector(7 downto 0);
signal SCAN14 : std_logic_vector(7 downto 0);
signal SCANLL : std_logic_vector(7 downto 0);
--
-- Key code exchange table
--
signal MTEN : std_logic_vector(3 downto 0);
signal MTDT : std_logic_vector(7 downto 0);
signal F_KBDT : std_logic_vector(7 downto 0);
--
-- Backdoor Access
--
signal RWEN : std_logic;
signal RCSK_x : std_logic;
--
-- Components
--
component dpram1kr
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
begin
--
-- Instantiation
--
MAP0 : dpram1kr PORT MAP (
data => RDI,
rdaddress => F_KBDT,
rdclock => KCLK,
wraddress => RADR(7 downto 0),
wrclock => RCLK,
wren => RWEN,
q => MTDT
);
--
-- Convert
--
process( ZRST_x, KCLK ) begin
if ZRST_x='0' then
SCAN00<=(others=>'0');
SCAN01<=(others=>'0');
SCAN02<=(others=>'0');
SCAN03<=(others=>'0');
SCAN04<=(others=>'0');
SCAN05<=(others=>'0');
SCAN06<=(others=>'0');
SCAN07<=(others=>'0');
SCAN08<=(others=>'0');
SCAN09<=(others=>'0');
SCAN10<=(others=>'0');
SCAN11<=(others=>'0');
SCAN12<=(others=>'0');
SCAN13<=(others=>'0');
SCAN14<=(others=>'0');
FLGF0<='0';
FLGE0<='0';
MTEN<=(others=>'0');
F_KBDT<=(others=>'1');
elsif KCLK'event and KCLK='1' then
MTEN<=MTEN(2 downto 0)&KBEN;
if KBEN='1' then
case KBDT is
when X"AA" => F_KBDT<=X"EF";
when X"F0" => FLGF0<='1'; F_KBDT<=X"EF";
when X"E0" => FLGE0<='1'; F_KBDT<=X"EF";
when others => F_KBDT(6 downto 0)<=KBDT(6 downto 0); F_KBDT(7)<=FLGE0 or KBDT(7); FLGE0<='0';
end case;
end if;
if MTEN(3)='1' then
case MTDT(7 downto 4) is
when "0000" => SCAN00(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0001" => SCAN01(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0010" => SCAN02(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0011" => SCAN03(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0100" => SCAN04(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0101" => SCAN05(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0110" => SCAN06(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "0111" => SCAN07(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1000" => SCAN08(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1001" => SCAN09(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1010" => SCAN10(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1011" => SCAN11(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1100" => SCAN12(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1101" => SCAN13(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
when "1110" => SCAN14(conv_integer(MTDT(2 downto 0)))<=not FLGF0;
when others => SCAN14(conv_integer(MTDT(2 downto 0)))<=not FLGF0; FLGF0<='0';
end case;
end if;
end if;
end process;
STROBE_L : for I in 0 to 7 generate
SCANLL(I)<=SCAN00(I) or SCAN01(I) or SCAN02(I) or SCAN03(I) or SCAN04(I)
or SCAN05(I) or SCAN06(I) or SCAN07(I) or SCAN08(I) or SCAN09(I)
or SCAN10(I) or SCAN11(I) or SCAN12(I) or SCAN13(I) or SCAN14(I);
end generate STROBE_L;
--
-- response from key access
--
KDATA<=(not SCANLL) when STALL='0' else
(not SCAN00) when STROBE="0000" else
(not SCAN01) when STROBE="0001" else
(not SCAN02) when STROBE="0010" else
(not SCAN03) when STROBE="0011" else
(not SCAN04) when STROBE="0100" else
(not SCAN05) when STROBE="0101" else
(not SCAN06) when STROBE="0110" else
(not SCAN07) when STROBE="0111" else
(not SCAN08) when STROBE="1000" else
(not SCAN09) when STROBE="1001" else
(not SCAN10) when STROBE="1010" else
(not SCAN11) when STROBE="1011" else
(not SCAN12) when STROBE="1100" else
(not SCAN13) when STROBE="1101" else (others=>'1');
--
-- NiosII access
--
RCSK_x<='0' when RADR(15 downto 8)="11000000" else '1';
RWEN<=not(RWE_x or RCSK_x);
RDO<=(others=>'0');
end Behavioral;

5
mz80b/old/linebuf.qip
View File

@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "12.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "linebuf.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf.cmp"]

232
mz80b/old/linebuf.vhd
View File

@@ -1,232 +0,0 @@
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: linebuf.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY linebuf IS
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END linebuf;
ARCHITECTURE SYN OF linebuf IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_b : STRING;
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(2 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 10,
widthad_b => 10,
width_a => 3,
width_b => 3,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "3072"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "buftest.hex"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL "data[2..0]"
-- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 3 0 data 0 0 3 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 3 0 @q_b 0 0 3 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

544
mz80b/old/mz80b.vhd
View File

@@ -1,544 +0,0 @@
--
-- mz80b.vhd
--
-- SHARP MZ-80B/2000 compatible logic, top module
-- for Altera DE0
--
-- Nibbles Lab. 2013-2014
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mz80b is
port(
-------------------- Clock Input ----------------------
CLOCK_50 : in std_logic; -- 50 MHz
CLOCK_50_2 : in std_logic; -- 50 MHz
-------------------- Push Button ----------------------------
BUTTON : in std_logic_vector(2 downto 0); -- Pushbutton[2:0]
-------------------- DPDT Switch ----------------------------
SW : in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
-------------------- 7-SEG Dispaly ----------------------------
HEX0_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 0
HEX0_DP : out std_logic; -- Seven Segment Digit DP 0
HEX1_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 1
HEX1_DP : out std_logic; -- Seven Segment Digit DP 1
HEX2_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 2
HEX2_DP : out std_logic; -- Seven Segment Digit DP 2
HEX3_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 3
HEX3_DP : out std_logic; -- Seven Segment Digit DP 3
-------------------- LED ----------------------------
LEDG : out std_logic_vector(9 downto 0); -- LED Green[9:0]
-------------------- UART ----------------------------
UART_TXD : out std_logic; -- UART Transmitter
UART_RXD : in std_logic; -- UART Receiver
UART_CTS : in std_logic; -- UART Clear To Send
UART_RTS : out std_logic; -- UART Request To Send
-------------------- SDRAM Interface ----------------------------
DRAM_DQ : inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits
DRAM_ADDR : out std_logic_vector(12 downto 0); -- SDRAM Address bus 13 Bits
DRAM_LDQM : out std_logic; -- SDRAM Low-byte Data Mask
DRAM_UDQM : out std_logic; -- SDRAM High-byte Data Mask
DRAM_WE_N : out std_logic; -- SDRAM Write Enable
DRAM_CAS_N : out std_logic; -- SDRAM Column Address Strobe
DRAM_RAS_N : out std_logic; -- SDRAM Row Address Strobe
DRAM_CS_N : out std_logic; -- SDRAM Chip Select
DRAM_BA_0 : out std_logic; -- SDRAM Bank Address 0
DRAM_BA_1 : out std_logic; -- SDRAM Bank Address 1
DRAM_CLK : out std_logic; -- SDRAM Clock
DRAM_CKE : out std_logic; -- SDRAM Clock Enable
-------------------- Flash Interface ----------------------------
FL_DQ : inout std_logic_vector(15 downto 0); -- FLASH Data bus 16 Bits
-- FL_DQ15_AM1 : out std_logic; -- FLASH Data bus Bit 15 or Address A-1
FL_ADDR : out std_logic_vector(21 downto 0); -- FLASH Address bus 22 Bits
FL_WE_N : out std_logic; -- FLASH Write Enable
FL_RST_N : out std_logic; -- FLASH Reset
FL_OE_N : out std_logic; -- FLASH Output Enable
FL_CE_N : out std_logic; -- FLASH Chip Enable
FL_WP_N : out std_logic; -- FLASH Hardware Write Protect
FL_BYTE_N : out std_logic; -- FLASH Selects 8/16-bit mode
FL_RY : out std_logic; -- FLASH Ready/Busy
-------------------- LCD Module 16X2 ----------------------------
LCD_BLON : out std_logic; -- LCD Back Light ON/OFF
LCD_RW : out std_logic; -- LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN : out std_logic; -- LCD Enable
LCD_RS : out std_logic; -- LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA : out std_logic_vector(7 downto 0); -- LCD Data bus 8 bits
-------------------- SD_Card Interface ----------------------------
SD_DAT0 : inout std_logic; -- SD Card Data 0 (DO)
SD_DAT3 : inout std_logic; -- SD Card Data 3 (CS)
SD_CMD : out std_logic; -- SD Card Command Signal (DI)
SD_CLK : out std_logic; -- SD Card Clock (SCLK)
SD_WP_N : in std_logic; -- SD Card Write Protect
-------------------- PS2 ----------------------------
PS2_KBDAT : in std_logic; -- PS2 Keyboard Data
PS2_KBCLK : in std_logic; -- PS2 Keyboard Clock
PS2_MSDAT : in std_logic; -- PS2 Mouse Data
PS2_MSCLK : in std_logic; -- PS2 Mouse Clock
-------------------- VGA ----------------------------
VGA_HS : out std_logic; -- VGA H_SYNC
VGA_VS : out std_logic; -- VGA V_SYNC
VGA_R : out std_logic_vector(3 downto 0); -- VGA Red[3:0]
VGA_G : out std_logic_vector(3 downto 0); -- VGA Green[3:0]
VGA_B : out std_logic_vector(3 downto 0); -- VGA Blue[3:0]
-------------------- GPIO ------------------------------
GPIO0_CLKIN : in std_logic_vector(1 downto 0); -- GPIO Connection 0 Clock In Bus
GPIO0_CLKOUT: out std_logic_vector(1 downto 0); -- GPIO Connection 0 Clock Out Bus
GPIO0_D : out std_logic_vector(31 downto 0); -- GPIO Connection 0 Data Bus
GPIO1_CLKIN : in std_logic_vector(1 downto 0); -- GPIO Connection 1 Clock In Bus
GPIO1_CLKOUT: out std_logic_vector(1 downto 0); -- GPIO Connection 1 Clock Out Bus
GPIO1_D : inout std_logic_vector(31 downto 0) -- GPIO Connection 1 Data Bus
);
end mz80b;
architecture rtl of mz80b is
--
-- Z80
--
signal ZADR : std_logic_vector(22 downto 0);
signal ZDI : std_logic_vector(7 downto 0);
signal ZDO : std_logic_vector(7 downto 0);
signal ZCS_x : std_logic;
signal ZWR_x : std_logic;
signal ZPG_x : std_logic;
--
-- NiosII
--
signal RRST_x : std_logic; -- NiosII Reset
signal RCLK : std_logic; -- NiosII Clock
signal RADR : std_logic_vector(15 downto 0); -- NiosII Address Bus
signal RCS_x : std_logic; -- NiosII Read Signal
signal RWE_x : std_logic; -- NiosII Write Signal
signal RDI : std_logic_vector(7 downto 0); -- NiosII Data Bus(in)
signal RDO : std_logic_vector(7 downto 0); -- NiosII Data Bus(out)
signal INTL : std_logic; -- Interrupt Line
signal MADR : std_logic_vector(20 downto 0); -- Address
signal MDI : std_logic_vector(31 downto 0); -- Data Input(32bit)
signal MDO : std_logic_vector(31 downto 0); -- Data Output(32bit)
signal MCS_x : std_logic; -- Chip Select
signal MWE_x : std_logic; -- Write Enable
signal MBEN_x : std_logic_vector(3 downto 0); -- Byte Enable
signal MWRQ_x : std_logic; -- CPU Wait
--
-- Clock, Reset
--
signal PCLK : std_logic;
signal URST : std_logic;
signal MRST : std_logic;
signal ARST : std_logic;
--
-- FD Buffer
--
signal BCS_x : std_logic; -- RAM Request
signal BADR : std_logic_vector(22 downto 0); -- RAM Address
signal BWR_x : std_logic; -- RAM Write Signal
signal BDI : std_logic_vector(7 downto 0); -- Data Bus Input from RAM
signal BDO : std_logic_vector(7 downto 0); -- Data Bus Output to RAM
--
-- GRAM
--
signal GADR : std_logic_vector(20 downto 0);
signal GCS_x : std_logic;
signal GWR_x : std_logic;
signal GBE_x : std_logic_vector(3 downto 0);
signal GDI : std_logic_vector(31 downto 0);
signal GDO : std_logic_vector(31 downto 0);
--
-- SDRAM
--
signal SDRAMDO : std_logic_vector(15 downto 0);
signal SDRAMDOE : std_logic;
--
-- MMC/SD CARD
--
signal SD_CS : std_logic;
signal SD_DEN : std_logic_vector(1 downto 0);
signal SD_DO : std_logic;
--
-- Flash Memory
--
signal FL_ADDR0 : std_logic_vector(21 downto 0);
signal FL_WE_Ni : std_logic_vector(0 downto 0);
signal FL_OE_Ni : std_logic_vector(0 downto 0);
signal FL_CE_Ni : std_logic_vector(0 downto 0);
--
-- Misc
--
signal T_LEDG : std_logic_vector(9 downto 0);
--signal ZLEDG : std_logic_vector(9 downto 0);
signal CNT1 : std_logic_vector(24 downto 0);
signal CNT2 : std_logic_vector(24 downto 0);
--
-- Components
--
component mz80b_core
port(
-- Z80 Memory Bus
ZADR : out std_logic_vector(22 downto 0);
ZDI : in std_logic_vector(7 downto 0);
ZDO : out std_logic_vector(7 downto 0);
ZCS_x : out std_logic;
ZWR_x : out std_logic;
ZPG_x : out std_logic;
-- NiosII Access
RRST_x : in std_logic; -- NiosII Reset
RCLK : in std_logic; -- NiosII Clock
RADR : in std_logic_vector(15 downto 0); -- NiosII Address Bus
RCS_x : in std_logic; -- NiosII Read Signal
RWE_x : in std_logic; -- NiosII Write Signal
RDI : in std_logic_vector(7 downto 0); -- NiosII Data Bus(in)
RDO : out std_logic_vector(7 downto 0); -- NiosII Data Bus(out)
INTL : out std_logic; -- Interrupt Line
-- Graphic VRAM Access
GCS_x : out std_logic; -- GRAM Request
GADR : out std_logic_vector(20 downto 0); -- GRAM Address
GWR_x : out std_logic; -- GRAM Write Signal
GBE_x : out std_logic_vector(3 downto 0); -- GRAM Byte Enable
GDI : in std_logic_vector(31 downto 0); -- Data Bus Input from GRAM
GDO : out std_logic_vector(31 downto 0); -- Data Bus Output to GRAM
-- FD Buffer RAM I/F
BCS_x : out std_logic; -- RAM Request
BADR : out std_logic_vector(22 downto 0); -- RAM Address
BWR_x : out std_logic; -- RAM Write Signal
BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
BDO : out std_logic_vector(7 downto 0); -- Data Bus Output to RAM
-- Resets
URST_x : out std_logic; -- Universal Reset
MRST_x : in std_logic; -- Reset after SDRAM init.
ARST_x : out std_logic; -- All Reset
-- Clock Input
CLOCK_50 : in std_logic; -- 50 MHz
-- Push Button
BUTTON : in std_logic_vector(2 downto 0); -- Pushbutton[2:0]
-- Switch
SW : in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
-- 7-SEG Dispaly
HEX0_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 0
HEX0_DP : out std_logic; -- Seven Segment Digit DP 0
HEX1_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 1
HEX1_DP : out std_logic; -- Seven Segment Digit DP 1
HEX2_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 2
HEX2_DP : out std_logic; -- Seven Segment Digit DP 2
HEX3_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 3
HEX3_DP : out std_logic; -- Seven Segment Digit DP 3
-- LED
LEDG : out std_logic_vector(9 downto 0); -- LED Green[9:0]
-- PS2
PS2_KBDAT : in std_logic; -- PS2 Keyboard Data
PS2_KBCLK : in std_logic; -- PS2 Keyboard Clock
-- VGA
VGA_HS : out std_logic; -- VGA H_SYNC
VGA_VS : out std_logic; -- VGA V_SYNC
VGA_R : out std_logic_vector(3 downto 0); -- VGA Red[3:0]
VGA_G : out std_logic_vector(3 downto 0); -- VGA Green[3:0]
VGA_B : out std_logic_vector(3 downto 0); -- VGA Blue[3:0]
-- GPIO
GPIO0_CLKIN : in std_logic_vector(1 downto 0); -- GPIO Connection 0 Clock In Bus
GPIO0_CLKOUT: out std_logic_vector(1 downto 0); -- GPIO Connection 0 Clock Out Bus
GPIO0_D : out std_logic_vector(31 downto 0); -- GPIO Connection 0 Data Bus
GPIO1_CLKIN : in std_logic_vector(1 downto 0); -- GPIO Connection 1 Clock In Bus
GPIO1_CLKOUT: out std_logic_vector(1 downto 0); -- GPIO Connection 1 Clock Out Bus
GPIO1_D : inout std_logic_vector(31 downto 0) -- GPIO Connection 1 Data Bus
);
end component;
component mz80b_de0
port (
spi_cs_export : out std_logic; -- export
cfi_tcm_address_out : out std_logic_vector(21 downto 0); -- tcm_address_out
cfi_tcm_read_n_out : out std_logic_vector(0 downto 0); -- tcm_read_n_out
cfi_tcm_write_n_out : out std_logic_vector(0 downto 0); -- tcm_write_n_out
cfi_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X'); -- tcm_data_out
cfi_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- tcm_chipselect_n_out
spi_MISO : in std_logic := 'X'; -- MISO
spi_MOSI : out std_logic; -- MOSI
spi_SCLK : out std_logic; -- SCLK
spi_SS_n : out std_logic_vector(1 downto 0); -- SS_n
uart_rxd : in std_logic := 'X'; -- rxd
uart_txd : out std_logic; -- txd
uart_cts_n : in std_logic := 'X'; -- cts_n
uart_rts_n : out std_logic; -- rts_n
clkin_clk : in std_logic := 'X'; -- clk
mem_address : out std_logic_vector(20 downto 0); -- address
mem_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
mem_writedata : out std_logic_vector(31 downto 0); -- writedata
mem_byteenable_n : out std_logic_vector(3 downto 0); -- byteenable_n
mem_chipselect_n : out std_logic; -- chipselect_n
mem_write_n : out std_logic; -- write_n
mem_waitrequest_n : in std_logic := 'X'; -- waitrequest_n
mem_reset_reset_n : out std_logic; -- reset_n
reset_reset_n : in std_logic := 'X'; -- reset_n
reg_address : out std_logic_vector(15 downto 0); -- address
reg_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
reg_writedata : out std_logic_vector(7 downto 0); -- writedata
reg_chipselect_n : out std_logic; -- chipselect_n
reg_write_n : out std_logic; -- write_n
reg_reset_reset_n : out std_logic; -- reset_n
intc_export : in std_logic := 'X' -- export
);
end component;
component sdram
port (
reset : in std_logic; -- Reset
RSTOUT : out std_logic; -- Reset After Init. SDRAM
CLOCK_50 : in std_logic; -- Clock(50MHz)
PCLK : out std_logic; -- CPU Clock
-- RAM access(port-A:Z80 bus)
AA : in std_logic_vector(22 downto 0); -- Address
DAI : in std_logic_vector(7 downto 0); -- Data Input(16bit)
DAO : out std_logic_vector(7 downto 0); -- Data Output(16bit)
CSA : in std_logic; -- Chip Select
WEA : in std_logic; -- Write Enable
PGA : in std_logic; -- Purge Cache
-- RAM access(port-B:Avalon bus bridge)
AB : in std_logic_vector(20 downto 0); -- Address
DBI : in std_logic_vector(31 downto 0); -- Data Input(32bit)
DBO : out std_logic_vector(31 downto 0); -- Data Output(32bit)
CSB : in std_logic; -- Chip Select
WEB : in std_logic; -- Write Enable
BEB : in std_logic_vector(3 downto 0); -- Byte Enable
WQB : out std_logic; -- CPU Wait
-- RAM access(port-C:Reserve)
AC : in std_logic_vector(21 downto 0); -- Address
DCI : in std_logic_vector(15 downto 0); -- Data Input(16bit)
DCO : out std_logic_vector(15 downto 0); -- Data Output(16bit)
CSC : in std_logic; -- Chip Select
WEC : in std_logic; -- Write Enable
BEC : in std_logic_vector(1 downto 0); -- Byte Enable
-- RAM access(port-D:FD Buffer Access port)
AD : in std_logic_vector(22 downto 0); -- Address
DDI : in std_logic_vector(7 downto 0); -- Data Input(16bit)
DDO : out std_logic_vector(7 downto 0); -- Data Output(16bit)
CSD : in std_logic; -- Chip Select
WED : in std_logic; -- Write Enable
--BED : in std_logic_vector(1 downto 0); -- Byte Enable
-- RAM access(port-E:Graphics Video Memory)
AE : in std_logic_vector(20 downto 0); -- Address
DEI : in std_logic_vector(31 downto 0); -- Data Input(32bit)
DEO : out std_logic_vector(31 downto 0); -- Data Output(32bit)
CSE : in std_logic; -- Chip Select
WEE : in std_logic; -- Write Enable
BEE : in std_logic_vector(3 downto 0); -- Byte Enable
-- SDRAM signal
MA : out std_logic_vector(11 downto 0); -- Address
MBA0 : out std_logic; -- Bank Address 0
MBA1 : out std_logic; -- Bank Address 1
MDI : in std_logic_vector(15 downto 0); -- Data Input(16bit)
MDO : out std_logic_vector(15 downto 0); -- Data Output(16bit)
MDOE : out std_logic; -- Data Output Enable
MLDQ : out std_logic; -- Lower Data Mask
MUDQ : out std_logic; -- Upper Data Mask
MCAS : out std_logic; -- Column Address Strobe
MRAS : out std_logic; -- Raw Address Strobe
MCS : out std_logic; -- Chip Select
MWE : out std_logic; -- Write Enable
MCKE : out std_logic; -- Clock Enable
MCLK : out std_logic -- SDRAM Clock
);
end component;
begin
--
-- Instantiation
--
MZ80B : mz80b_core port map(
-- Z80 Memory Bus
ZADR => ZADR,
ZDI => ZDI,
ZDO => ZDO,
ZCS_x =>ZCS_x,
ZWR_x => ZWR_x,
ZPG_x => ZPG_x,
-- NiosII Access
RRST_x => RRST_x, -- NiosII Reset
RCLK => PCLK, -- NiosII Clock
RADR => RADR, -- NiosII Address Bus
RCS_x => RCS_x, -- NiosII Read Signal
RWE_x => RWE_x, -- NiosII Write Signal
RDI => RDO, -- NiosII Data Bus(in)
RDO => RDI, -- NiosII Data Bus(out)
INTL => INTL, -- Interrupt Line
-- Graphic VRAM Access
GCS_x => GCS_x, -- GRAM Request
GADR => GADR, -- GRAM Address
GWR_x => GWR_x, -- GRAM Write Signal
GBE_x => GBE_x, -- GRAM Byte Enable
GDI => GDI, -- Data Bus Input from GRAM
GDO => GDO, -- Data Bus Output to GRAM
-- FD Buffer RAM I/F
BCS_x => BCS_x, -- RAM Request
BADR => BADR, -- RAM Address
BWR_x => BWR_x, -- RAM Write Signal
BDI => BDI, -- Data Bus Input from RAM
BDO => BDO, -- Data Bus Output to RAM
-- Resets
URST_x => URST, -- Universal Reset
MRST_x => MRST, -- All Reset
ARST_x => ARST, -- All Reset
-- Clock Input
CLOCK_50 => CLOCK_50, -- 50 MHz
-- Push Button
BUTTON => BUTTON, -- Pushbutton[2:0]
-- Switch
SW => SW, -- Toggle Switch[9:0]
-- 7-SEG Dispaly
HEX0_D => HEX0_D, -- Seven Segment Digit 0
HEX0_DP => HEX0_DP, -- Seven Segment Digit DP 0
HEX1_D => HEX1_D, -- Seven Segment Digit 1
HEX1_DP => HEX1_DP, -- Seven Segment Digit DP 1
HEX2_D => HEX2_D, -- Seven Segment Digit 2
HEX2_DP => HEX2_DP, -- Seven Segment Digit DP 2
HEX3_D => HEX3_D, -- Seven Segment Digit 3
HEX3_DP => HEX3_DP, -- Seven Segment Digit DP 3
-- LED
LEDG => T_LEDG, -- LED Green[9:0]
-- PS2
PS2_KBDAT => PS2_KBDAT, -- PS2 Keyboard Data
PS2_KBCLK => PS2_KBCLK, -- PS2 Keyboard Clock
-- VGA
VGA_HS => VGA_HS, -- VGA H_SYNC
VGA_VS => VGA_VS, -- VGA V_SYNC
VGA_R => VGA_R, -- VGA Red[3:0]
VGA_G => VGA_G, -- VGA Green[3:0]
VGA_B => VGA_B, -- VGA Blue[3:0]
-- GPIO
GPIO0_CLKIN => GPIO0_CLKIN, -- GPIO Connection 0 Clock In Bus
GPIO0_CLKOUT => GPIO0_CLKOUT, -- GPIO Connection 0 Clock Out Bus
GPIO0_D => GPIO0_D, -- GPIO Connection 0 Data Bus
GPIO1_CLKIN => GPIO1_CLKIN, -- GPIO Connection 1 Clock In Bus
GPIO1_CLKOUT => GPIO1_CLKOUT, -- GPIO Connection 1 Clock Out Bus
GPIO1_D => GPIO1_D -- GPIO Connection 1 Data Bus
);
SOPC0 : mz80b_de0 port map (
spi_cs_export => SD_CS, -- spi_cs.export
cfi_tcm_address_out => FL_ADDR0, -- cfi.tcm_address_out
cfi_tcm_read_n_out => FL_OE_Ni, -- .tcm_read_n_out
cfi_tcm_write_n_out => FL_WE_Ni, -- .tcm_write_n_out
cfi_tcm_data_out => FL_DQ, -- .tcm_data_out
cfi_tcm_chipselect_n_out => FL_CE_Ni, -- .tcm_chipselect_n_out
spi_MISO => SD_DAT0, -- spi.MISO
spi_MOSI => SD_DO, -- .MOSI
spi_SCLK => SD_CLK, -- .SCLK
spi_SS_n => SD_DEN, -- .SS_n
uart_rxd => UART_RXD, -- uart.rxd
uart_txd => UART_TXD, -- .txd
uart_cts_n => UART_CTS, -- .cts_n
uart_rts_n => UART_RTS, -- .rts_n
clkin_clk => PCLK, -- clkin.clk
mem_address => MADR, -- mem.address
mem_readdata => MDI, -- .readdata
mem_writedata => MDO, -- .writedata
mem_byteenable_n => MBEN_x, -- .byteenable_n
mem_chipselect_n => MCS_x, -- .chipselect_n
mem_write_n => MWE_x, -- .write_n
mem_waitrequest_n => MWRQ_x, -- .waitrequest_n
mem_reset_reset_n => open, -- mem_reset.reset_n
reset_reset_n => ARST, -- reset.reset_n
reg_address => RADR, -- reg.address
reg_readdata => RDI, -- .readdata
reg_writedata => RDO, -- .writedata
reg_chipselect_n => RCS_x, -- .chipselect_n
reg_write_n => RWE_x, -- .write_n
reg_reset_reset_n => RRST_x, -- reg_reset.reset_n
intc_export => INTL -- intc.export
);
DRAM0 : sdram port map (
reset => URST, -- Reset
RSTOUT => MRST, -- Reset After Init. SDRAM
CLOCK_50 => CLOCK_50_2, -- Clock(50MHz)
PCLK => PCLK, -- CPU Clock
-- RAM access(port-A:Z80 Memory Bus)
AA => ZADR, -- Address
DAI => ZDO, -- Data Input(16bit)
DAO => ZDI, -- Data Output(16bit)
CSA => ZCS_x, -- Chip Select
WEA => ZWR_x, -- Write Enable
PGA => ZPG_x, -- Purge Cache
-- RAM access(port-B:Avalon Bus)
AB => MADR, -- Address
DBI => MDO, -- Data Input(32bit)
DBO => MDI, -- Data Output(32bit)
CSB => MCS_x, -- Chip Select
WEB => MWE_x, -- Write Enable
BEB => MBEN_x, -- Byte Enable
WQB => MWRQ_x, -- CPU Wait
-- RAM access(port-C:Reserve)
AC => (others=>'1'), -- Address
DCI => (others=>'0'), -- Data Input(16bit)
DCO => open, -- Data Output(16bit)
CSC => '1', -- Chip Select
WEC => '1', -- Write Enable
BEC => "11", -- Byte Enable
-- RAM access(port-D:FD Buffer)
AD => BADR, -- Address
DDI => BDO, -- Data Input(16bit)
DDO => BDI, -- Data Output(16bit)
CSD => BCS_x, -- Chip Select
WED => BWR_x, -- Write Enable
--BED => "00", -- Byte Enable
-- RAM access(port-E:Graphics Video Memory)
AE => GADR, -- Address
DEI => GDO, -- Data Input(32bit)
DEO => GDI, -- Data Output(32bit)
CSE => GCS_x, -- Chip Select
WEE => GWR_x, -- Write Enable
BEE => GBE_x, -- Byte Enable
-- SDRAM signal
MA => DRAM_ADDR(11 downto 0), -- Address
MBA0 => DRAM_BA_0, -- Bank Address 0
MBA1 => DRAM_BA_1, -- Bank Address 1
MDI => DRAM_DQ, -- Data Input(16bit)
MDO => SDRAMDO, -- Data Output(16bit)
MDOE => SDRAMDOE, -- Data Output Enable
MLDQ => DRAM_LDQM, -- Lower Data Mask
MUDQ => DRAM_UDQM, -- Upper Data Mask
MCAS => DRAM_CAS_N, -- Column Address Strobe
MRAS => DRAM_RAS_N, -- Raw Address Strobe
MCS => DRAM_CS_N, -- Chip Select
MWE => DRAM_WE_N, -- Write Enable
MCKE => DRAM_CKE, -- Clock Enable
MCLK => DRAM_CLK -- SDRAM Clock
);
--
-- MMC/SD CARD
--
SD_CMD<=SD_DO when SD_DEN(1)='0' else '1';
SD_DAT3<=SD_CS;
--
-- SDRAM
--
DRAM_DQ<=SDRAMDO when SDRAMDOE='1' else (others=>'Z');
--
-- Flash Memory
--
FL_ADDR<='0'&FL_ADDR0(21 downto 1);
FL_RST_N<='1'; --URST;
FL_WP_N<='1';
FL_BYTE_N<='1';
FL_WE_N<=FL_WE_Ni(0);
FL_OE_N<=FL_OE_Ni(0);
FL_CE_N<=FL_CE_Ni(0);
--
-- Misc & Debug
--
LEDG<=(not SD_CS)&T_LEDG(8 downto 0);
-- LEDG<=(not SD_CS)&"000000000";
--GPIO0_D(0)<=PS2_KBCLK;
--GPIO0_D(1)<=PS2_KBDAT;
--GPIO0_D(2)<=KBEN;
--GPIO0_D(10 downto 3)<=KBDT;
--GPIO0_D(11)<=ARST;
end rtl;

6
mz80b/old/pll100.qip
View File

@@ -1,6 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll100.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll100_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll100.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll100.ppf"]

446
mz80b/old/pll100.vhd
View File

@@ -1,446 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll100.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll100 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
);
END pll100;
ARCHITECTURE SYN OF pll100 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "-1667",
clk2_divide_by => 5,
clk2_duty_cycle => 50,
clk2_multiply_by => 2,
clk2_phase_shift => "0",
clk3_divide_by => 1600,
clk3_duty_cycle => 50,
clk3_multiply_by => 1,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll100",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "20.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.031250"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "20.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.03125000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-60.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll100.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1667"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1600"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll100_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

6
mz80b/old/pll50.qip
View File

@@ -1,6 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "12.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll50.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll50_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll50.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll50.ppf"]

446
mz80b/old/pll50.vhd
View File

@@ -1,446 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll50.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll50 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
);
END pll50;
ARCHITECTURE SYN OF pll50 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 25,
clk1_duty_cycle => 50,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
clk2_divide_by => 25,
clk2_duty_cycle => 50,
clk2_multiply_by => 2,
clk2_phase_shift => "0",
clk3_divide_by => 1600,
clk3_duty_cycle => 50,
clk3_multiply_by => 1,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll50",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "4.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.031250"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "4.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.03125000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll50.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1600"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

77
mz80b/old/ps2kb.vhd
View File

@@ -1,77 +0,0 @@
--
-- ps2kb.vhd
--
-- PS/2 Keyboard Interface module
-- for MZ-700 on FPGA
--
-- Nibbles Lab. 2005
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ps2kb is
Port ( RST : in std_logic;
KCLK : in std_logic;
PS2CK : in std_logic;
PS2DT : in std_logic;
DTEN : out std_logic;
DATA : out std_logic_vector(7 downto 0));
end ps2kb;
architecture Behavioral of ps2kb is
--
-- PS/2 recieve data
--
signal KEYDT : std_logic_vector(10 downto 0);
signal CKDT : std_logic_vector(3 downto 0);
--
-- Parity
--
signal PARITY : std_logic;
begin
--
-- PS/2 recieve
--
process( RST, KCLK ) begin
if RST='0' then
KEYDT<=(others=>'1');
DATA<=(others=>'0');
DTEN<='0';
elsif KCLK'event and KCLK='1' then
CKDT<=CKDT(2 downto 0)&PS2CK;
if CKDT="0011" then
KEYDT<=PS2DT&KEYDT(10 downto 1);
end if;
if KEYDT(0)='0' and KEYDT(10)='1' and KEYDT(9)=not PARITY then
DTEN<='1';
DATA<=KEYDT(8 downto 1);
KEYDT<=(others=>'1');
else
DTEN<='0';
end if;
end if;
end process;
process( KEYDT(9 downto 2) )
variable TEMP : std_logic;
begin
TEMP:='0';
for I in 1 to 8 loop
TEMP:=TEMP xor KEYDT(I);
end loop;
PARITY<=TEMP;
end process;
end Behavioral;

755
mz80b/old/sdram.vhd
View File

@@ -1,755 +0,0 @@
--
-- sdram.vhd
--
-- SDRAM access module with self refresh and multi ports
-- for MZ-80C/80B on FPGA
--
-- Nibbles Lab. 2007-2014
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdram is
port (
reset : in std_logic; -- Reset
RSTOUT : out std_logic; -- Reset After Init. SDRAM
CLOCK_50 : in std_logic; -- Clock(50MHz)
PCLK : out std_logic; -- NiosII Clock(20MHz)
-- RAM access(port-A:Z80 bus)
AA : in std_logic_vector(22 downto 0); -- Address
DAI : in std_logic_vector(7 downto 0); -- Data Input(16bit)
DAO : out std_logic_vector(7 downto 0); -- Data Output(16bit)
CSA : in std_logic; -- Chip Select
WEA : in std_logic; -- Write Enable
PGA : in std_logic; -- Purge Cache
--BEA : in std_logic_vector(1 downto 0); -- Byte Enable
-- RAM access(port-B:Avalon bus bridge)
AB : in std_logic_vector(20 downto 0); -- Address
DBI : in std_logic_vector(31 downto 0); -- Data Input(32bit)
DBO : out std_logic_vector(31 downto 0); -- Data Output(32bit)
CSB : in std_logic; -- Chip Select
WEB : in std_logic; -- Write Enable
BEB : in std_logic_vector(3 downto 0); -- Byte Enable
WQB : out std_logic; -- CPU Wait
-- RAM access(port-C:Reserve)
AC : in std_logic_vector(21 downto 0); -- Address
DCI : in std_logic_vector(15 downto 0); -- Data Input(16bit)
DCO : out std_logic_vector(15 downto 0); -- Data Output(16bit)
CSC : in std_logic; -- Chip Select
WEC : in std_logic; -- Write Enable
BEC : in std_logic_vector(1 downto 0); -- Byte Enable
-- RAM access(port-D:FD Buffer Access port)
AD : in std_logic_vector(22 downto 0); -- Address
DDI : in std_logic_vector(7 downto 0); -- Data Input(16bit)
DDO : out std_logic_vector(7 downto 0); -- Data Output(16bit)
CSD : in std_logic; -- Chip Select
WED : in std_logic; -- Write Enable
--BED : in std_logic_vector(1 downto 0); -- Byte Enable
-- RAM access(port-E:Graphics Video Memory)
AE : in std_logic_vector(20 downto 0); -- Address
DEI : in std_logic_vector(31 downto 0); -- Data Input(32bit)
DEO : out std_logic_vector(31 downto 0); -- Data Output(32bit)
CSE : in std_logic; -- Chip Select
WEE : in std_logic; -- Write Enable
BEE : in std_logic_vector(3 downto 0); -- Byte Enable
-- SDRAM signal
MA : out std_logic_vector(11 downto 0); -- Address
MBA0 : out std_logic; -- Bank Address 0
MBA1 : out std_logic; -- Bank Address 1
MDI : in std_logic_vector(15 downto 0); -- Data Input(16bit)
MDO : out std_logic_vector(15 downto 0); -- Data Output(16bit)
MDOE : out std_logic; -- Data Output Enable
MLDQ : out std_logic; -- Lower Data Mask
MUDQ : out std_logic; -- Upper Data Mask
MCAS : out std_logic; -- Column Address Strobe
MRAS : out std_logic; -- Raw Address Strobe
MCS : out std_logic; -- Chip Select
MWE : out std_logic; -- Write Enable
MCKE : out std_logic; -- Clock Enable
MCLK : out std_logic -- SDRAM Clock
);
end sdram;
architecture rtl of sdram is
signal A : std_logic_vector(21 downto 0);
signal RA : std_logic_vector(21 downto 0);
signal RD : std_logic_vector(21 downto 0);
--signal DI : std_logic_vector(15 downto 0);
signal WCNT : std_logic_vector(2 downto 0);
signal CNT200 : std_logic;
signal CNT3 : std_logic_vector(2 downto 0);
--signal BUF : std_logic_vector(7 downto 0);
signal CSMA : std_logic; -- Masked
signal CSMD : std_logic; -- Masked
signal PGAi : std_logic; -- Purge Flag
signal PGDi : std_logic; -- Purge Flag
signal CSAi : std_logic;
signal CSAii : std_logic_vector(3 downto 0);
signal CSBi : std_logic;
signal CSBii : std_logic_vector(3 downto 0);
signal CSCi : std_logic;
signal CSCii : std_logic_vector(3 downto 0);
signal CSDi : std_logic;
signal CSDii : std_logic_vector(3 downto 0);
signal CSDiii : std_logic_vector(3 downto 0);
signal CSEi : std_logic;
signal CSEii : std_logic_vector(3 downto 0);
signal REFCNT : std_logic_vector(10 downto 0);
signal PA : std_logic;
signal PB : std_logic;
signal PC : std_logic;
signal PD : std_logic;
signal PE : std_logic;
signal WB : std_logic;
signal DAIR : std_logic_vector(15 downto 0);
signal DAOR : std_logic_vector(15 downto 0);
signal DBIR : std_logic_vector(31 downto 0);
signal DCIR : std_logic_vector(15 downto 0);
signal DDIR : std_logic_vector(15 downto 0);
signal DDOR : std_logic_vector(15 downto 0);
signal DEIR : std_logic_vector(31 downto 0);
signal WAITB : std_logic;
signal RDEN : std_logic;
signal WREN : std_logic;
signal UBEN : std_logic;
signal LBEN : std_logic;
signal UBEN2 : std_logic;
signal LBEN2 : std_logic;
signal RWAIT : std_logic;
signal MEMCLK : std_logic;
signal SCLK : std_logic;
--
-- State Machine
--
signal CUR : std_logic_vector(5 downto 0); -- Current Status
signal NXT : std_logic_vector(5 downto 0); -- Next Status
constant IWAIT : std_logic_vector(5 downto 0) := "000000"; -- 200us Wait
constant IPALL : std_logic_vector(5 downto 0) := "000001"; -- All Bank Precharge
constant IDLY1 : std_logic_vector(5 downto 0) := "000010"; -- Initial Delay 1
constant IRFSH : std_logic_vector(5 downto 0) := "000011"; -- Auto Refresh
constant IDLY2 : std_logic_vector(5 downto 0) := "000100"; -- Initial Delay 2
constant IDLY3 : std_logic_vector(5 downto 0) := "000101"; -- Initial Delay 3
constant IDLY4 : std_logic_vector(5 downto 0) := "000110"; -- Initial Delay 4
constant IDLY5 : std_logic_vector(5 downto 0) := "000111"; -- Initial Delay 5
constant IDLY6 : std_logic_vector(5 downto 0) := "001000"; -- Initial Delay 6
constant IMODE : std_logic_vector(5 downto 0) := "001001"; -- Mode Register Setting
constant RACT : std_logic_vector(5 downto 0) := "001010"; -- Read Activate
constant RDLY1 : std_logic_vector(5 downto 0) := "001011"; -- Read Delay 1
constant READ : std_logic_vector(5 downto 0) := "001100"; -- Read
constant READ2 : std_logic_vector(5 downto 0) := "001101"; -- Read 2nd word
constant RDLY2 : std_logic_vector(5 downto 0) := "001110"; -- Read Delay 2
constant RDLY3 : std_logic_vector(5 downto 0) := "001111"; -- Read Delay 3
constant RPRE : std_logic_vector(5 downto 0) := "010000"; -- Precharge
constant RDLY4 : std_logic_vector(5 downto 0) := "010001"; -- Read Delay 4
constant HALT : std_logic_vector(5 downto 0) := "010010"; -- Waiting
constant WACT : std_logic_vector(5 downto 0) := "010011"; -- Write Activate
constant WDLY1 : std_logic_vector(5 downto 0) := "010100"; -- Write Delay 1
constant WRIT : std_logic_vector(5 downto 0) := "010101"; -- Write
constant WRIT2 : std_logic_vector(5 downto 0) := "010110"; -- Write 2nd word
constant WDLY2 : std_logic_vector(5 downto 0) := "010111"; -- Write Delay 2
constant WDLY3 : std_logic_vector(5 downto 0) := "011000"; -- Write Delay 3
constant WPRE : std_logic_vector(5 downto 0) := "011001"; -- Precharge
constant FRFSH : std_logic_vector(5 downto 0) := "011010"; -- Auto Refresh
constant FDLY1 : std_logic_vector(5 downto 0) := "011011"; -- Refresh Delay 1
constant FDLY2 : std_logic_vector(5 downto 0) := "011100"; -- Refresh Delay 2
constant FDLY3 : std_logic_vector(5 downto 0) := "011101"; -- Refresh Delay 3
constant FDLY4 : std_logic_vector(5 downto 0) := "011110"; -- Refresh Delay 4
--
-- Components
--
component pll100
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
);
end component;
begin
--
-- Instantiation
--
RCKGEN0 : pll100 PORT MAP (
inclk0 => CLOCK_50, -- Master Clock (50MHz) ... input
c0 => MEMCLK, -- SDRAM Controler Clock (100MHz) ... internal use
c1 => MCLK, -- SDRAM Clock (100MHz:-60deg) ... output
c2 => PCLK, -- Nios II Clock (20MHz) ... output
c3 => SCLK -- Slow Clock (31.25kHz) ... internal use/output
);
--
-- Seqence control
--
process( reset, MEMCLK ) begin
if reset='0' then
CUR<=IWAIT; -- Start at Initial-Waiting(200us)
elsif MEMCLK'event and MEMCLK='1' then
CUR<=NXT; -- Move to Next State
end if;
end process;
--
-- Arbitoration and Data Output
--
process( reset, MEMCLK ) begin
if reset='0' then
CSAi<='0';
CSBi<='0';
CSCi<='0';
CSDi<='0';
CSEi<='0';
CSAii<=(others=>'1');
CSBii<=(others=>'1');
CSCii<=(others=>'1');
CSDii<=(others=>'1');
CSEii<=(others=>'1');
PA<='0';
PB<='0';
PC<='0';
PD<='0';
PE<='0';
WAITB<='1';
-- WAITD<='1';
RDEN<='0';
WREN<='0';
UBEN<='1';
LBEN<='1';
UBEN2<='1';
LBEN2<='1';
PGAi<='0';
elsif MEMCLK'event and MEMCLK='1' then
--
-- Sense CS
--
CSAii<=CSAii(2 downto 0)&CSMA;
if CSAii(1 downto 0)="10" then
CSAi<='1';
DAIR<=DAI&DAI;
end if;
CSBii<=CSBii(2 downto 0)&CSB;
if CSBii="1110" then
WAITB<='0';
end if;
if CSBii(1 downto 0)="10" then
CSBi<='1';
DBIR<=DBI;
end if;
CSCii<=CSCii(2 downto 0)&CSC;
if CSCii(1 downto 0)="10" then
CSCi<='1';
DCIR<=DCI;
end if;
CSDii<=CSDii(2 downto 0)&CSMD;
if CSDii(1 downto 0)="10" then
CSDi<='1';
DDIR(15 downto 8)<=DDI;
end if;
CSEii<=CSEii(2 downto 0)&CSE;
if CSEii(1 downto 0)="10" then
CSEi<='1';
DEIR<=DEI;
end if;
CSDiii<=CSDiii(2 downto 0)&CSD;
if CSDiii(1 downto 0)="10" and AD(0)='0' then
DDIR(7 downto 0)<=DDI;
end if;
--
-- Select Response Port
--
if CUR=HALT then
if CSAi='1' and PB='0' and PC='0' and PD='0' and PE='0' then
PA<='1';
RDEN<=WEA;
WREN<=not WEA;
UBEN<=(not AA(0)) and (not WEA);
LBEN<=AA(0) and (not WEA);
UBEN2<='1';
LBEN2<='1';
elsif CSCi='1' and PA='0' and PB='0' and PD='0' and PE='0' then
PC<='1';
RDEN<=WEC;
WREN<=not WEC;
UBEN<=BEC(1);
LBEN<=BEC(0);
UBEN2<='1';
LBEN2<='1';
elsif CSEi='1' and PA='0' and PB='0' and PC='0' and PD='0' then
PE<='1';
RDEN<=WEE;
WREN<=not WEE;
UBEN2<=BEE(3);
LBEN2<=BEE(2);
UBEN<=BEE(1);
LBEN<=BEE(0);
elsif CSDi='1' and PA='0' and PB='0' and PC='0' and PE='0' then
PD<='1';
RDEN<=WED;
WREN<=not WED;
UBEN<='0';
LBEN<='0';
UBEN2<='1';
LBEN2<='1';
elsif CSBi='1' and PA='0' and PC='0' and PD='0' and PE='0' then
PB<='1';
RDEN<=WEB;
WREN<=not WEB;
UBEN2<=BEB(3);
LBEN2<=BEB(2);
UBEN<=BEB(1);
LBEN<=BEB(0);
else
PA<='0'; PB<='0'; PC<='0'; PD<='0'; PE<='0';
RDEN<='0';
WREN<='0';
UBEN<='1';
LBEN<='1';
UBEN2<='1';
LBEN2<='1';
end if;
end if;
--
-- Deselect Port
--
if CUR=RPRE or CUR=WPRE then
if PA='1' then
PA<='0';
RDEN<='0';
WREN<='0';
CSAi<='0';
end if;
if PC='1' then
PC<='0';
RDEN<='0';
WREN<='0';
CSCi<='0';
end if;
if PD='1' then
PD<='0';
RDEN<='0';
WREN<='0';
CSDi<='0';
end if;
end if;
if CUR=RDLY4 or CUR=WPRE then
if PB='1' then
PB<='0';
RDEN<='0';
WREN<='0';
CSBi<='0';
WAITB<='1';
end if;
if PE='1' then
PE<='0';
RDEN<='0';
WREN<='0';
CSEi<='0';
end if;
end if;
--
-- Data Output for Processor
--
if CUR=RPRE then -- Ready for Data Output
if PA='1' then
DAOR<=MDI;
RA<=A;
PGAi<='1';
elsif PB='1' then
DBO(15 downto 0)<=MDI;
elsif PC='1' then
DCO<=MDI;
elsif PD='1' then
DDOR<=MDI;
RD<=A;
PGDi<='1';
elsif PE='1' then
DEO(15 downto 0)<=MDI;
end if;
end if;
if CUR=RDLY4 then
if PB='1' then
DBO(31 downto 16)<=MDI;
elsif PE='1' then
DEO(31 downto 16)<=MDI;
end if;
end if;
--
-- Data Output for SDRAM
--
if CUR=WACT then
if PA='1' then
MDO<=DAIR;
elsif PB='1' then
MDO<=DBIR(15 downto 0);
elsif PC='1' then
MDO<=DCIR;
elsif PD='1' then
MDO<=DDIR;
elsif PE='1' then
MDO<=DEIR(15 downto 0);
end if;
elsif CUR=WRIT then
if PB='1' then
MDO<=DBIR(31 downto 16);
elsif PE='1' then
MDO<=DEIR(31 downto 16);
end if;
end if;
--
-- Purge Flag
--
if PGA='0' then
PGAi<='0';
end if;
end if;
end process;
--
-- Wait Control for NiosII
--
WQB<=CSB or WAITB;
--
-- Wait after Reset
--
process( reset, SCLK ) begin -- SCLK=31.25kHz
if reset='0' then
WCNT<=(others=>'0');
CNT200<='0';
elsif SCLK'event and SCLK='1' then
if WCNT="110" then
CNT200<='1';
else
WCNT<=WCNT+1;
end if;
end if;
end process;
--
-- Refresh Times Counter for Initialize (8 times)
--
process( reset, MEMCLK ) begin
if reset='0' then
CNT3<=(others=>'0');
elsif MEMCLK'event and MEMCLK='1' then
if CUR=IWAIT then
CNT3<=(others=>'0');
elsif CUR=IDLY3 then
CNT3<=CNT3+1;
end if;
end if;
end process;
--
-- Refresh Cycle Counter
--
process( reset, MEMCLK ) begin
if reset='0' then
REFCNT<=(others=>'0');
elsif MEMCLK'event and MEMCLK='1' then
if CUR=FRFSH then -- Enter Refresh Command
REFCNT<=(others=>'0');
else
REFCNT<=REFCNT+'1';
end if;
end if;
end process;
--
-- Sequencer
--
process( CUR, CNT200, CNT3, REFCNT, RDEN, WREN, PA, PB, PC, PD, PE ) begin
case CUR is
-- Initialize
when IWAIT => -- 200us Wait
if CNT200='1' then
NXT<=IPALL;
else
NXT<=IWAIT;
end if;
when IPALL => -- All Bank Precharge
NXT<=IDLY1;
when IDLY1 => -- Initial Delay 1
NXT<=IRFSH;
when IRFSH => -- Auto Refresh
NXT<=IDLY2;
when IDLY2 => -- Initial Delay 2
NXT<=IDLY3;
when IDLY3 => -- Initial Delay 2
NXT<=IDLY4;
when IDLY4 => -- Initial Delay 2
NXT<=IDLY5;
when IDLY5 => -- Initial Delay 2
NXT<=IDLY6;
when IDLY6 => -- Initial Delay 3
if CNT3="111" then
NXT<=IMODE;
else
NXT<=IDLY1;
end if;
when IMODE => -- Mode Register Setting
NXT<=HALT;
-- Read
when RACT => -- Read Activate
NXT<=RDLY1;
when RDLY1 => -- Read Delay 1
NXT<=READ;
when READ => -- Read once or 1st word
if PB='1' or PE='1' then
NXT<=READ2;
else
NXT<=RDLY2;
end if;
when READ2|RDLY2 => -- Read 2nd word / Read Delay 2
NXT<=RDLY3;
when RDLY3 => -- Read Delay 3
NXT<=RPRE;
when RPRE => -- Precharge
if PB='1' or PE='1' then
NXT<=RDLY4;
else
NXT<=HALT;
end if;
when RDLY4 => -- Read Delay 4
NXT<=HALT;
-- Waiting
when HALT => -- Waiting
if REFCNT>"11000000100" then -- Over 1540 Counts
NXT<=FRFSH;
elsif RDEN='1' then
NXT<=RACT;
elsif WREN='1' then
NXT<=WACT;
else
NXT<=HALT;
end if;
-- Write
when WACT => -- Write Activate
NXT<=WDLY1;
when WDLY1 => -- Write Delay 1
NXT<=WRIT;
when WRIT => -- Write once or 1st word
if PB='1' or PE='1' then
NXT<=WRIT2;
else
NXT<=WDLY2;
end if;
when WRIT2|WDLY2 => -- Write 2nd word / Write Delay 2
NXT<=WDLY3;
when WDLY3 => -- Write Delay 3
NXT<=WPRE;
when WPRE => -- Precharge
NXT<=HALT;
-- Refresh
when FRFSH => -- Auto Refresh
NXT<=FDLY1;
when FDLY1 => -- Refresh Delay 1
NXT<=FDLY2;
when FDLY2 => -- Refresh Delay 2
NXT<=FDLY3;
when FDLY3 => -- Refresh Delay 3
NXT<=FDLY4;
when FDLY4 => -- Refresh Delay 4
NXT<=HALT;
when others =>
NXT<=HALT;
end case;
end process;
--
-- Command operation
--
-- MA(11 downto 0)
process( CUR, A ) begin
case CUR is
when IMODE => -- Mode Register Setting
MA<="0010" & "0" & "011" & "0" & "000"; -- w-single,CL=3,WT=0(seq),BL=1
--MA<="0010" & "0" & "010" & "0" & "000"; -- w-single,CL=2,WT=0(seq),BL=1
--MA<="0010" & "0" & "010" & "0" & "001"; -- w-single,CL=2,WT=0(seq),BL=2
when RACT|WACT => -- Read/Write Activate
MA<=A(19 downto 8);
when IPALL => -- All Bank Precharge
MA<="010000000000";
when READ|WRIT => -- Read/Write
--MA(11 downto 8)<="0100"; -- auto precharge
MA(11 downto 8)<="0000"; -- manual precharge
MA(7 downto 0)<=A(7 downto 0);
when READ2|WRIT2 => -- Read/Write 2nd word
--MA(11 downto 8)<="0100"; -- auto precharge
MA(11 downto 8)<="0000"; -- manual precharge
MA(7 downto 0)<=A(7 downto 1)&'1';
-- when RPRE|WPRE => -- Select Bank Precharge
-- MA<="000000000000";
when others =>
MA<=(others=>'0');
end case;
end process;
-- LBEN/UBEN
process( CUR, LBEN, UBEN, LBEN2, UBEN2 ) begin
case CUR is
when READ2|RDLY2|WRIT => -- Read 2nd word/Read delay 2/Write
MLDQ<=LBEN;
MUDQ<=UBEN;
when RDLY3|WRIT2 => -- Read delay 3/Write 2nd word
MLDQ<=LBEN2;
MUDQ<=UBEN2;
when others =>
MLDQ<='1';
MUDQ<='1';
end case;
end process;
-- MDOE
process( CUR ) begin
case CUR is
when WRIT => -- Write
MDOE<='1';
when WRIT2 => -- Write 2nd word
MDOE<='1';
when others =>
MDOE<='0';
end case;
end process;
-- MWE
process( CUR ) begin
case CUR is
when IMODE => -- Mode Register Setting
MWE<='0';
when IPALL => -- All Bank Precharge
MWE<='0';
when WRIT => -- Write
MWE<='0';
when WRIT2 => -- Write 2nd word
MWE<='0';
when RPRE|WPRE => -- Select Bank Precharge
MWE<='0';
when others =>
MWE<='1';
end case;
end process;
-- MCS
process( CUR ) begin
case CUR is
when IMODE => -- Mode Register Setting
MCS<='0';
when RACT|WACT => -- Read/Write Activate
MCS<='0';
when IPALL => -- All Bank Precharge
MCS<='0';
when READ => -- Read
MCS<='0';
when READ2 => -- Read 2nd word
MCS<='0';
when WRIT => -- Write
MCS<='0';
when WRIT2 => -- Write 2nd word
MCS<='0';
when IRFSH|FRFSH => -- auto refresh
MCS<='0';
when RPRE|WPRE => -- Select Bank Precharge
MCS<='0';
when others =>
MCS<='1';
end case;
end process;
-- MRAS/MCAS
process( CUR ) begin
case CUR is
when IMODE => -- Mode Register Setting
MRAS<='0';
MCAS<='0';
when RACT|WACT => -- Read/Write Activate
MRAS<='0';
MCAS<='1';
when IPALL => -- All Bank Precharge
MRAS<='0';
MCAS<='1';
when READ => -- Read
MRAS<='1';
MCAS<='0';
when READ2 => -- Read 2nd word
MRAS<='1';
MCAS<='0';
when WRIT => -- Write
MRAS<='1';
MCAS<='0';
when WRIT2 => -- Write 2nd word
MRAS<='1';
MCAS<='0';
when IRFSH|FRFSH => -- auto refresh
MRAS<='0';
MCAS<='0';
when RPRE|WPRE => -- Select Bank Precharge
MRAS<='0';
MCAS<='1';
when others =>
MRAS<='1';
MCAS<='1';
end case;
end process;
--
-- Reset Control
--
process( reset, MEMCLK ) begin
if reset='0' then
RSTOUT<='0';
elsif MEMCLK'event and MEMCLK='1' then
if CUR=HALT then
RSTOUT<='1';
end if;
end if;
end process;
--
-- SDRAM ports(Fixed Signals)
--
MCKE<='1';
MBA0<=A(20);
MBA1<=A(21);
--
-- Ports select
--
A <=AA(22 downto 1) when PA='1' else
AB&'0' when PB='1' else
AC when PC='1' else
AD(22 downto 1) when PD='1' else
AE&'0' when PE='1' else (others=>'0');
DAO<=DAOR(15 downto 8) when AA(0)='1' else DAOR(7 downto 0);
CSMA<=(CSA or WEA) when RA=AA(22 downto 1) and PGAi='1' else CSA;
DDO<=DDOR(15 downto 8) when AD(0)='1' else DDOR(7 downto 0);
CSMD<=CSD when (AD(0)='0' and WED='1') or (AD(0)='1' and WED='0') else '1';
-- process(RA, AA(22 downto 1), PGAi, CSA, WEA) begin
-- if RA=AA(22 downto 1) then
-- if PGAi='0' then
-- CSMA<=CSA;
-- else
-- if WEA='0' then
-- CSMA<=CSA;
-- else
-- CSMA<='1';
-- end if;
-- end if;
-- else
-- CSMA<=CSA;
-- end if;
-- end process;
end rtl;

174
mz80b/old/seg7.vhd
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@@ -1,174 +0,0 @@
--
-- 7seg.vhd
--
-- 4-digit 7-segment LED decorder
-- for MZ-80B on FPGA
--
-- Nibbles Lab. 2013
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seg7 is
Port (
-- 7-SEG Dispaly
HEX0_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 0
HEX0_DP : out std_logic; -- Seven Segment Digit DP 0
HEX1_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 1
HEX1_DP : out std_logic; -- Seven Segment Digit DP 1
HEX2_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 2
HEX2_DP : out std_logic; -- Seven Segment Digit DP 2
HEX3_D : out std_logic_vector(6 downto 0); -- Seven Segment Digit 3
HEX3_DP : out std_logic; -- Seven Segment Digit DP 3
-- Status Signal
MZMODE : in std_logic; -- Hardware Mode
-- "0" .. MZ-80B
-- "1" .. MZ-2000
DMODE : in std_logic; -- Display Mode
-- "0" .. Green
-- "1" .. Color
SCLK : in std_logic;
APSS : in std_logic;
FF : in std_logic;
REW : in std_logic;
NUMEN : in std_logic;
NUMBER : in std_logic_vector(15 downto 0)
);
end seg7;
architecture RTL of seg7 is
signal TCNT : std_logic_vector(2 downto 0) := "000";
signal DCNT : std_logic_vector(12 downto 0) := "0000000000000";
begin
HEX3_D<= "1111111" when APSS='0' and NUMEN='0' and MZMODE='0' else -- " "
"0100100" when APSS='0' and NUMEN='0' and MZMODE='1' else -- "2"
"1000000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"0" else -- "0"
"1111001" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"1" else -- "1"
"0100100" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"2" else -- "2"
"0110000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"3" else -- "3"
"0011001" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"4" else -- "4"
"0010010" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"5" else -- "5"
"0000010" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"6" else -- "6"
"1011000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"7" else -- "7"
"0000000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"8" else -- "8"
"0010000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"9" else -- "9"
"0001000" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"a" else -- "A"
"0000011" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"b" else -- "b"
"1000110" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"c" else -- "C"
"0100001" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"d" else -- "d"
"0000110" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"e" else -- "E"
"0001110" when APSS='0' and NUMEN='1' and NUMBER(15 downto 12)=X"f" else -- "F"
"1000111" when APSS='1' and TCNT="010" else -- "["
"1100110" when APSS='1' and TCNT="011" else -- "["
"1010110" when APSS='1' and TCNT="100" else -- "["
"1001110" when APSS='1' and TCNT="101" else -- "["
"1000110" when APSS='1' else -- "["
"1111111";
HEX3_DP<='1';
HEX2_D<= "0000000" when APSS='0' and NUMEN='0' and MZMODE='0' else -- "8"
"1000000" when APSS='0' and NUMEN='0' and MZMODE='1' and DMODE='0' else -- "0"
"0100100" when APSS='0' and NUMEN='0' and MZMODE='1' and DMODE='1' else -- "2"
"1000000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"0" else -- "0"
"1111001" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"1" else -- "1"
"0100100" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"2" else -- "2"
"0110000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"3" else -- "3"
"0011001" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"4" else -- "4"
"0010010" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"5" else -- "5"
"0000010" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"6" else -- "6"
"1011000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"7" else -- "7"
"0000000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"8" else -- "8"
"0010000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"9" else -- "9"
"0001000" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"a" else -- "A"
"0000011" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"b" else -- "b"
"1000110" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"c" else -- "C"
"0100001" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"d" else -- "d"
"0000110" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"e" else -- "E"
"0001110" when APSS='0' and NUMEN='1' and NUMBER(11 downto 8)=X"f" else -- "F"
"1111110" when APSS='1' and TCNT="110" else -- "~"
"1110111" when APSS='1' and TCNT="001" else -- "_"
"1110110" when APSS='1' else -- "="
"1111111";
HEX2_DP<='1';
HEX1_D<= "1000000" when APSS='0' and NUMEN='0' else -- "0"
"1000000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"0" else -- "0"
"1111001" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"1" else -- "1"
"0100100" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"2" else -- "2"
"0110000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"3" else -- "3"
"0011001" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"4" else -- "4"
"0010010" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"5" else -- "5"
"0000010" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"6" else -- "6"
"1011000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"7" else -- "7"
"0000000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"8" else -- "8"
"0010000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"9" else -- "9"
"0001000" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"a" else -- "A"
"0000011" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"b" else -- "b"
"1000110" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"c" else -- "C"
"0100001" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"d" else -- "d"
"0000110" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"e" else -- "E"
"0001110" when APSS='0' and NUMEN='1' and NUMBER(7 downto 4)=X"f" else -- "F"
"1111110" when APSS='1' and TCNT="001" else -- "~"
"1110111" when APSS='1' and TCNT="110" else -- "_"
"1110110" when APSS='1' else -- "="
"1111111";
HEX1_DP<='1';
HEX0_D<= "0000011" when APSS='0' and NUMEN='0' and MZMODE='0' else -- "b"
"1000000" when APSS='0' and NUMEN='0' and MZMODE='1' else -- "0"
"1000000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"0" else -- "0"
"1111001" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"1" else -- "1"
"0100100" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"2" else -- "2"
"0110000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"3" else -- "3"
"0011001" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"4" else -- "4"
"0010010" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"5" else -- "5"
"0000010" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"6" else -- "6"
"1011000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"7" else -- "7"
"0000000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"8" else -- "8"
"0010000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"9" else -- "9"
"0001000" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"a" else -- "A"
"0000011" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"b" else -- "b"
"1000110" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"c" else -- "C"
"0100001" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"d" else -- "d"
"0000110" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"e" else -- "E"
"0001110" when APSS='0' and NUMEN='1' and NUMBER(3 downto 0)=X"f" else -- "F"
"1111000" when APSS='1' and TCNT="010" else
"1110100" when APSS='1' and TCNT="011" else
"1110010" when APSS='1' and TCNT="100" else
"1110001" when APSS='1' and TCNT="101" else
"1110000" when APSS='1' else -- "]"
"1111111";
HEX0_DP<='0' when NUMEN='0' and DMODE='1' else '1';
process( SCLK ) begin
if SCLK'event and SCLK='1' then
if DCNT="0011100010000" then
DCNT<=(others=>'0');
if FF=REW then
TCNT<="000";
elsif FF='1' and REW='0' then
if TCNT="110" then
TCNT<="001";
else
TCNT<=TCNT+'1';
end if;
elsif REW='1' and FF='0' then
if TCNT(2 downto 1)="00" then
TCNT<="110";
else
TCNT<=TCNT-'1';
end if;
end if;
else
DCNT<=DCNT+'1';
end if;
end if;
end process;
end RTL;