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.metadata
.dm
.gradle
/Releases
/.nb-gradle/
*.bin
*.dmp
*.elf
*.lss
*.map
*.rpt
*.srec
*.swp
*.zpu
*.log
*.done
*.smsg
*.summary
*.jdi
*.pin
*.out.sdc
*.sof
*.sld
*.rbf
*.qws
*.sav
*.pof
*.qdf
*.srf
c5_pin_model_dump.txt
build/db/
build/incremental_db/
build/output_files/
build/simulation/
software/apps/*/*_obj/
software/zputa/zpu_obj/
software/iocp/iocp_obj/
software/build/
old/
*/old/
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nohup.out
cpu/sav
build/.qsys_edit/
build/A-Hdrive
build/ADV7123.vhd
build/ADV7123_TEST.qpf
build/ADV7123_TEST.qsf
build/Clock_50to100.BAK.vhd
build/KEY_TEST.qpf
build/KEY_TEST.qsf
build/KEY_TEST.v
build/Makefile.1306
build/audio_shifter.v
build/audio_top.v
build/constraints.sdc
build/ddr2_sodimm.qpf
build/ddr2_sodimm.qpf.v1
build/ddr2_sodimm.qsf
build/ddr2_sodimm.qsf.v1
build/ledwater.qpf
build/ledwater.qsf
build/ledwater.v
build/mypll.cmp
build/mypll.qip
build/mypll.vhd
build/serial.qpf
build/serial.qsf
build/serial.v
build/serv_req_info.txt
build/template.qsf
build/unsaved.qsys
build/unsaved.sopcinfo
build/unsaved/
devices/sysbus/TCPU/
tools/Master0.z80
tools/Master1.z80
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# Sharp MZ Series Personal and Business Computer Emulation
<br>
This project aims to provide full hardware emulation (along with extensions) of the Sharp MZ Series Computers.
Written by Philip Smart, 2018 for the Terasic DE10 Nano board under the MiSTer framework.
The initial version is based on the Terasic DE10 Nano board and hosted under the [MiSTer_Devel](https://github.com/MiSTer_Devel) project using the HPS processor for UI operations. Work is currently under way to embed the ZPU Evo into the design to act as the UI processor such that the emulation can be hosted on different hardware as needed.
Please consult my [GitHub](https://pdsmart.github.io) website for more upto date information.
The following emulations have been written:
This project aims to provide full emulation (along with extensions) of the Sharp MZ Series Computers.
The following emulations have been written
- MZ80K
- MZ80C
- MZ1200
- MZ80A
- MZ700
| Emulator | Status | | | Emulator | Status |
| -------- | ------ | --- | -------- | ------ |
| MZ80K | Developed | | | MZ80C | Developed |
| MZ1200 | Developed | | | MZ80A | Developed |
| MZ700 | Developed | | | MZ80B | Developed |
| MZ2000 | Partially Developed | | | MZ800 | Under development |
and the following are under development:
- MZ800
- MZ80B
- MZ2000
<br>
The current version of the emulator provides:
The current emulations provide:
| 48K RAM for MZ80K,C,1200,A |
| 64K RAM for MZ700, MZ80B |
| Hardware Tape Read/Write with selectable 1x - 32x Fast Mode |
| APSS Tape Drive for the MZ80B/MZ2000 - Fully automated APSS using the Menu Queue system. |
| Turbo Mode 1x - 32x (ie. 112MHz for MZ700) |
| Programmable Character Generator (PCG-8000/PCG-1200) |
| 40x25, 80x25 Mono and Colour Display Modes |
| 320x200, 640x200 8 Colour Bit addressed Graphics |
| VGA Scaling |
| Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type. |
| i8253 mono audio or Tape audio |
- 48K RAM for MZ80K,C,1200,A
- 64K RAM for MZ700
- Hardware Tape Read/Write with selectable 1x - 32x Fast Mode
- Turbo Mode 1x - 32x (ie. 112MHz for MZ700)
- Programmable Character Generator (PCG-8000/PCG-1200)
- 40x25, 80x25 Mono and Colour Display Modes
- 320x200, 640x200 8 Colour Bit addressed Graphics
- Updateable Monitor Rom, CGRom, Keymap, User Rom, FDC Rom per Emulation type.
- i8253 mono audio
### Enhancements in test/under development
### Enhancements in test/under development:
- Floppy Disk Drive/Controller 5.25"
- Quick Disk Controller
- Dual digital Joystick Input (MZ700)
| Floppy Disk Drive/Controller 5.25" |
| Quick Disk Controller |
| Dual digital Joystick Input (MZ700) |
### Known Issues
- Tape Write isn’t working correctly, I made some structural changes resulting in it no longer working, so this needs to be resolved.
- Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A.
- HDMI needs to be re-enabled in the design.
- The Aspect Ratio/Scandoubler options aren’t working on the VGA output.
| Keyboard mappings could be better, especially for the MZ1200 which is the Japanese version of the MZ80A. |
| HDMI needs to be re-enabled in the design. |
| Need to complete the status frame buffer, used by the ZPU I/O processor for status information display - not critical to use. |
## Installation
1. Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide
2. Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:-
scp SharpMZ_MiSTer/releases/SharpMZ_\<date\>.rbf root@\<de10 ip address\>/media/fat/SharpMZ.rbf
Target name can be anything you like ending with .rbf
3. Make a SharpMZ directory on the SD card, ie:
|1. |Follow the Setup Guide to create a new SD boot disk. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide |
|2. |Copy across to the SD (via scp or mount the SD under Windows/Linux and use local copy commands) the latest RBF file from the releases folder, ie:- |
| |scp SharpMZ_MiSTer/releases/SharpMZ_\<date\>.rbf root@\<de10 ip address\>/media/fat/SharpMZ.rbf |
| |Target name can be anything you like ending with .rbf |
|3. |Make a SharpMZ directory on the SD card, ie: |
| |ssh root@\<de10 ip address\> |
| |mkdir /media/fat/SharpMZ |
|4. |Copy any Rom Files, MZF Tape Files, DSK files across to the new directory, ie: |
| |scp \*.mzf root@\<de10 ip address\>:/media/fat/SharpMZ/ |
|5. |Start the MiSTer menu (ie. press the DE10 reset button if it is not showing). |
|6. |Select the SharpMZ core (or whatever name you called it). |
|7. |The emulator will boot into an MZ80K model with the SP-1002 monitor. |
|8. |Press F12 to change the configuration, select Save Config to store it. |
ssh root@\<de10 ip address\>
mkdir /media/fat/SharpMZ
4. Copy any Rom Files, MZF Tape Files, DSK files across to the new directory, ie:
scp \*.mzf root@\<de10 ip address\>:/media/fat/SharpMZ/
5. Start the MiSTer menu (ie. press the DE10 reset button if it is not showing).
6. Select the SharpMZ core (or whatever name you called it).
7. The emulator will boot into an MZ80K model with the SP-1002 monitor.
8. Press F12 to change the configuration, select Save Config to store it.
## Detail
## Design Detail
### Design Summary
The idea of this design is to keep the emulation as independent of the HPS as possible (so it works standalone), only needing the HPS to set control registers,
read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
read/write tape/floppy cache ram with complete images and overlay the menu control system. The MiSTer/HPS system is an excellent base on which to host emulations, but there may be
someone wanting to port this emulator to another target such as the Xilinx Zynq 7000 (which I have also been playing with). This in theory should allow easier porting if someone
wants to port this emulator to another platform and control it with a PC (parallel port), HPS or instantiate another CPU as the menu control system.
As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
As the Cyclone V SE on the Terasic DE10 has 5.5Mbits of memory, nearly all the RAM used by the emulation is on the FPGA. The Floppy Disk Controller may use HPS memory/external
SDRAM depending on whether I decide to cache entire Floppy Disks as per the CMT unit or use the secondary SD card.
### Menu System
The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the display parameters, debugging and access to the MiSTer control menu.
The MiSTer menu system is used extensively on this design as the Front End control. It allows for loading/saving of cassettes and floppy disks, setting the machine parameters, the
display parameters, debugging and access to the MiSTer control menu.
### Tape Storage
In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved on to Floppy/Quick Disks.
In order to use the emulation seriously, you need to be able to load and save existing programs. Initially (on the original machines) this was via a CMT (tape) unit and later moved
on to Floppy/Quick Disks.
This menu controls the hardware CMT unit and has the following choices:
- Load direct to RAM
This option allows you to load an MZF format tape file (ie. 128 bytes header + code) directly into RAM. It uses the Load Address and Size stored in the header in order to correctly locate the code and also stores the header in the Cassette Work area at 10F0H. After load is completed and warm reset is made, the details of the tape are displayed on-screen. In order to run the loaded program, simply issue the correct monitor command, ie. J1200 (Jump to 1200H where 1200H is shown as the Execution Address in the tape summary).
This option allows you to load an MZF format tape file (ie. 128 bytes header + code) directly into RAM. It uses the Load Address and Size stored in the header in order to correctly
locate the code and also stores the header in the Cassette Work area at 10F0H. After load is completed and warm reset is made, the details of the tape are displayed on-screen. In
order to run the loaded program, simply issue the correct monitor command, ie. J1200 (Jump to 1200H where 1200H is shown as the Execution Address in the tape summary).
- Queue Tape
A real cassette has 1 or more programs stored on it sequentially. The emulation cache only stores 1 full program so this is a mechanism to line up multiple programs and they will be fed into the emulation cache as it becomes empty, thus simulating a real cassette.
Selecting this option presents you with a directory listing of all MZF files. Choose one per selection and it will be added to the Queue. The programs queued will be displayed on the menu.
A real cassette has 1 or more programs stored on it sequentially. The emulation cache only stores 1 full program so this is a mechanism to line up multiple programs and they will
be fed into the emulation cache as it becomes empty, thus simulating a real cassette. Selecting this option presents you with a directory listing of all MZF files. Choose one per
selection and it will be added to the Queue. The programs queued will be displayed on the menu.
For the MZ80B/MZ2000, the original tape drive was an automated APSS drive capable of searching backwards and forwards for a program. The queue emulates this by interpreting the
APSS signals, moving the queue forward and backwards as necessary. Thus is you are to use a database program or similar which has multiple volumes you need to add these into the
tape queue for the program to function correctly.
- Clear Queue
This option allows you to purge all queue entries.
- Save Tape
- <s>Save Tape</s>
This option allows you to save a program to the MiSTer SD card which is in the emulation cache. Normally the emulation would have written a program/data to tape (ie. via the BASIC ‘SAVE’ command) which in reality is stored in the emulation cache.
The tape is saved under the name given in the emulation save command (ie. in BASIC ‘SAVE “myfile”’ would result in a file called myfile.mzf being saved).
- Auto Save Tape
<s>This option allows you to save a program to the MiSTer SD card which is in the emulation cache. Normally the emulation would have written a program/data to tape (ie. via the BASIC ‘SAVE’
command) which in reality is stored in the emulation cache. The tape is saved under the name given in the emulation save command (ie. in BASIC ‘SAVE “myfile”’ would result in a file
called myfile.mzf being saved).</s>
- <s>Auto Save Tape</s>
This option allows you to auto save the emulation cache. Ie. when an emulation save completes, a flag is raised which is seen by the MiSTer program and the emulation cache is saved to SD under the name given in the emulation.
- Tape Buttons
<s>This option allows you to auto save the emulation cache. Ie. when an emulation save completes, a flag is raised which is seen by the MiSTer program and the emulation cache is saved to SD under
the name given in the emulation.</s>
- <s>Tape Buttons</s>
This option allows you to set the active Tape buttons, ie. Play, Record or Auto. Auto is a hardware mechanism to detect if the emulation is reading or writing to tape and process accordingly.
<s>This option allows you to set the active Tape buttons, ie. Play, Record or Auto. Auto is a hardware mechanism to detect if the emulation is reading or writing to tape and process accordingly.</s>
- Fast Tape Load
This option allows you to set the speed of the tape drive. On the original machines, the tape runs at 1200baud which is quite slow, so use of this option is recommended.
You can select one of: "Off", "2x", "4x", "8x", "16x", "32x"
You can select one of: "Off", "2x", "4x", "8x", "16x"
Selecting “Off” runs the tape drive at the original speed.
*NB: With the introduction of the APSS functionality, Save Tape and Auto Save Tape are redundant. When a program running on the emulation issues a save, the name is transferred through to the
MiSTer Main binary which then uses that name to create a file on the SD card.*
### Machine
The emulation emulates several Sharp MZ computers and this menu allows you to make selections accordingly.
@@ -168,25 +179,41 @@ The display on the Sharp MZ computers was originally quite simplistic. In order
This option allows you to select the display used. Normally, when a machine model is chosen, it defaults to the original display, this option allows you to override the default. The choices are:
"Mono 40x25", "Mono 80x25 ", "Colour 40x25", "Colour 80x25"
- VGA Scaling
In order to cater for various VGA monitors, this option programs the sync generator to mimic standard VGA signals. As VGA resolution is higher than the original Sharp MZ 40x25 screen (320x200 pixels), scaling occurs from the original format
upto the VGA format. The choices are:
"640x480@60Hz", "Off"
- Video
An extension to the original design was the addition of a graphics frame buffer. It is possible to blend the original display video with the graphics frame buffer. This option allows you to enable or disable the original display video (ie. if you only want graphics).
An extension to the original design was the addition of a graphics frame buffer. It is possible to blend the original display video with the graphics frame buffer. This option allows you to enable or disable the original display video (ie.
if you only want graphics).
- Graphics
There were various add-on boards made available in order to display bit addressable pixel graphics. This is my extension to the original design and as I gather information on other add-on boards, I will adapt the hardware interface so it accommodates these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
There were various add-on boards made available in order to display bit addressable pixel graphics. This is my extension to the original design and as I gather information on other add-on boards, I will adapt the hardware interface so it accommodates
these options. Please see the section below on the graphics frame buffer details if needed. This option allows you to enable or disable the display of the graphics frame buffer (which is blended with the original character based video output).
- Graphics Addr
As the emulation is catering for several Sharp MZ models in addition to adding graphics onto machines which originally didnt have graphics there can be a clash of I/O address for selecting the graphics mode and options. This option sets the default
IO address for accessing the graphics control registers.
- VRAM CPU Wait
I deviated from the original design by adding a pixel based display buffer. During the Vertical Blanking period, I expand the character based VRAM and Attribute RAM into pixels and store them in the display buffer (a double buffer technique). This consequently means that no snow/tearing will occur if the CPU accesses the VRAM/Attribute RAM during the visible display period. The original design added software waits (MZ80K) and hardware CPU wait states (MZ80A/700) to eliminate snow/tearing and due to the addition of double buffering, this is no longer needed. You can thus disable the wait states with this option and gain some speed or enable them to keep compatibility.
I deviated from the original design by adding a pixel based display buffer. During the Vertical Blanking period, I expand the character based VRAM and Attribute RAM into pixels and store them in the display buffer (a double buffer technique).
This consequently means that no snow/tearing will occur if the CPU accesses the VRAM/Attribute RAM during the visible display period. The original design added software waits (MZ80K) and hardware CPU wait states (MZ80A/700) to eliminate snow/tearing and
due to the addition of double buffering, this is no longer needed. You can thus disable the wait states with this option and gain some speed or enable them to keep compatibility.
- PCG Mode
All of the Sharp MZ computers used character generators which were hard coded in a ROM. External vendors offered add-ons to allow for a Programmable Character Generator based in RAM. This option enables the Programmable Character Generator which is compatible with the HAL PCG-8000/PCG-1200 add-ons.
- Aspect Ratio
This option is a MiSTer framework extension which converts the Aspect Ratio from 4:3 to 16:9. It doesn’t work at the moment with VGA output but should work on HDMI. Use this option to choose the desired format.
- Scandoubler
This option is a MiSTer framework extension which doubles the scan lines to widen/improve the image of older computer displays. It doesn’t work correctly with VGA output at the moment but should work on HDMI.
The choices are: "None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%"
All of the Sharp MZ computers used character generators which were hard coded in a ROM. External vendors offered add-ons to allow for a Programmable Character Generator based in RAM. This option enables the Programmable Character Generator which is
compatible with the HAL PCG-8000/PCG-1200 add-ons.
- <s>Aspect Ratio</s>
### System
This is the MiSTer main control menu which allows you to select a core, map keys etc.
<s>This option is a MiSTer framework extension which converts the Aspect Ratio from 4:3 to 16:9. It doesn’t work at the moment with VGA output but should work on HDMI. Use this option to choose the desired format.</s>
- <s>Scandoubler</s>
<s>This option is a MiSTer framework extension which doubles the scan lines to widen/improve the image of older computer displays. It doesn’t work correctly with VGA output at the moment but should work on HDMI. The choices are:<br></s>
<s>"None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%"</s>
*NB: Aspect Ratio and Scandoubler are currently disabled due to the inclusion of the VGA Scaling hardware. When HDMI output is compiled into the design in the near future they will be re-enabled.*
### Debugging
*Debugging has now been made a compile time option. If debugging logic has been enabled in the RTL and Main MiSTer binary, the debugging options below will be available.*
As you cannot easily get out a trusty Oscilloscope or write breakpoint/debug messages with an FPGA, I’ve added a debugging mode which can be used at any time without affecting the emulation (unless you choose a debug frequency in which case the emulation will run at the selected frequency).
Basically, the 8 LED’s on the main DE10 main board can display a selectable set of signals, either in auto mode (move from set to set after a fixed period) or a static set. The sample rate of the signals displayed on the LED’s is selectable from the Z80 CPU frequency down to 1Hz. You can also attach an oscilloscope onto the LED’s and thus see the waveform if a simple flicker is not sufficient. In addition, you can slow the CPU frequency down in steps from 1MHz to 1/10Hz so you have a good chance of seeing what is happening internally.
This debugging addition is also a great method of understanding the internals of a computer and seeing the Z80 in action.
@@ -249,6 +276,21 @@ To use the debug mode, press F12 to enter the MiSTer menu, then select Debug and
- MZ80B I => Not yet defined.
- MZ80B II => Not yet defined.
### System
This is the MiSTer main control menu which allows you to select a core, map keys, set bluetooth, view IP address etc.
### Control Options
The menu system presents additional control options whose function is detailed below:
| Option | Description |
| ------ | ----------- |
| Boot Reset | Perform a cold reset on the Emulator, ie. reset the FPGA and the HPS Processor |
| Reset | Reset the emulation, ie. toggle it's reset line. |
| Reload config | Reload the configuration saved previously. Any change made in these menus can be stored for future use, if additional changes are unwanted, use this option to reload your last good configuration. |
| Save config | Save the configuration to SD card. Any changes you made in the Menu system will be saved. |
| Reset config | Reset the configuration to standard defaults. |
### Graphics Frame Buffer
An addition to the original design is a 640x200/320x200 8 colour Graphics frame buffer. There were many additions to the Sharp MZ series to allow graphics (ie. MZ80B comes with standard mono graphics) display and as I don’t have detailed information of these to date, I designed my own extension with the intention of adding hardware abstraction layers at a later date to add compatibility to external vendor add-ons.
@@ -320,17 +362,29 @@ Blend Operator (00=OR ,01=AND, 10=NAND, 11=XOR). Operator to blend Character dis
For Indirect mode (Control Register bits 3/2 set to 11), a write to the Graphics RAM when mapped into CPU address space C000H – FFFFH will see the byte masked by the Red Colour Writer Register and written to the Red Bank with the same operation for Green and Blue. This allows rapid setting of a colour across the 3 banks.
## Credits
My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab and his excellent work.
Also credit to Sorgelig for his hard work in creating the MiSTer framework and design of some excellent hardware add-ons. The MiSTer framework makes it significantly easier to design/port emulations.
## Links
The Sharp MZ Series Computers were not as wide spread as Commodore, Atari or Sinclair but they had a dedicated following. Given their open design it was very easy to modify and extend applications such as the BASIC interpreters and likewise easy to add hardware extension. As such, a look round the web finds some very comprehensive User Groups with invaluable resources. If you need manuals, programs, information then please look (for starters) at the following sites:
- https://www.eaw.app/
- https://original.sharpmz.org/
- https://www.sharpmz.no/
- https://mz-80a.com
- http://www.sharpusersclub.org/
- http://www.scav.cz/uvod.htm (use chrome to auto translate Czech)
## Credits
My original intention was to port the MZ80C Emulator written by Nibbles Lab https://github.com/NibblesLab/mz80c_de0 to the Terasic DE10 Nano. After spending some time analyzing it and trying to remove the NIOSII dependency, I discovered the MISTer project, at that point I decided upon writing my own emulation. Consequently some ideas in this code will have originated from Nibbles Lab and the i8253/Keymatrix modules were adapted to work in this implementation. Thus due credit to Nibbles Lab and his excellent work.
Also credit to Sorgelig for his hard work in creating the MiSTer framework and design of some excellent hardware add-ons. The MiSTer framework makes it significantly easier to design/port emulations.
Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. All 3rd party software, to my knowledge and research, is open source and freely useable, if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.
## Licenses
This design, hardware and software, is licensed under the GNU Public Licence v3.
### The Gnu Public License v3
The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.

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@@ -174,146 +174,146 @@ component sharpmz
);
end component;
component STORM_SoC
port (
-- Global Control --
CLK_I : in std_logic;
RST_I : in std_logic;
-- General purpose (debug) UART --
UART0_RXD_I : in std_logic;
UART0_TXD_O : out std_logic;
-- System Control --
START_I : in std_logic; -- low active
BOOT_CONFIG_I : in std_logic_vector(03 downto 0); -- low active
LED_BAR_O : out std_logic_vector(07 downto 0);
-- GP Input Pins --
GP_INPUT_I : in std_logic_vector(07 downto 0);
-- GP Output Pins --
GP_OUTPUT_O : out std_logic_vector(07 downto 0);
-- I²C Port --
I2C_SCL_IO : inout std_logic;
I2C_SDA_IO : inout std_logic;
-- SPI Port 0 [3 devices] --
SPI_P0_CLK_O : out std_logic;
SPI_P0_MISO_I : in std_logic;
SPI_P0_MOSI_O : out std_logic;
SPI_P0_CS_O : out std_logic_vector(02 downto 0);
-- SPI Port 1 [3 devices] --
SPI_P1_CLK_O : out std_logic;
SPI_P1_MISO_I : in std_logic;
SPI_P1_MOSI_O : out std_logic;
SPI_P1_CS_O : out std_logic_vector(02 downto 0);
-- SPI Port 2 [2 devices] --
SPI_P2_CLK_O : out std_logic;
SPI_P2_MISO_I : in std_logic;
SPI_P2_MOSI_O : out std_logic;
SPI_P2_CS_O : out std_logic_vector(01 downto 0);
-- PWM Port 0 --
-- PWM0_PORT_O : out std_logic_vector(07 downto 0)
-- IOCTL Bus --
IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA.
IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA.
IOCTL_CLK : out std_logic; -- I/O Clock.
IOCTL_WR : out std_logic; -- Write Enable to FPGA.
IOCTL_RD : out std_logic; -- Read Enable from FPGA.
IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus.
IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus.
IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
IOCTL_DIN : in std_logic_vector(31 downto 0) -- Data to be read into HPS.
-- -- SDRAM Interface --
-- SDRAM_CLK_O : out std_logic;
-- SDRAM_CSN_O : out std_logic;
-- SDRAM_CKE_O : out std_logic;
-- SDRAM_RASN_O : out std_logic;
-- SDRAM_CASN_O : out std_logic;
-- SDRAM_WEN_O : out std_logic;
-- SDRAM_DQM_O : out std_logic_vector(01 downto 0);
-- SDRAM_BA_O : out std_logic_vector(01 downto 0);
-- SDRAM_ADR_O : out std_logic_vector(11 downto 0);
-- SDRAM_DAT_IO : inout std_logic_vector(15 downto 0)
);
end component;
component neo430
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := false;-- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := true; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- gpio --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(02 downto 0); -- pwm channels
-- serial com --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- IOCTL Bus --
ioctl_download : out std_logic; -- Downloading to FPGA.
ioctl_upload : out std_logic; -- Uploading from FPGA.
ioctl_clk : out std_logic; -- I/O Clock.
ioctl_wr : out std_logic; -- Write Enable to FPGA.
ioctl_rd : out std_logic; -- Read Enable from FPGA.
ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus.
ioctl_select : out std_logic; -- Enable CFU control over ioctl bus.
ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
ioctl_dout : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
ioctl_din : in std_logic_vector(31 downto 0); -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_dat_i : in std_logic_vector(31 downto 0); -- read data
wb_dat_o : out std_logic_vector(31 downto 0); -- write data
wb_we_o : out std_logic; -- read/write
wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_logic; -- strobe
wb_cyc_o : out std_logic; -- valid cycle
wb_ack_i : in std_logic; -- transfer acknowledge
-- interrupts --
irq_i : in std_logic; -- external interrupt request line
irq_ack_o : out std_logic -- external interrupt request acknowledge
);
end component;
--component STORM_SoC
-- port (
-- -- Global Control --
-- CLK_I : in std_logic;
-- RST_I : in std_logic;
--
-- -- General purpose (debug) UART --
-- UART0_RXD_I : in std_logic;
-- UART0_TXD_O : out std_logic;
--
-- -- System Control --
-- START_I : in std_logic; -- low active
-- BOOT_CONFIG_I : in std_logic_vector(03 downto 0); -- low active
-- LED_BAR_O : out std_logic_vector(07 downto 0);
--
-- -- GP Input Pins --
-- GP_INPUT_I : in std_logic_vector(07 downto 0);
--
-- -- GP Output Pins --
-- GP_OUTPUT_O : out std_logic_vector(07 downto 0);
--
-- -- I²C Port --
-- I2C_SCL_IO : inout std_logic;
-- I2C_SDA_IO : inout std_logic;
--
-- -- SPI Port 0 [3 devices] --
-- SPI_P0_CLK_O : out std_logic;
-- SPI_P0_MISO_I : in std_logic;
-- SPI_P0_MOSI_O : out std_logic;
-- SPI_P0_CS_O : out std_logic_vector(02 downto 0);
--
-- -- SPI Port 1 [3 devices] --
-- SPI_P1_CLK_O : out std_logic;
-- SPI_P1_MISO_I : in std_logic;
-- SPI_P1_MOSI_O : out std_logic;
-- SPI_P1_CS_O : out std_logic_vector(02 downto 0);
--
-- -- SPI Port 2 [2 devices] --
-- SPI_P2_CLK_O : out std_logic;
-- SPI_P2_MISO_I : in std_logic;
-- SPI_P2_MOSI_O : out std_logic;
-- SPI_P2_CS_O : out std_logic_vector(01 downto 0);
--
-- -- PWM Port 0 --
---- PWM0_PORT_O : out std_logic_vector(07 downto 0)
--
-- -- IOCTL Bus --
-- IOCTL_DOWNLOAD : out std_logic; -- Downloading to FPGA.
-- IOCTL_UPLOAD : out std_logic; -- Uploading from FPGA.
-- IOCTL_CLK : out std_logic; -- I/O Clock.
-- IOCTL_WR : out std_logic; -- Write Enable to FPGA.
-- IOCTL_RD : out std_logic; -- Read Enable from FPGA.
-- IOCTL_SENSE : in std_logic; -- Sense to see if HPS accessing ioctl bus.
-- IOCTL_SELECT : out std_logic; -- Enable IOP control over ioctl bus.
-- IOCTL_ADDR : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
-- IOCTL_DOUT : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
-- IOCTL_DIN : in std_logic_vector(31 downto 0) -- Data to be read into HPS.
--
---- -- SDRAM Interface --
---- SDRAM_CLK_O : out std_logic;
---- SDRAM_CSN_O : out std_logic;
---- SDRAM_CKE_O : out std_logic;
---- SDRAM_RASN_O : out std_logic;
---- SDRAM_CASN_O : out std_logic;
---- SDRAM_WEN_O : out std_logic;
---- SDRAM_DQM_O : out std_logic_vector(01 downto 0);
---- SDRAM_BA_O : out std_logic_vector(01 downto 0);
---- SDRAM_ADR_O : out std_logic_vector(11 downto 0);
---- SDRAM_DAT_IO : inout std_logic_vector(15 downto 0)
-- );
--end component;
--
--component neo430
-- generic (
-- -- general configuration --
-- CLOCK_SPEED : natural := 100000000; -- main clock in Hz
-- IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
-- DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- -- additional configuration --
-- USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- -- module configuration --
-- DADD_USE : boolean := true; -- implement DADD instruction? (default=true)
-- MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
-- WB32_USE : boolean := false;-- implement WB32 unit? (default=true)
-- WDT_USE : boolean := true; -- implement WDT? (default=true)
-- GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
-- TIMER_USE : boolean := true; -- implement timer? (default=true)
-- UART_USE : boolean := true; -- implement UART? (default=true)
-- CRC_USE : boolean := true; -- implement CRC unit? (default=true)
-- CFU_USE : boolean := true; -- implement custom functions unit? (default=false)
-- PWM_USE : boolean := true; -- implement PWM controller?
-- TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
-- SPI_USE : boolean := true; -- implement SPI? (default=true)
-- -- boot configuration --
-- BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
-- IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
-- );
-- port (
-- -- global control --
-- clk_i : in std_logic; -- global clock, rising edge
-- rst_i : in std_logic; -- global reset, async, low-active
-- -- gpio --
-- gpio_o : out std_logic_vector(15 downto 0); -- parallel output
-- gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- -- pwm channels --
-- pwm_o : out std_logic_vector(02 downto 0); -- pwm channels
-- -- serial com --
-- uart_txd_o : out std_logic; -- UART send data
-- uart_rxd_i : in std_logic; -- UART receive data
-- spi_sclk_o : out std_logic; -- serial clock line
-- spi_mosi_o : out std_logic; -- serial data line out
-- spi_miso_i : in std_logic; -- serial data line in
-- spi_cs_o : out std_logic_vector(07 downto 0); -- SPI CS 0..7
-- twi_sda_io : inout std_logic; -- twi serial data line
-- twi_scl_io : inout std_logic; -- twi serial clock line
-- -- IOCTL Bus --
-- ioctl_download : out std_logic; -- Downloading to FPGA.
-- ioctl_upload : out std_logic; -- Uploading from FPGA.
-- ioctl_clk : out std_logic; -- I/O Clock.
-- ioctl_wr : out std_logic; -- Write Enable to FPGA.
-- ioctl_rd : out std_logic; -- Read Enable from FPGA.
-- ioctl_sense : in std_logic; -- Sense to see if HPS accessing ioctl bus.
-- ioctl_select : out std_logic; -- Enable CFU control over ioctl bus.
-- ioctl_addr : out std_logic_vector(24 downto 0); -- Address in FPGA to write into.
-- ioctl_dout : out std_logic_vector(31 downto 0); -- Data to be written into FPGA.
-- ioctl_din : in std_logic_vector(31 downto 0); -- Data to be read into HPS.
-- -- 32-bit wishbone interface --
-- wb_adr_o : out std_logic_vector(31 downto 0); -- address
-- wb_dat_i : in std_logic_vector(31 downto 0); -- read data
-- wb_dat_o : out std_logic_vector(31 downto 0); -- write data
-- wb_we_o : out std_logic; -- read/write
-- wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
-- wb_stb_o : out std_logic; -- strobe
-- wb_cyc_o : out std_logic; -- valid cycle
-- wb_ack_i : in std_logic; -- transfer acknowledge
-- -- interrupts --
-- irq_i : in std_logic; -- external interrupt request line
-- irq_ack_o : out std_logic -- external interrupt request acknowledge
-- );
--end component;
begin
@@ -356,156 +356,156 @@ begin
IOCTL_DIN => CON_IOCTL_DIN -- Data to be read into HPS.
);
-- If enabled, instantiate the local STORM IO processor to provide IO and user interface services.
--
STORM_ENABLED: if STORM_ENABLE = 1 generate
STORM_0: STORM_SoC
port map (
-- Global Control --
CLK_I => CON_CLKIOP, -- global clock, rising edge
RST_I => (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
-- -- If enabled, instantiate the local STORM IO processor to provide IO and user interface services.
-- --
-- STORM_ENABLED: if STORM_ENABLE = 1 generate
-- STORM_0: STORM_SoC
-- port map (
-- -- Global Control --
-- CLK_I => CON_CLKIOP, -- global clock, rising edge
-- RST_I => (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
--
-- -- General purpose (debug) UART --
-- UART0_RXD_I => CON_UART_RX,
-- UART0_TXD_O => CON_UART_TX,
--
-- -- System Control --
-- START_I => '1',
-- BOOT_CONFIG_I => "0000",
-- LED_BAR_O => open,
--
-- -- GP Input Pins --
-- GP_INPUT_I => x"FF",
--
-- -- GP Output Pins --
-- GP_OUTPUT_O => open,
--
-- -- I²C Port --
-- I2C_SCL_IO => open,
-- I2C_SDA_IO => open,
--
-- -- SPI Port 0 [3 devices] --
-- SPI_P0_CLK_O => CON_SPI_SCLK,
-- SPI_P0_MISO_I => CON_SPI_MISO,
-- SPI_P0_MOSI_O => CON_SPI_MOSI,
-- SPI_P0_CS_O => CON_SPI_CS(2 downto 0),
--
-- -- SPI Port 1 [3 devices] --
-- SPI_P1_CLK_O => open,
-- SPI_P1_MISO_I => '0',
-- SPI_P1_MOSI_O => open,
-- SPI_P1_CS_O => open,
--
-- -- SPI Port 2 [2 devices] --
-- SPI_P2_CLK_O => open,
-- SPI_P2_MISO_I => '0',
-- SPI_P2_MOSI_O => open,
-- SPI_P2_CS_O => open,
--
-- -- PWM Port 0 --
---- PWM0_PORT_O => open
--
-- -- IOCTL Bus --
-- IOCTL_DOWNLOAD => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
-- IOCTL_UPLOAD => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
-- IOCTL_CLK => IOP_IOCTL_CLK, -- I/O Clock.
-- IOCTL_WR => IOP_IOCTL_WR, -- Write Enable to FPGA.
-- IOCTL_RD => IOP_IOCTL_RD, -- Read Enable from FPGA.
-- IOCTL_SENSE => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
-- IOCTL_SELECT => IOP_IOCTL_SELECT, -- Enable IOP control over ioctl bus.
-- IOCTL_ADDR => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
-- IOCTL_DOUT => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
-- IOCTL_DIN => IOP_IOCTL_DIN -- Data to be read into HPS.
--
---- -- SDRAM Interface --
---- SDRAM_CLK_O => open,
---- SDRAM_CSN_O => open,
---- SDRAM_CKE_O => open,
---- SDRAM_RASN_O => open,
---- SDRAM_CASN_O => open,
---- SDRAM_WEN_O => open,
---- SDRAM_DQM_O => open,
---- SDRAM_BA_O => open,
---- SDRAM_ADR_O => open,
---- SDRAM_DAT_IO => open
-- );
-- end generate;
--
-- -- If enabled, instantiate the local IO processor to provide IO and user interface services.
-- --
-- NEO430_ENABLED: if NEO_ENABLE = 1 generate
-- NEO430_0 : neo430
-- generic map (
-- -- general configuration --
-- CLOCK_SPEED => 64000000, -- main clock in Hz
-- IMEM_SIZE => 48*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
-- DMEM_SIZE => 12*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- -- additional configuration --
-- USER_CODE => x"0000", -- custom user code
-- -- module configuration --
-- DADD_USE => true, -- implement DADD instruction? (default=true)
-- MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
-- WB32_USE => false, -- implement WB32 unit? (default=true)
-- WDT_USE => true, -- implement WDT? (default=true)
-- GPIO_USE => true, -- implement GPIO unit? (default=true)
-- TIMER_USE => true, -- implement timer? (default=true)
-- UART_USE => true, -- implement UART? (default=true)
-- CRC_USE => false, -- implement CRC unit? (default=true)
-- CFU_USE => false, -- implement custom functions unit? (default=false)
-- PWM_USE => true, -- implement PWM controller?
-- TWI_USE => false, -- implement two wire serial interface? (default=true)
-- SPI_USE => true, -- implement SPI? (default=true)
-- -- boot configuration --
-- BOOTLD_USE => true, -- implement and use bootloader? (default=true)
-- IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
-- )
-- port map (
-- -- global control --
-- clk_i => CON_CLKIOP, -- global clock, rising edge
-- rst_i => not (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
-- -- gpio --
-- gpio_o => open, -- parallel output
-- gpio_i => X"0000", -- parallel input
-- -- pwm channels --
-- pwm_o => open, -- pwm channels
-- -- serial com --
-- uart_txd_o => CON_UART_TX, -- UART send data
-- uart_rxd_i => CON_UART_RX, -- UART receive data
-- spi_sclk_o => CON_SPI_SCLK, -- serial clock line
-- spi_mosi_o => CON_SPI_MOSI, -- serial data line out
-- spi_miso_i => CON_SPI_MISO, -- serial data line in
-- spi_cs_o => CON_SPI_CS, -- SPI CS 0..7
-- twi_sda_io => open, -- twi serial data line
-- twi_scl_io => open, -- twi serial clock line
-- -- IOCTL Bus --
-- ioctl_download => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
-- ioctl_upload => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
-- ioctl_clk => IOP_IOCTL_CLK, -- I/O Clock.
-- ioctl_wr => IOP_IOCTL_WR, -- Write Enable to FPGA.
-- ioctl_rd => IOP_IOCTL_RD, -- Read Enable from FPGA.
-- ioctl_sense => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
-- ioctl_select => IOP_IOCTL_SELECT, -- Enable CFU control over ioctl bus.
-- ioctl_addr => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
-- ioctl_dout => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
-- ioctl_din => IOP_IOCTL_DIN, -- Data to be read into HPS.
-- -- 32-bit wishbone interface --
-- wb_adr_o => open, -- address
-- wb_dat_i => (others => '0'), -- read data
-- wb_dat_o => open, -- write data
-- wb_we_o => open, -- read/write
-- wb_sel_o => open, -- byte enable
-- wb_stb_o => open, -- strobe
-- wb_cyc_o => open, -- valid cycle
-- wb_ack_i => '0', -- transfer acknowledge
-- -- interrupts --
-- irq_i => '0', -- external interrupt request line
-- irq_ack_o => open -- external interrupt request acknowledge
-- );
-- end generate;
-- General purpose (debug) UART --
UART0_RXD_I => CON_UART_RX,
UART0_TXD_O => CON_UART_TX,
-- System Control --
START_I => '1',
BOOT_CONFIG_I => "0000",
LED_BAR_O => open,
-- GP Input Pins --
GP_INPUT_I => x"FF",
-- GP Output Pins --
GP_OUTPUT_O => open,
-- I²C Port --
I2C_SCL_IO => open,
I2C_SDA_IO => open,
-- SPI Port 0 [3 devices] --
SPI_P0_CLK_O => CON_SPI_SCLK,
SPI_P0_MISO_I => CON_SPI_MISO,
SPI_P0_MOSI_O => CON_SPI_MOSI,
SPI_P0_CS_O => CON_SPI_CS(2 downto 0),
-- SPI Port 1 [3 devices] --
SPI_P1_CLK_O => open,
SPI_P1_MISO_I => '0',
SPI_P1_MOSI_O => open,
SPI_P1_CS_O => open,
-- SPI Port 2 [2 devices] --
SPI_P2_CLK_O => open,
SPI_P2_MISO_I => '0',
SPI_P2_MOSI_O => open,
SPI_P2_CS_O => open,
-- PWM Port 0 --
-- PWM0_PORT_O => open
-- IOCTL Bus --
IOCTL_DOWNLOAD => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
IOCTL_UPLOAD => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
IOCTL_CLK => IOP_IOCTL_CLK, -- I/O Clock.
IOCTL_WR => IOP_IOCTL_WR, -- Write Enable to FPGA.
IOCTL_RD => IOP_IOCTL_RD, -- Read Enable from FPGA.
IOCTL_SENSE => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
IOCTL_SELECT => IOP_IOCTL_SELECT, -- Enable IOP control over ioctl bus.
IOCTL_ADDR => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
IOCTL_DOUT => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
IOCTL_DIN => IOP_IOCTL_DIN -- Data to be read into HPS.
-- -- SDRAM Interface --
-- SDRAM_CLK_O => open,
-- SDRAM_CSN_O => open,
-- SDRAM_CKE_O => open,
-- SDRAM_RASN_O => open,
-- SDRAM_CASN_O => open,
-- SDRAM_WEN_O => open,
-- SDRAM_DQM_O => open,
-- SDRAM_BA_O => open,
-- SDRAM_ADR_O => open,
-- SDRAM_DAT_IO => open
);
end generate;
-- If enabled, instantiate the local IO processor to provide IO and user interface services.
--
NEO430_ENABLED: if NEO_ENABLE = 1 generate
NEO430_0 : neo430
generic map (
-- general configuration --
CLOCK_SPEED => 64000000, -- main clock in Hz
IMEM_SIZE => 48*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => 12*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => x"0000", -- custom user code
-- module configuration --
DADD_USE => true, -- implement DADD instruction? (default=true)
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => false, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WDT? (default=true)
GPIO_USE => true, -- implement GPIO unit? (default=true)
TIMER_USE => true, -- implement timer? (default=true)
UART_USE => true, -- implement UART? (default=true)
CRC_USE => false, -- implement CRC unit? (default=true)
CFU_USE => false, -- implement custom functions unit? (default=false)
PWM_USE => true, -- implement PWM controller?
TWI_USE => false, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
-- boot configuration --
BOOTLD_USE => true, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => CON_CLKIOP, -- global clock, rising edge
rst_i => not (CON_COLD_RESET or CON_WARM_RESET), -- global reset, async
-- gpio --
gpio_o => open, -- parallel output
gpio_i => X"0000", -- parallel input
-- pwm channels --
pwm_o => open, -- pwm channels
-- serial com --
uart_txd_o => CON_UART_TX, -- UART send data
uart_rxd_i => CON_UART_RX, -- UART receive data
spi_sclk_o => CON_SPI_SCLK, -- serial clock line
spi_mosi_o => CON_SPI_MOSI, -- serial data line out
spi_miso_i => CON_SPI_MISO, -- serial data line in
spi_cs_o => CON_SPI_CS, -- SPI CS 0..7
twi_sda_io => open, -- twi serial data line
twi_scl_io => open, -- twi serial clock line
-- IOCTL Bus --
ioctl_download => IOP_IOCTL_DOWNLOAD, -- Downloading to FPGA.
ioctl_upload => IOP_IOCTL_UPLOAD, -- Uploading from FPGA.
ioctl_clk => IOP_IOCTL_CLK, -- I/O Clock.
ioctl_wr => IOP_IOCTL_WR, -- Write Enable to FPGA.
ioctl_rd => IOP_IOCTL_RD, -- Read Enable from FPGA.
ioctl_sense => IOP_IOCTL_SENSE, -- Sense to see if HPS accessing ioctl bus.
ioctl_select => IOP_IOCTL_SELECT, -- Enable CFU control over ioctl bus.
ioctl_addr => IOP_IOCTL_ADDR, -- Address in FPGA to write into.
ioctl_dout => IOP_IOCTL_DOUT, -- Data to be written into FPGA.
ioctl_din => IOP_IOCTL_DIN, -- Data to be read into HPS.
-- 32-bit wishbone interface --
wb_adr_o => open, -- address
wb_dat_i => (others => '0'), -- read data
wb_dat_o => open, -- write data
wb_we_o => open, -- read/write
wb_sel_o => open, -- byte enable
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- interrupts --
irq_i => '0', -- external interrupt request line
irq_ack_o => open -- external interrupt request acknowledge
);
end generate;
-- If the IO Processor is disabled, set the signals to inactive.
--
IOP_DISABLED: if NEO_ENABLE = 0 and STORM_ENABLE = 0 generate
-- -- If the IO Processor is disabled, set the signals to inactive.
-- --
-- IOP_DISABLED: if NEO_ENABLE = 0 and STORM_ENABLE = 0 generate
IOP_IOCTL_DOWNLOAD <= '0';
IOP_IOCTL_UPLOAD <= '0';
IOP_IOCTL_CLK <= '0';
@@ -516,7 +516,7 @@ begin
--IOP_IOCTL_DIN => open;
--IOP_IOCTL_SENSE => open;
IOP_IOCTL_SELECT <= '0';
end generate;
-- end generate;
-- Assign signals from the emu onto local wires.
--

4
build_id.v
View File

@@ -1,2 +1,2 @@
`define BUILD_DATE "190107"
`define BUILD_TIME "222840"
`define BUILD_DATE "200430"
`define BUILD_TIME "002036"

4
clean.sh
View File

@@ -32,6 +32,6 @@ rm -f *.cdf
rm -f *.rpt
rm -f new_rtl_netlist
rm -f old_rtl_netlist
rm -f asm/*.obj
rm -f asm/*.sym
rm -f software/asm/*.obj
rm -f software/asm/*.sym
(cd ../Main_MiSTer; make clean)

13
jtag.cdf
View File

@@ -1,13 +0,0 @@
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23I7) Path("output_files/") File("sharpmz-lite.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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releases/MiSTer_SharpMZ_20200430 Executable file
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sharpmz-lite-div.qws
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76
sharpmz-lite.qsf
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@@ -431,46 +431,46 @@ set_global_assignment -name VHDL_FILE mz80b/mz80b.vhd
#============================================================
# STORM
#============================================================
set_global_assignment -name VHDL_FILE storm/STORM_SoC.vhd
set_global_assignment -name VHDL_FILE storm/CPU/ALU.vhd
set_global_assignment -name VHDL_FILE storm/CPU/BARREL_SHIFTER.vhd
set_global_assignment -name VHDL_FILE storm/CPU/BUS_UNIT.vhd
set_global_assignment -name VHDL_FILE storm/CPU/CACHE.vhd
set_global_assignment -name VHDL_FILE storm/CPU/CORE.vhd
set_global_assignment -name VHDL_FILE storm/CPU/CORE_PKG.vhd
set_global_assignment -name VHDL_FILE storm/CPU/FLOW_CTRL.vhd
set_global_assignment -name VHDL_FILE storm/CPU/LOAD_STORE_UNIT.vhd
set_global_assignment -name VHDL_FILE storm/CPU/MC_SYS.vhd
set_global_assignment -name VHDL_FILE storm/CPU/MS_UNIT.vhd
set_global_assignment -name VHDL_FILE storm/CPU/MULTIPLY_UNIT.vhd
set_global_assignment -name VHDL_FILE storm/CPU/OPCODE_DECODER.vhd
set_global_assignment -name VHDL_FILE storm/CPU/OPERAND_UNIT.vhd
set_global_assignment -name VHDL_FILE storm/CPU/REG_FILE.vhd
set_global_assignment -name VHDL_FILE storm/CPU/STORM_TOP.vhd
set_global_assignment -name VHDL_FILE storm/CPU/WB_UNIT.vhd
set_global_assignment -name VHDL_FILE storm/components/boot_rom/rtl/BOOT_ROM_FILE.vhd
#set_global_assignment -name VHDL_FILE storm/STORM_SoC.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/ALU.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/BARREL_SHIFTER.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/BUS_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/CACHE.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/CORE.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/CORE_PKG.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/FLOW_CTRL.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/LOAD_STORE_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/MC_SYS.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/MS_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/MULTIPLY_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/OPCODE_DECODER.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/OPERAND_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/REG_FILE.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/STORM_TOP.vhd
#set_global_assignment -name VHDL_FILE storm/CPU/WB_UNIT.vhd
#set_global_assignment -name VHDL_FILE storm/components/boot_rom/rtl/BOOT_ROM_FILE.vhd
#set_global_assignment -name VHDL_FILE storm/components/seven_segment_controller/rtl/SEVEN_SEG_CTRL.vhd
set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2_wb.vhd
set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2.vhd
set_global_assignment -name VHDL_FILE storm/components/reset_protector/rtl/RST_PROTECT.vhd
set_global_assignment -name VHDL_FILE storm/components/timer/rtl/TIMER.vhd
set_global_assignment -name VHDL_FILE storm/components/io_controller/rtl/GP_IO_CTRL.vhd
set_global_assignment -name VHDL_FILE storm/components/vector_interrupt_controller/rtl/VIC.vhd
set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/MINI_UART.vhd
set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Txunit.vhd
set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Rxunit.vhd
set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/utils.vhd
set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_top.vhd
set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_bit_ctrl.vhd
#set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2_wb.vhd
#set_global_assignment -name VHDL_FILE storm/components/ps2core/rtl/vhdl/ps2.vhd
#set_global_assignment -name VHDL_FILE storm/components/reset_protector/rtl/RST_PROTECT.vhd
#set_global_assignment -name VHDL_FILE storm/components/timer/rtl/TIMER.vhd
#set_global_assignment -name VHDL_FILE storm/components/io_controller/rtl/GP_IO_CTRL.vhd
#set_global_assignment -name VHDL_FILE storm/components/vector_interrupt_controller/rtl/VIC.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/MINI_UART.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Txunit.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/Rxunit.vhd
#set_global_assignment -name VHDL_FILE storm/components/miniuart/rtl/vhdl/utils.vhd
#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_top.vhd
#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_byte_ctrl.vhd
#set_global_assignment -name VHDL_FILE storm/components/i2c_controller/rtl/vhdl/i2c_master_bit_ctrl.vhd
#set_global_assignment -name VHDL_FILE storm/components/pwm_controller/rtl/PWM_CTRL.vhd
set_global_assignment -name VHDL_FILE storm/components/sram_memory/rtl/MEMORY.vhd
set_global_assignment -name VHDL_FILE storm/components/ioctl/rtl/ioctl.vhd
set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_top.v
set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_defines.v
set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_clgen.v
set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_shift.v
set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/timescale.v
#set_global_assignment -name VHDL_FILE storm/components/sram_memory/rtl/MEMORY.vhd
#set_global_assignment -name VHDL_FILE storm/components/ioctl/rtl/ioctl.vhd
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_top.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_defines.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_clgen.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/spi_shift.v
#set_global_assignment -name VERILOG_FILE storm/components/spi_controller/rtl/verilog/timescale.v
#============================================================
# PLL

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sharpmz-lite.qws
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4
sharpmz.qpf
View File

@@ -18,12 +18,12 @@
#
# Quartus Prime
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
# Date created = 20:18:34 October 31, 2018
# Date created = 15:03:54 April 29, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.1"
DATE = "20:18:34 October 31, 2018"
DATE = "15:03:54 April 29, 2020"
# Revisions

3
sharpmz.qsf
View File

@@ -354,4 +354,5 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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software/asm/IPL.obj
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140
software/asm/IPL.sym
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@@ -1,140 +0,0 @@
?RDD: equ 0CFH
?RDI: equ 0AEH
BLK1: equ 1E5H
BLK2: equ 1EDH
BLK3: equ 1EFH
BOOTER: equ 23FH
BREAD: equ 47AH
BUSY: equ 421H
BUSY0: equ 42BH
BUSY1: equ 439H
BUSY2: equ 428H
CLEAR: equ 2BH
CMT: equ 6BH
CONVRT: equ 43FH
DCHK: equ 458H
DEL1M: equ 223H
DEL6: equ 21DH
DISP: equ 246H
DISP1: equ 256H
DISP2: equ 239H
DISP3: equ 24EH
DLY1M: equ 5DDH
DLY2: equ 229H
DLY60M: equ 5E4H
DLY80U: equ 5D6H
DLYT: equ 5E8H
DM1: equ 210H
DNO: equ 58AH
DNO0: equ 5C1H
DNO1: equ 5CFH
DNO10: equ 594H
DNO3: equ 5A4H
DTCK1: equ 477H
EDGE: equ 121H
EDGE1: equ 129H
EIRTN: equ 0CDH
ERMT1: equ 603H
EROM1: equ 5F8H
EROM2: equ 605H
ERR: equ 556H
ERR1: equ 559H
EXROMT: equ 5EFH
FD: equ 33CH
FDCC: equ 5FH
FR: equ 1F4H
FR1: equ 1F6H
IPLMC: equ 335H
KEYIN: equ 3DH
KEYS: equ 4DH
KEYS1: equ 4BH
KYEMES: equ 1CEH
L0211: equ 211H
L0212: equ 212H
L022B: equ 22BH
LDMSG: equ 230H
MCHECK: equ 35FH
MES1: equ 261H
MES10: equ 2B3H
MES11: equ 2BFH
MES12: equ 2D0H
MES13: equ 2DFH
MES14: equ 2EEH
MES15: equ 309H
MES16: equ 326H
MES3: equ 26FH
MES6: equ 28BH
MES8: equ 299H
MES9: equ 2A6H
MISMCH: equ 9EH
MOFF: equ 3F3H
MOT1: equ 19CH
MOTOR: equ 186H
MOTR: equ 1B1H
MOTRD: equ 1AEH
MSTOP: equ 1B5H
MTD1: equ 3D2H
MTD2: equ 3D5H
MTON: equ 3CCH
NKIN: equ 57H
NMASTE: equ 54AH
NODISK: equ 38CH
NST: equ 2H
OPEN: equ 1C2H
PLAY: equ 1D9H
RBY1: equ 136H
RBY2: equ 147H
RBY3: equ 150H
RBYTE: equ 132H
RCLB: equ 409H
RD1: equ 0B7H
RDDAT: equ 0CFH
RDINF: equ 0AEH
RE0: equ 490H
RE1: equ 4AAH
RE2: equ 4ACH
RE3: equ 4F7H
RE4: equ 4D4H
RE5: equ 4EFH
RE6: equ 4D2H
RE7: equ 519H
RE8: equ 49FH
READ1: equ 483H
READY: equ 399H
REDY0: equ 3AEH
REE: equ 51EH
RET2S: equ 0C6H
RETS: equ 4EEH
REW: equ 20BH
REX: equ 510H
RRW: equ 207H
RTAPE: equ 0DBH
RTP2: equ 0E0H
RTP3: equ 0F2H
RTP5: equ 113H
RTP6: equ 119H
SEEK: equ 3E2H
SEROMA: equ 612H
SEROMD: equ 61AH
SPDIN: equ 17AH
ST1: equ 90H
START: equ 6H
STPEIR: equ 0CAH
TM0: equ 15BH
TM1: equ 15EH
TM2: equ 161H
TM3: equ 16BH
TMARK: equ 152H
TRANS: equ 448H
TRANS1: equ 44FH
TRTN1: equ 11DH
TRYAG: equ 55FH
TRYAG1: equ 57CH
TRYAG2: equ 55CH
TRYAG3: equ 5ABH
TRYAG4: equ 5B5H
TRYAG5: equ 5B7H
WAIT: equ 52DH
WAIT0: equ 537H
WAIT1: equ 545H
WAIT2: equ 534H

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software/asm/hi-ramcheck.obj
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55
software/asm/hi-ramcheck.sym
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@@ -1,55 +0,0 @@
AMPM: equ 119BH
ATRB: equ 10F0H
BANKMSG: equ 0BF4DH
BITMSG: equ 0BF45H
BUFER: equ 11A3H
COMNT: equ 1108H
CSMDT: equ 1199H
DONEMSG: equ 0BF31H
DPRNT: equ 1194H
DSPXY: equ 1171H
DTADR: equ 1104H
EXADR: equ 1106H
FLASH: equ 118EH
FLPST: equ 118FH
FLSDT: equ 1192H
FLSST: equ 1191H
GRAM0: equ 0BE2DH
GRAM1: equ 0BE31H
GRAMINIT: equ 0BE27H
GRPHPOS: equ 0BF79H
IBUFE: equ 10F0H
KANAF: equ 1170H
LOOP: equ 0BE4BH
LOOP1: equ 0BE50H
LOOP10: equ 0BF1BH
LOOP11: equ 0BF1DH
LOOP1a: equ 0BE5CH
LOOP1b: equ 0BE62H
LOOP2: equ 0BE73H
LOOP3: equ 0BE91H
LOOP4: equ 0BEC1H
LOOP5: equ 0BEC8H
LOOP6: equ 0BEDAH
LOOP7: equ 0BEEBH
LOOP8: equ 0BEF3H
LOOP9: equ 0BF13H
MANG: equ 1173H
MEND: equ 0BF7BH
NAME: equ 10F1H
OCTV: equ 11A0H
OKCHECK: equ 0BF22H
OKMSG: equ 0BF2CH
ONTYO: equ 119FH
RATIO: equ 11A1H
SIGNON: equ 0BE3DH
SIZE: equ 1102H
SPV: equ 10F0H
START: equ 0BE00H
STRGF: equ 1193H
SUMDT: equ 1197H
SWRK: equ 119DH
TEMPW: equ 119EH
TIMFG: equ 119CH
TITLE: equ 0BF55H
TMCNT: equ 1195H

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software/asm/monitor_1Z-013A.obj
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382
software/asm/monitor_1Z-013A.sym
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@@ -1,382 +0,0 @@
ALPH1: equ 0EE2H
ALPHA: equ 0EE1H
AMPM: equ 119BH
ASC: equ 3DAH
ATBL: equ 0A92H
ATRB: equ 10F0H
AUTO3: equ 7EDH
BELL: equ 3EH
BGETL: equ 12FH
BRKEY: equ 1EH
BUFER: equ 11A3H
CKS1: equ 720H
CKS2: equ 72FH
CKS3: equ 733H
CKSUM: equ 71AH
CLEAR: equ 9D8H
CLEAR1: equ 9DAH
CLRS: equ 0E3AH
CMY0: equ 5BH
COMNT: equ 1108H
CR: equ 0E5AH
CR1: equ 0E6AH
CSMDT: equ 1199H
CTBL: equ 0EAAH
CURS1: equ 0DFFH
CURS2: equ 0E16H
CURS3: equ 0DFFH
CURS4: equ 0E23H
CURS5: equ 0E02H
CURSD: equ 0DF8H
CURSL: equ 0E25H
CURSR: equ 0E0DH
CURSU: equ 0E05H
CURSU1: equ 0E0BH
DACN1: equ 0BE3H
DACN2: equ 0BDFH
DACN3: equ 0BE0H
DEL: equ 0EF8H
DEL1: equ 0F0EH
DEL2: equ 0F1CH
DLY1: equ 759H
DLY12: equ 996H
DLY2: equ 760H
DLY3: equ 0A4AH
DLY4: equ 9A9H
DMCP: equ 6BH
DPRNT: equ 1194H
DSP01: equ 0DB9H
DSP04: equ 0DD0H
DSPXY: equ 1171H
DSWEP: equ 830H
DTADR: equ 1104H
DUM1: equ 0D88H
DUM2: equ 0D3EH
DUM3: equ 0D37H
DUMP: equ 0D29H
EDG1: equ 607H
EDG2: equ 613H
EDGE: equ 601H
EXADR: equ 1106H
FD: equ 0FFH
FD1: equ 106H
FD2: equ 102H
FLAS1: equ 97BH
FLAS2: equ 9EFH
FLASH: equ 118EH
FLKEY: equ 57EH
FLPST: equ 118FH
FLSDT: equ 1192H
FLSST: equ 1191H
GAP: equ 77AH
GAP1: equ 78EH
GAP2: equ 796H
GAP3: equ 79CH
GAPCK: equ 0FE2H
GAPCK1: equ 0FEBH
GAPCK2: equ 0FEDH
GAPCK3: equ 0FFDH
GETKY: equ 1BH
GETL: equ 3H
GETL1: equ 7EAH
GETL2: equ 818H
GETL3: equ 85BH
GETL5: equ 81DH
GETL6: equ 865H
GETLA: equ 82BH
GETLB: equ 863H
GETLC: equ 822H
GETLR: equ 87EH
GETLU: equ 876H
GETLZ: equ 86CH
GOTO: equ 0F3H
GRSTAS: equ 0DD4H
HEX: equ 3F9H
HEXIY: equ 13DH
HEXJ: equ 3E5H
HLHEX: equ 410H
HOME: equ 0E4DH
IBUFE: equ 10F0H
INST: equ 0F38H
INST2: equ 0ECAH
KANA: equ 0EEEH
KANAF: equ 1170H
KSL1: equ 9B7H
KSL2: equ 9BCH
KTBL: equ 0BEAH
KTBLC: equ 0CAAH
KTBLG: equ 0CE9H
KTBLGS: equ 0C6AH
KTBLS: equ 0C2AH
L010F: equ 10FH
L01F5: equ 1F5H
L0207: equ 207H
L0220: equ 220H
L0239: equ 239H
L023F: equ 23FH
L0255: equ 255H
L025A: equ 25AH
L02D5: equ 2D5H
L02DB: equ 2DBH
L0363: equ 363H
L0378: equ 378H
L041D: equ 41DH
L0434: equ 434H
L047D: equ 47DH
L04C2: equ 4C2H
L04C4: equ 4C4H
L0563: equ 563H
L060E: equ 60EH
L061A: equ 61AH
L066C: equ 66CH
L06AD: equ 6ADH
L06B4: equ 6B4H
L071C: equ 71CH
L0725: equ 725H
L0737: equ 737H
L0739: equ 739H
L075B: equ 75BH
L0762: equ 762H
L08F7: equ 8F7H
L092C: equ 92CH
L0968: equ 968H
L0999: equ 999H
L09AB: equ 9ABH
L0A89: equ 0A89H
L0BA0: equ 0BA0H
L0BB1: equ 0BB1H
L0D36: equ 0D36H
L0D51: equ 0D51H
L0D78: equ 0D78H
L0D7A: equ 0D7AH
L0D85: equ 0D85H
L0DA7: equ 0DA7H
L0DAD: equ 0DADH
L0DE0: equ 0DE0H
L0E2D: equ 0E2DH
L0F17: equ 0F17H
L0F33: equ 0F33H
L0F42: equ 0F42H
L0F4D: equ 0F4DH
L2HEX: equ 41FH
LETNL: equ 6H
LLPT: equ 470H
LOA0: equ 116H
LOAD: equ 111H
LONG: equ 0A1AH
LPRNT: equ 18FH
MANG: equ 1173H
MCOR: equ 7A8H
MCR1: equ 7ABH
MCR2: equ 7D4H
MCR3: equ 7D7H
MELDY: equ 30H
MLD1: equ 1D1H
MLD2: equ 205H
MLD3: equ 20DH
MLD4: equ 211H
MLD5: equ 214H
MLDS1: equ 2C4H
MLDSP: equ 2BEH
MLDST: equ 2ABH
MNTBL: equ 284H
MONIT: equ 0H
MOT1: equ 6A4H
MOT2: equ 6ABH
MOT4: equ 6B9H
MOT5: equ 6D8H
MOT7: equ 6B7H
MOT8: equ 6D0H
MOT9: equ 6D7H
MOTOR: equ 69FH
MSG: equ 15H
MSG1: equ 896H
MSGE1: equ 147H
MSGN1: equ 3FBH
MSGN2: equ 3FDH
MSGN3: equ 402H
MSGN7: equ 467H
MSGOK: equ 942H
MSGQ2: equ 9A0H
MSGQ3: equ 6E7H
MSGSV: equ 98BH
MSGX: equ 18H
MSGX1: equ 8A4H
MSGX2: equ 8A7H
MST1: equ 705H
MST3: equ 717H
MSTA: equ 44H
MSTOP: equ 700H
MSTP: equ 47H
MTBL: equ 26CH
NAME: equ 10F1H
NBRK: equ 8B8H
NCLR08: equ 9D4H
NCLR8: equ 9D5H
NL: equ 9H
NLPHL: equ 5FAH
NOADD: equ 3E2H
OCTV: equ 11A0H
ONP1: equ 21FH
ONP2: equ 22CH
ONP3: equ 265H
ONPU: equ 21CH
ONTYO: equ 119FH
OPTBL: equ 29CH
P4DE: equ 2A6H
PEN: equ 18BH
PLOT: equ 184H
PLPT: equ 176H
PMANG: equ 2F3H
PMSG: equ 1A5H
PMSG1: equ 1A8H
PPLPT: equ 17BH
PRNT: equ 12H
PRNT2: equ 967H
PRNT3: equ 96CH
PRNT4: equ 96FH
PRNT5: equ 959H
PRNTS: equ 0CH
PRNTT: equ 0FH
PRTHL: equ 3BAH
PRTHX: equ 3C3H
PTEST: equ 155H
PTRN: equ 180H
PTST0: equ 15AH
PTST1: equ 170H
QADCN: equ 0BB9H
QBEL: equ 577H
QBELD: equ 352H
QBLNK: equ 0DA6H
QBRK: equ 0A32H
QBRK1: equ 0A48H
QBRK2: equ 980H
QBRK3: equ 986H
QCLER: equ 0FD8H
QCLRFF: equ 0FDBH
QDACN: equ 0BCEH
QDINT: equ 0FDDH
QDPCT: equ 0DDCH
QDSP: equ 0DB5H
QER: equ 107H
QFLAS: equ 9FFH
QFLS: equ 9E3H
QGET: equ 8BDH
QGETL: equ 7E6H
QKEY: equ 8CAH
QKY1: equ 8D6H
QKY2: equ 8DAH
QKY5: equ 8FAH
QKY55: equ 8FBH
QKYGRP: equ 8FEH
QKYGRS: equ 909H
QKYSM: equ 8B3H
QLOAD: equ 5F0H
QLTNL: equ 90EH
QMLDY: equ 1C7H
QMODE: equ 73EH
QMSG: equ 893H
QMSGX: equ 8A1H
QNL: equ 918H
QPNT1: equ 0FB4H
QPNT2: equ 0FBFH
QPONT: equ 0FB1H
QPRNT: equ 935H
QPRT: equ 946H
QPRTS: equ 920H
QPRTT: equ 924H
QQKEY: equ 9B3H
QRDD: equ 4F8H
QRDI: equ 4D8H
QRSTR: equ 0EE5H
QRSTR1: equ 0EE6H
QSAVE: equ 0B92H
QSWEP: equ 0A50H
QTEMP: equ 2E5H
QTMR1: equ 375H
QTMR2: equ 37FH
QTMRD: equ 358H
QTMS1: equ 331H
QTMS2: equ 344H
QTMST: equ 308H
QVRFY: equ 588H
QWRD: equ 475H
QWRI: equ 436H
RATIO: equ 11A1H
RBY1: equ 630H
RBY2: equ 649H
RBY3: equ 654H
RBYTE: equ 624H
RD1: equ 4E6H
RDA: equ 1B6H
RDDAT: equ 2AH
RDINF: equ 27H
RET1: equ 4D2H
RET2: equ 554H
RET3: equ 69BH
RTAPE: equ 50EH
RTP1: equ 513H
RTP2: equ 519H
RTP3: equ 532H
RTP4: equ 554H
RTP5: equ 565H
RTP6: equ 572H
RTP7: equ 56EH
RTP8: equ 553H
RTP9: equ 574H
RYTHM: equ 2C8H
SAV1: equ 0F8EH
SAVE: equ 0F5EH
SCROL: equ 0E6DH
SG: equ 0F7H
SHORT: equ 0A01H
SIZE: equ 1102H
SLPT: equ 3D5H
SPHEX: equ 3B1H
SPV: equ 10F0H
SS: equ 0A2H
ST0: equ 70H
ST1: equ 0ADH
ST2: equ 0BBH
START: equ 4AH
STRGF: equ 1193H
SUMDT: equ 1197H
SV0: equ 0BA2H
SV1: equ 0BB5H
SWEP0: equ 0A66H
SWEP01: equ 0A64H
SWEP2: equ 0A7FH
SWEP3: equ 0A77H
SWEP6: equ 0A5FH
SWEP9: equ 0A73H
SWRK: equ 119DH
TEMPW: equ 119EH
TIMFG: equ 119CH
TIMIN: equ 38DH
TIMRD: equ 3BH
TIMST: equ 33H
TM1: equ 675H
TM2: equ 678H
TM3: equ 688H
TM4: equ 69BH
TMARK: equ 65BH
TMCNT: equ 1195H
TVF1: equ 5B2H
TVF2: equ 5B8H
TVF3: equ 5CCH
TVRFY: equ 5ADH
VERFY: equ 2DH
VRFY: equ 0FCBH
VRNS: equ 0BC5H
WBY1: equ 76DH
WBYTE: equ 767H
WRDAT: equ 24H
WRI1: equ 444H
WRI2: equ 45EH
WRI3: equ 464H
WRINF: equ 21H
WTAP1: equ 494H
WTAP2: equ 4A5H
WTAP3: equ 4D2H
WTAPE: equ 48AH
XTEMP: equ 41H

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software/asm/monitor_80c_1Z-013A.sym
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ALPH1: equ 0EE2H
ALPHA: equ 0EE1H
AMPM: equ 119BH
ASC: equ 3DAH
ATBL: equ 0A92H
ATRB: equ 10F0H
AUTO3: equ 7EDH
BELL: equ 3EH
BGETL: equ 12FH
BRKEY: equ 1EH
BUFER: equ 11A3H
CKS1: equ 720H
CKS2: equ 72FH
CKS3: equ 733H
CKSUM: equ 71AH
CLEAR: equ 9D8H
CLEAR1: equ 9DAH
CLRS: equ 0E3AH
CMY0: equ 5BH
COMNT: equ 1108H
CR: equ 0E5AH
CR1: equ 0E6AH
CSMDT: equ 1199H
CTBL: equ 0EAAH
CURS1: equ 0DFFH
CURS2: equ 0E16H
CURS3: equ 0DFFH
CURS4: equ 0E23H
CURS5: equ 0E02H
CURSD: equ 0DF8H
CURSL: equ 0E25H
CURSR: equ 0E0DH
CURSU: equ 0E05H
CURSU1: equ 0E0BH
DACN1: equ 0BE3H
DACN2: equ 0BDFH
DACN3: equ 0BE0H
DEL: equ 0EF8H
DEL1: equ 0F0EH
DEL2: equ 0F1CH
DLY1: equ 759H
DLY12: equ 996H
DLY2: equ 760H
DLY3: equ 0A4AH
DLY4: equ 9A9H
DMCP: equ 6BH
DPRNT: equ 1194H
DSP01: equ 0DB9H
DSP04: equ 0DD0H
DSPXY: equ 1171H
DSWEP: equ 830H
DTADR: equ 1104H
DUM1: equ 0D88H
DUM2: equ 0D3EH
DUM3: equ 0D37H
DUMP: equ 0D29H
EDG1: equ 607H
EDG2: equ 613H
EDGE: equ 601H
EXADR: equ 1106H
FD: equ 0FFH
FD1: equ 106H
FD2: equ 102H
FLAS1: equ 97BH
FLAS2: equ 9EFH
FLASH: equ 118EH
FLKEY: equ 57EH
FLPST: equ 118FH
FLSDT: equ 1192H
FLSST: equ 1191H
GAP: equ 77AH
GAP1: equ 78EH
GAP2: equ 796H
GAP3: equ 79CH
GAPCK: equ 0FE2H
GAPCK1: equ 0FEBH
GAPCK2: equ 0FEDH
GAPCK3: equ 0FFDH
GETKY: equ 1BH
GETL: equ 3H
GETL1: equ 7EAH
GETL2: equ 818H
GETL3: equ 85BH
GETL5: equ 81DH
GETL6: equ 865H
GETLA: equ 82BH
GETLB: equ 863H
GETLC: equ 822H
GETLR: equ 87EH
GETLU: equ 876H
GETLZ: equ 86CH
GOTO: equ 0F3H
GRSTAS: equ 0DD4H
HEX: equ 3F9H
HEXIY: equ 13DH
HEXJ: equ 3E5H
HLHEX: equ 410H
HOME: equ 0E4DH
IBUFE: equ 10F0H
INST: equ 0F38H
INST2: equ 0ECAH
KANA: equ 0EEEH
KANAF: equ 1170H
KSL1: equ 9B7H
KSL2: equ 9BCH
KTBL: equ 0BEAH
KTBLC: equ 0CAAH
KTBLG: equ 0CE9H
KTBLGS: equ 0C6AH
KTBLS: equ 0C2AH
L010F: equ 10FH
L01F5: equ 1F5H
L0207: equ 207H
L0220: equ 220H
L0239: equ 239H
L023F: equ 23FH
L0255: equ 255H
L025A: equ 25AH
L02D5: equ 2D5H
L02DB: equ 2DBH
L0363: equ 363H
L0378: equ 378H
L041D: equ 41DH
L0434: equ 434H
L047D: equ 47DH
L04C2: equ 4C2H
L04C4: equ 4C4H
L0563: equ 563H
L060E: equ 60EH
L061A: equ 61AH
L066C: equ 66CH
L06AD: equ 6ADH
L06B4: equ 6B4H
L071C: equ 71CH
L0725: equ 725H
L0737: equ 737H
L0739: equ 739H
L075B: equ 75BH
L0762: equ 762H
L08F7: equ 8F7H
L092C: equ 92CH
L0968: equ 968H
L0999: equ 999H
L09AB: equ 9ABH
L0A89: equ 0A89H
L0BA0: equ 0BA0H
L0BB1: equ 0BB1H
L0D36: equ 0D36H
L0D51: equ 0D51H
L0D78: equ 0D78H
L0D7A: equ 0D7AH
L0D85: equ 0D85H
L0DA7: equ 0DA7H
L0DAD: equ 0DADH
L0DE0: equ 0DE0H
L0E2D: equ 0E2DH
L0F17: equ 0F17H
L0F33: equ 0F33H
L0F42: equ 0F42H
L0F4D: equ 0F4DH
L2HEX: equ 41FH
LETNL: equ 6H
LLPT: equ 470H
LOA0: equ 116H
LOAD: equ 111H
LONG: equ 0A1AH
LPRNT: equ 18FH
MANG: equ 1173H
MCOR: equ 7A8H
MCR1: equ 7ABH
MCR2: equ 7D4H
MCR3: equ 7D7H
MELDY: equ 30H
MLD1: equ 1D1H
MLD2: equ 205H
MLD3: equ 20DH
MLD4: equ 211H
MLD5: equ 214H
MLDS1: equ 2C4H
MLDSP: equ 2BEH
MLDST: equ 2ABH
MNTBL: equ 284H
MONIT: equ 0H
MOT1: equ 6A4H
MOT2: equ 6ABH
MOT4: equ 6B9H
MOT5: equ 6D8H
MOT7: equ 6B7H
MOT8: equ 6D0H
MOT9: equ 6D7H
MOTOR: equ 69FH
MSG: equ 15H
MSG1: equ 896H
MSGE1: equ 147H
MSGN1: equ 3FBH
MSGN2: equ 3FDH
MSGN3: equ 402H
MSGN7: equ 467H
MSGOK: equ 942H
MSGQ2: equ 9A0H
MSGQ3: equ 6E7H
MSGSV: equ 98BH
MSGX: equ 18H
MSGX1: equ 8A4H
MSGX2: equ 8A7H
MST1: equ 705H
MST3: equ 717H
MSTA: equ 44H
MSTOP: equ 700H
MSTP: equ 47H
MTBL: equ 26CH
NAME: equ 10F1H
NBRK: equ 8B8H
NCLR08: equ 9D4H
NCLR8: equ 9D5H
NL: equ 9H
NLPHL: equ 5FAH
NOADD: equ 3E2H
OCTV: equ 11A0H
ONP1: equ 21FH
ONP2: equ 22CH
ONP3: equ 265H
ONPU: equ 21CH
ONTYO: equ 119FH
OPTBL: equ 29CH
P4DE: equ 2A6H
PEN: equ 18BH
PLOT: equ 184H
PLPT: equ 176H
PMANG: equ 2F3H
PMSG: equ 1A5H
PMSG1: equ 1A8H
PPLPT: equ 17BH
PRNT: equ 12H
PRNT2: equ 967H
PRNT3: equ 96CH
PRNT4: equ 96FH
PRNT5: equ 959H
PRNTS: equ 0CH
PRNTT: equ 0FH
PRTHL: equ 3BAH
PRTHX: equ 3C3H
PTEST: equ 155H
PTRN: equ 180H
PTST0: equ 15AH
PTST1: equ 170H
QADCN: equ 0BB9H
QBEL: equ 577H
QBELD: equ 352H
QBLNK: equ 0DA6H
QBRK: equ 0A32H
QBRK1: equ 0A48H
QBRK2: equ 980H
QBRK3: equ 986H
QCLER: equ 0FD8H
QCLRFF: equ 0FDBH
QDACN: equ 0BCEH
QDINT: equ 0FDDH
QDPCT: equ 0DDCH
QDSP: equ 0DB5H
QER: equ 107H
QFLAS: equ 9FFH
QFLS: equ 9E3H
QGET: equ 8BDH
QGETL: equ 7E6H
QKEY: equ 8CAH
QKY1: equ 8D6H
QKY2: equ 8DAH
QKY5: equ 8FAH
QKY55: equ 8FBH
QKYGRP: equ 8FEH
QKYGRS: equ 909H
QKYSM: equ 8B3H
QLOAD: equ 5F0H
QLTNL: equ 90EH
QMLDY: equ 1C7H
QMODE: equ 73EH
QMSG: equ 893H
QMSGX: equ 8A1H
QNL: equ 918H
QPNT1: equ 0FB4H
QPNT2: equ 0FBFH
QPONT: equ 0FB1H
QPRNT: equ 935H
QPRT: equ 946H
QPRTS: equ 920H
QPRTT: equ 924H
QQKEY: equ 9B3H
QRDD: equ 4F8H
QRDI: equ 4D8H
QRSTR: equ 0EE5H
QRSTR1: equ 0EE6H
QSAVE: equ 0B92H
QSWEP: equ 0A50H
QTEMP: equ 2E5H
QTMR1: equ 375H
QTMR2: equ 37FH
QTMRD: equ 358H
QTMS1: equ 331H
QTMS2: equ 344H
QTMST: equ 308H
QVRFY: equ 588H
QWRD: equ 475H
QWRI: equ 436H
RATIO: equ 11A1H
RBY1: equ 630H
RBY2: equ 649H
RBY3: equ 654H
RBYTE: equ 624H
RD1: equ 4E6H
RDA: equ 1B6H
RDDAT: equ 2AH
RDINF: equ 27H
RET1: equ 4D2H
RET2: equ 554H
RET3: equ 69BH
RTAPE: equ 50EH
RTP1: equ 513H
RTP2: equ 519H
RTP3: equ 532H
RTP4: equ 554H
RTP5: equ 565H
RTP6: equ 572H
RTP7: equ 56EH
RTP8: equ 553H
RTP9: equ 574H
RYTHM: equ 2C8H
SAV1: equ 0F8EH
SAVE: equ 0F5EH
SCROL: equ 0E6DH
SG: equ 0F7H
SHORT: equ 0A01H
SIZE: equ 1102H
SLPT: equ 3D5H
SPHEX: equ 3B1H
SPV: equ 10F0H
SS: equ 0A2H
ST0: equ 70H
ST1: equ 0ADH
ST2: equ 0BBH
START: equ 4AH
STRGF: equ 1193H
SUMDT: equ 1197H
SV0: equ 0BA2H
SV1: equ 0BB5H
SWEP0: equ 0A66H
SWEP01: equ 0A64H
SWEP2: equ 0A7FH
SWEP3: equ 0A77H
SWEP6: equ 0A5FH
SWEP9: equ 0A73H
SWRK: equ 119DH
TEMPW: equ 119EH
TIMFG: equ 119CH
TIMIN: equ 38DH
TIMRD: equ 3BH
TIMST: equ 33H
TM1: equ 675H
TM2: equ 678H
TM3: equ 688H
TM4: equ 69BH
TMARK: equ 65BH
TMCNT: equ 1195H
TVF1: equ 5B2H
TVF2: equ 5B8H
TVF3: equ 5CCH
TVRFY: equ 5ADH
VERFY: equ 2DH
VRFY: equ 0FCBH
VRNS: equ 0BC5H
WBY1: equ 76DH
WBYTE: equ 767H
WRDAT: equ 24H
WRI1: equ 444H
WRI2: equ 45EH
WRI3: equ 464H
WRINF: equ 21H
WTAP1: equ 494H
WTAP2: equ 4A5H
WTAP3: equ 4D2H
WTAPE: equ 48AH
XTEMP: equ 41H

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software/asm/monitor_80c_SA1510.sym
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@@ -1,394 +0,0 @@
.CP1: equ 13AH
.CR: equ 128H
.CTBL: equ 168H
.DSP03: equ 39DH
.MANG: equ 0A2BH
.MANG1: equ 0A4CH
.MANG2: equ 3A6H
.MANG3: equ 0A38H
.MANG4: equ 0A45H
.SCROL: equ 13DH
?ADCN: equ 0BB9H
?BEL: equ 2E5H
?BELD: equ 0DB1H
?BLNK: equ 0DA6H
?BRK: equ 0D11H
?CLER: equ 0FD8H
?CLRFF: equ 0FDBH
?DACN: equ 0BCEH
?DINT: equ 0FDDH
?DPCT: equ 0DDCH
?DSP: equ 0DB5H
?DSPA: equ 0D7CH
?ER: equ 0CFH
?FLAS: equ 9FFH
?GET: equ 8B3H
?GETL: equ 7A8H
?KEY: equ 8CAH
?KY1: equ 8D6H
?KY10: equ 8EFH
?KY11: equ 8EAH
?KY2: equ 8F2H
?KY3: equ 922H
?KY4: equ 92FH
?KY5: equ 91EH
?KY6: equ 92AH
?KY7: equ 93AH
?KY9: equ 93FH
?LOAD: equ 5F5H
?LTNL: equ 980H
?MLDY: equ 188H
?MODE: equ 74DH
?MSG: equ 893H
?MSGX: equ 8A1H
?NL: equ 97BH
?PNT1: equ 0FB4H
?PNT2: equ 0FCAH
?PONT: equ 0FB1H
?PRNT: equ 995H
?PRT: equ 946H
?PRTS: equ 993H
?PRTT: equ 984H
?RDD: equ 4EFH
?RDI: equ 4CFH
?RSTR: equ 0EE5H
?RSTR1: equ 0EE6H
?SAVE: equ 263H
?SWEP: equ 0A50H
?TEMP: equ 2ECH
?TMR1: equ 361H
?TMR1A: equ 364H
?TMR2: equ 36BH
?TMRD: equ 344H
?TMST: equ 2FAH
?VRFY: equ 575H
?WRD: equ 470H
?WRI: equ 436H
ALPHA: equ 0EE1H
ALPHI: equ 0EE2H
AMPM: equ 119BH
ASC: equ 3DAH
ATBL: equ 0AB5H
ATRB: equ 10F0H
AUTCK: equ 9F1H
AUTO2: equ 807H
AUTO3: equ 7C4H
AUTO5: equ 824H
AUTOL: equ 810H
AUTOL1: equ 812H
BELL: equ 3EH
BRKEY: equ 1EH
BUFER: equ 11A3H
CHGP1: equ 84BH
CHGPA: equ 83EH
CHGPK: equ 841H
CHGPK1: equ 843H
CLR8: equ 9E3H
CLRS: equ 0EB3H
CLRS1: equ 0ED1H
COMNT: equ 1108H
CR: equ 0F73H
CR2: equ 0F8BH
CR3: equ 0F99H
CSMDT: equ 1199H
CTBL: equ 0DFFH
CURS1: equ 0E66H
CURS2: equ 0E86H
CURS3: equ 0E69H
CURS4: equ 0E93H
CURS5: equ 0EAAH
CURS5A: equ 0E9FH
CURS6: equ 0ED7H
CURSD: equ 0E5DH
CURSL: equ 0E95H
CURSR: equ 0E7BH
CURSU: equ 0E6EH
CURSU1: equ 0E76H
DACN1: equ 0BE3H
DACN2: equ 0BDFH
DACN3: equ 0BE0H
DEL: equ 0EF2H
DEL1: equ 0F0AH
DEL2: equ 0F1DH
DLY12: equ 0DA7H
DLY12A: equ 0DAAH
DLY3: equ 9A2H
DMT: equ 857H
DPCT1: equ 0DF9H
DPRNT: equ 1194H
DSP01: equ 0DC2H
DSP02: equ 0D97H
DSP04: equ 0D8DH
DSPXY: equ 1171H
DTADR: equ 1104H
EDG1: equ 607H
EDG1A: equ 60FH
EDG2: equ 615H
EDG3: equ 61DH
EDGE: equ 601H
EXADR: equ 1106H
FD: equ 0C7H
FD2: equ 0CAH
FLAS1: equ 0A12H
FLAS2: equ 0A0BH
FLAS3: equ 0A0FH
FLASH: equ 118EH
FLSDT: equ 1192H
GAPCK: equ 0FE2H
GAPCK1: equ 0FEBH
GAPCK2: equ 0FEDH
GAPCK3: equ 0FFDH
GETKY: equ 1BH
GETL: equ 3H
GETL0: equ 7ACH
GETL0A: equ 7AFH
GETL0B: equ 7B6H
GETL0C: equ 7BEH
GETL0D: equ 7C5H
GETL1: equ 81AH
GETL2: equ 803H
GETL3: equ 85BH
GETL5: equ 839H
GETL6: equ 865H
GETL6A: equ 86CH
GETL6B: equ 878H
GETLA: equ 886H
GETLB: equ 863H
GETLC: equ 84EH
GETLD: equ 5E1H
GETLR: equ 880H
GOTO: equ 0BBH
HEX: equ 3F9H
HEX1: equ 3F2H
HEX2: equ 3F5H
HEXJ: equ 3E5H
HLHEX: equ 410H
HOM0: equ 409H
HOM00: equ 0ED4H
HOM1: equ 406H
HOME: equ 3FBH
HOOK: equ 120H
IBUFE: equ 10F0H
INST: equ 0F2DH
INST1: equ 0F4FH
INST1A: equ 0F37H
INST2: equ 0F42H
KANA: equ 0EEEH
KANAF: equ 1170H
KDATW: equ 116EH
KTBL: equ 0BEAH
KTBLC: equ 0CDAH
KTBLG: equ 0C6AH
KTBLGS: equ 0CA2H
KTBLS: equ 0C32H
L0270: equ 270H
L028F: equ 28FH
L029A: equ 29AH
L02C4: equ 2C4H
L02D5: equ 2D5H
L02DB: equ 2DBH
L0323: equ 323H
L0336: equ 336H
L03D5: equ 3D5H
L041D: equ 41DH
L041F: equ 41FH
L0434: equ 434H
L0444: equ 444H
L045E: equ 45EH
L0464: equ 464H
L0485: equ 485H
L048F: equ 48FH
L049E: equ 49EH
L04BB: equ 4BBH
L04BD: equ 4BDH
L04CB: equ 4CBH
L04DD: equ 4DDH
L0505: equ 505H
L050A: equ 50AH
L0510: equ 510H
L052A: equ 52AH
L0551: equ 551H
L0552: equ 552H
L0561: equ 561H
L0563: equ 563H
L056C: equ 56CH
L0570: equ 570H
L0572: equ 572H
L06B1: equ 6B1H
L06E7: equ 6E7H
L06F0: equ 6F0H
L0705: equ 705H
L0717: equ 717H
L071A: equ 71AH
L0720: equ 720H
L072F: equ 72FH
L0733: equ 733H
L0737: equ 737H
L073E: equ 73EH
L0743: equ 743H
L0759: equ 759H
L075B: equ 75BH
L0760: equ 760H
L0762: equ 762H
L0767: equ 767H
L076D: equ 76DH
L077A: equ 77AH
L078E: equ 78EH
L0796: equ 796H
L079C: equ 79CH
L0917: equ 917H
L091B: equ 91BH
L098C: equ 98CH
L09AB: equ 9ABH
L09B9: equ 9B9H
L09C7: equ 9C7H
L09E2: equ 9E2H
L09E8: equ 9E8H
L0D27: equ 0D27H
L0D2B: equ 0D2BH
L0D37: equ 0D37H
L0D3E: equ 0D3EH
L0D57: equ 0D57H
L0D80: equ 0D80H
L0D89: equ 0D89H
L0D90: equ 0D90H
L0F13: equ 0F13H
LETNL: equ 6H
LOAD: equ 0D9H
LOCK: equ 88BH
M?TBL: equ 241H
MANG: equ 1173H
MANGE: equ 1179H
MELDY: equ 30H
MGP.D: equ 29DH
MGP.I: equ 283H
MGPNT: equ 117CH
MLD1: equ 192H
MLD1A: equ 1B6H
MLD2: equ 1C6H
MLD2A: equ 1C8H
MLD3: equ 1CEH
MLD4: equ 1D2H
MLD5: equ 1D5H
MLDSP: equ 2BEH
MLDST: equ 2ABH
MONIT: equ 0H
MOT1: equ 6A8H
MOT2: equ 6AFH
MOT4: equ 6B9H
MOT5: equ 6D8H
MOT7: equ 6B7H
MOT8: equ 6D0H
MOT9: equ 6D7H
MOTOR: equ 6A3H
MSG: equ 15H
MSG1: equ 896H
MSG?2: equ 0F7H
MSG?3: equ 100H
MSG?7: equ 467H
MSGE1: equ 118H
MSGX: equ 18H
MSGX1: equ 8A4H
MSGX2: equ 8A7H
MSG_1: equ 0D9EH
MSG_2: equ 0DA0H
MSG_3: equ 6F4H
MSTA: equ 44H
MSTOP: equ 700H
MSTP: equ 47H
MTBL: equ 229H
NAME: equ 10F1H
NL: equ 9H
NOADD: equ 3E2H
OCTV: equ 11A0H
ONP1A: equ 1E1H
ONP2: equ 1EDH
ONP2A: equ 1FAH
ONP2B: equ 200H
ONP2C: equ 216H
ONP2D: equ 21BH
ONPU: equ 1DDH
ONTYO: equ 119FH
OPTBL: equ 259H
PAGETP: equ 117DH
PBIAS: equ 117AH
PRNT: equ 12H
PRNT2: equ 967H
PRNT2A: equ 968H
PRNT3: equ 96CH
PRNT4: equ 96FH
PRNT4A: equ 979H
PRNT5: equ 955H
PRNTS: equ 0CH
PRNTT: equ 0FH
PRTHL: equ 3B8H
PRTHX: equ 3C3H
RATIO: equ 11A1H
RBY1: equ 630H
RBY2: equ 649H
RBY3: equ 654H
RBYTE: equ 624H
RDDAT: equ 2AH
RDINF: equ 27H
RET3: equ 69FH
REV: equ 0A17H
REV1: equ 0A25H
REV2: equ 0A28H
REVFLG: equ 1190H
ROL2: equ 0F68H
ROLD: equ 0F59H
ROLEND: equ 117FH
ROLTOP: equ 117BH
ROLU: equ 0F9FH
ROLU1: equ 0FA9H
ROLUP: equ 5E8H
RYTHM: equ 2C8H
SCROL: equ 0E1FH
SCROL1: equ 0E32H
SCROL2: equ 0E42H
SCROL3: equ 0E55H
SFTLK: equ 118FH
SG: equ 0C1H
SIZE: equ 1102H
SPAGE: equ 1191H
SPV: equ 10F0H
SS: equ 89H
SS1: equ 8BH
ST1: equ 95H
ST2: equ 0A3H
START: equ 4AH
STRGF: equ 1193H
STRT1: equ 69H
SUMDT: equ 1197H
SWEP0: equ 0A76H
SWEP01: equ 0A74H
SWEP11: equ 0A8EH
SWEP2: equ 0AACH
SWEP3: equ 0A92H
SWEP6: equ 0A62H
SWEP7: equ 0AA5H
SWEP8: equ 0AA0H
SWEP9: equ 0A8AH
SWPW: equ 1164H
SWRK: equ 119DH
TEMPW: equ 119EH
TIMFG: equ 119CH
TIMIN: equ 379H
TIMRD: equ 3BH
TIMST: equ 33H
TM0: equ 66AH
TM1: equ 673H
TM2: equ 676H
TM3: equ 689H
TM4: equ 69FH
TMARK: equ 658H
TMCNT: equ 1195H
TVF1: equ 5A0H
TVF2: equ 5A6H
TVF3: equ 5BAH
TVRFY: equ 59BH
VERFY: equ 2DH
WRDAT: equ 24H
WRINF: equ 21H
XTEMP: equ 41H
_BRK: equ 0BC5H

BIN
software/asm/monitor_SA1510.obj
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394
software/asm/monitor_SA1510.sym
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@@ -1,394 +0,0 @@
.CP1: equ 13AH
.CR: equ 128H
.CTBL: equ 168H
.DSP03: equ 39DH
.MANG: equ 0A2BH
.MANG1: equ 0A4CH
.MANG2: equ 3A6H
.MANG3: equ 0A38H
.MANG4: equ 0A45H
.SCROL: equ 13DH
?ADCN: equ 0BB9H
?BEL: equ 2E5H
?BELD: equ 0DB1H
?BLNK: equ 0DA6H
?BRK: equ 0D11H
?CLER: equ 0FD8H
?CLRFF: equ 0FDBH
?DACN: equ 0BCEH
?DINT: equ 0FDDH
?DPCT: equ 0DDCH
?DSP: equ 0DB5H
?DSPA: equ 0D7CH
?ER: equ 0CFH
?FLAS: equ 9FFH
?GET: equ 8B3H
?GETL: equ 7A8H
?KEY: equ 8CAH
?KY1: equ 8D6H
?KY10: equ 8EFH
?KY11: equ 8EAH
?KY2: equ 8F2H
?KY3: equ 922H
?KY4: equ 92FH
?KY5: equ 91EH
?KY6: equ 92AH
?KY7: equ 93AH
?KY9: equ 93FH
?LOAD: equ 5F5H
?LTNL: equ 980H
?MLDY: equ 188H
?MODE: equ 74DH
?MSG: equ 893H
?MSGX: equ 8A1H
?NL: equ 97BH
?PNT1: equ 0FB4H
?PNT2: equ 0FCAH
?PONT: equ 0FB1H
?PRNT: equ 995H
?PRT: equ 946H
?PRTS: equ 993H
?PRTT: equ 984H
?RDD: equ 4EFH
?RDI: equ 4CFH
?RSTR: equ 0EE5H
?RSTR1: equ 0EE6H
?SAVE: equ 263H
?SWEP: equ 0A50H
?TEMP: equ 2ECH
?TMR1: equ 361H
?TMR1A: equ 364H
?TMR2: equ 36BH
?TMRD: equ 344H
?TMST: equ 2FAH
?VRFY: equ 575H
?WRD: equ 470H
?WRI: equ 436H
ALPHA: equ 0EE1H
ALPHI: equ 0EE2H
AMPM: equ 119BH
ASC: equ 3DAH
ATBL: equ 0AB5H
ATRB: equ 10F0H
AUTCK: equ 9F1H
AUTO2: equ 807H
AUTO3: equ 7C4H
AUTO5: equ 824H
AUTOL: equ 810H
AUTOL1: equ 812H
BELL: equ 3EH
BRKEY: equ 1EH
BUFER: equ 11A3H
CHGP1: equ 84BH
CHGPA: equ 83EH
CHGPK: equ 841H
CHGPK1: equ 843H
CLR8: equ 9E3H
CLRS: equ 0EB3H
CLRS1: equ 0ED1H
COMNT: equ 1108H
CR: equ 0F73H
CR2: equ 0F8BH
CR3: equ 0F99H
CSMDT: equ 1199H
CTBL: equ 0DFFH
CURS1: equ 0E66H
CURS2: equ 0E86H
CURS3: equ 0E69H
CURS4: equ 0E93H
CURS5: equ 0EAAH
CURS5A: equ 0E9FH
CURS6: equ 0ED7H
CURSD: equ 0E5DH
CURSL: equ 0E95H
CURSR: equ 0E7BH
CURSU: equ 0E6EH
CURSU1: equ 0E76H
DACN1: equ 0BE3H
DACN2: equ 0BDFH
DACN3: equ 0BE0H
DEL: equ 0EF2H
DEL1: equ 0F0AH
DEL2: equ 0F1DH
DLY12: equ 0DA7H
DLY12A: equ 0DAAH
DLY3: equ 9A2H
DMT: equ 857H
DPCT1: equ 0DF9H
DPRNT: equ 1194H
DSP01: equ 0DC2H
DSP02: equ 0D97H
DSP04: equ 0D8DH
DSPXY: equ 1171H
DTADR: equ 1104H
EDG1: equ 607H
EDG1A: equ 60FH
EDG2: equ 615H
EDG3: equ 61DH
EDGE: equ 601H
EXADR: equ 1106H
FD: equ 0C7H
FD2: equ 0CAH
FLAS1: equ 0A12H
FLAS2: equ 0A0BH
FLAS3: equ 0A0FH
FLASH: equ 118EH
FLSDT: equ 1192H
GAPCK: equ 0FE2H
GAPCK1: equ 0FEBH
GAPCK2: equ 0FEDH
GAPCK3: equ 0FFDH
GETKY: equ 1BH
GETL: equ 3H
GETL0: equ 7ACH
GETL0A: equ 7AFH
GETL0B: equ 7B6H
GETL0C: equ 7BEH
GETL0D: equ 7C5H
GETL1: equ 81AH
GETL2: equ 803H
GETL3: equ 85BH
GETL5: equ 839H
GETL6: equ 865H
GETL6A: equ 86CH
GETL6B: equ 878H
GETLA: equ 886H
GETLB: equ 863H
GETLC: equ 84EH
GETLD: equ 5E1H
GETLR: equ 880H
GOTO: equ 0BBH
HEX: equ 3F9H
HEX1: equ 3F2H
HEX2: equ 3F5H
HEXJ: equ 3E5H
HLHEX: equ 410H
HOM0: equ 409H
HOM00: equ 0ED4H
HOM1: equ 406H
HOME: equ 3FBH
HOOK: equ 128H
IBUFE: equ 10F0H
INST: equ 0F2DH
INST1: equ 0F4FH
INST1A: equ 0F37H
INST2: equ 0F42H
KANA: equ 0EEEH
KANAF: equ 1170H
KDATW: equ 116EH
KTBL: equ 0BEAH
KTBLC: equ 0CDAH
KTBLG: equ 0C6AH
KTBLGS: equ 0CA2H
KTBLS: equ 0C32H
L0270: equ 270H
L028F: equ 28FH
L029A: equ 29AH
L02C4: equ 2C4H
L02D5: equ 2D5H
L02DB: equ 2DBH
L0323: equ 323H
L0336: equ 336H
L03D5: equ 3D5H
L041D: equ 41DH
L041F: equ 41FH
L0434: equ 434H
L0444: equ 444H
L045E: equ 45EH
L0464: equ 464H
L0485: equ 485H
L048F: equ 48FH
L049E: equ 49EH
L04BB: equ 4BBH
L04BD: equ 4BDH
L04CB: equ 4CBH
L04DD: equ 4DDH
L0505: equ 505H
L050A: equ 50AH
L0510: equ 510H
L052A: equ 52AH
L0551: equ 551H
L0552: equ 552H
L0561: equ 561H
L0563: equ 563H
L056C: equ 56CH
L0570: equ 570H
L0572: equ 572H
L06B1: equ 6B1H
L06E7: equ 6E7H
L06F0: equ 6F0H
L0705: equ 705H
L0717: equ 717H
L071A: equ 71AH
L0720: equ 720H
L072F: equ 72FH
L0733: equ 733H
L0737: equ 737H
L073E: equ 73EH
L0743: equ 743H
L0759: equ 759H
L075B: equ 75BH
L0760: equ 760H
L0762: equ 762H
L0767: equ 767H
L076D: equ 76DH
L077A: equ 77AH
L078E: equ 78EH
L0796: equ 796H
L079C: equ 79CH
L0917: equ 917H
L091B: equ 91BH
L098C: equ 98CH
L09AB: equ 9ABH
L09B9: equ 9B9H
L09C7: equ 9C7H
L09E2: equ 9E2H
L09E8: equ 9E8H
L0D27: equ 0D27H
L0D2B: equ 0D2BH
L0D37: equ 0D37H
L0D3E: equ 0D3EH
L0D57: equ 0D57H
L0D80: equ 0D80H
L0D89: equ 0D89H
L0D90: equ 0D90H
L0F13: equ 0F13H
LETNL: equ 6H
LOAD: equ 0D9H
LOCK: equ 88BH
M?TBL: equ 241H
MANG: equ 1173H
MANGE: equ 1179H
MELDY: equ 30H
MGP.D: equ 29DH
MGP.I: equ 283H
MGPNT: equ 117CH
MLD1: equ 192H
MLD1A: equ 1B6H
MLD2: equ 1C6H
MLD2A: equ 1C8H
MLD3: equ 1CEH
MLD4: equ 1D2H
MLD5: equ 1D5H
MLDSP: equ 2BEH
MLDST: equ 2ABH
MONIT: equ 0H
MOT1: equ 6A8H
MOT2: equ 6AFH
MOT4: equ 6B9H
MOT5: equ 6D8H
MOT7: equ 6B7H
MOT8: equ 6D0H
MOT9: equ 6D7H
MOTOR: equ 6A3H
MSG: equ 15H
MSG1: equ 896H
MSG?2: equ 0F7H
MSG?3: equ 100H
MSG?7: equ 467H
MSGE1: equ 118H
MSGX: equ 18H
MSGX1: equ 8A4H
MSGX2: equ 8A7H
MSG_1: equ 0D9EH
MSG_2: equ 0DA0H
MSG_3: equ 6F4H
MSTA: equ 44H
MSTOP: equ 700H
MSTP: equ 47H
MTBL: equ 229H
NAME: equ 10F1H
NL: equ 9H
NOADD: equ 3E2H
OCTV: equ 11A0H
ONP1A: equ 1E1H
ONP2: equ 1EDH
ONP2A: equ 1FAH
ONP2B: equ 200H
ONP2C: equ 216H
ONP2D: equ 21BH
ONPU: equ 1DDH
ONTYO: equ 119FH
OPTBL: equ 259H
PAGETP: equ 117DH
PBIAS: equ 117AH
PRNT: equ 12H
PRNT2: equ 967H
PRNT2A: equ 968H
PRNT3: equ 96CH
PRNT4: equ 96FH
PRNT4A: equ 979H
PRNT5: equ 955H
PRNTS: equ 0CH
PRNTT: equ 0FH
PRTHL: equ 3B8H
PRTHX: equ 3C3H
RATIO: equ 11A1H
RBY1: equ 630H
RBY2: equ 649H
RBY3: equ 654H
RBYTE: equ 624H
RDDAT: equ 2AH
RDINF: equ 27H
RET3: equ 69FH
REV: equ 0A17H
REV1: equ 0A25H
REV2: equ 0A28H
REVFLG: equ 1190H
ROL2: equ 0F68H
ROLD: equ 0F59H
ROLEND: equ 117FH
ROLTOP: equ 117BH
ROLU: equ 0F9FH
ROLU1: equ 0FA9H
ROLUP: equ 5E8H
RYTHM: equ 2C8H
SCROL: equ 0E1FH
SCROL1: equ 0E32H
SCROL2: equ 0E42H
SCROL3: equ 0E55H
SFTLK: equ 118FH
SG: equ 0C1H
SIZE: equ 1102H
SPAGE: equ 1191H
SPV: equ 10F0H
SS: equ 89H
SS1: equ 8BH
ST1: equ 95H
ST2: equ 0A3H
START: equ 4AH
STRGF: equ 1193H
STRT1: equ 69H
SUMDT: equ 1197H
SWEP0: equ 0A76H
SWEP01: equ 0A74H
SWEP11: equ 0A8EH
SWEP2: equ 0AACH
SWEP3: equ 0A92H
SWEP6: equ 0A62H
SWEP7: equ 0AA5H
SWEP8: equ 0AA0H
SWEP9: equ 0A8AH
SWPW: equ 1164H
SWRK: equ 119DH
TEMPW: equ 119EH
TIMFG: equ 119CH
TIMIN: equ 379H
TIMRD: equ 3BH
TIMST: equ 33H
TM0: equ 66AH
TM1: equ 673H
TM2: equ 676H
TM3: equ 689H
TM4: equ 69FH
TMARK: equ 658H
TMCNT: equ 1195H
TVF1: equ 5A0H
TVF2: equ 5A6H
TVF3: equ 5BAH
TVRFY: equ 59BH
VERFY: equ 2DH
WRDAT: equ 24H
WRINF: equ 21H
XTEMP: equ 41H
_BRK: equ 0BC5H

BIN
software/asm/monitor_mz-1r12.obj
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49
software/asm/monitor_mz-1r12.sym
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@@ -1,49 +0,0 @@
CHECK: equ 0E93DH
CK1: equ 0E942H
CK2: equ 0E947H
LE83B: equ 0E83BH
LE85B: equ 0E85BH
LE877: equ 0E877H
LE893: equ 0E893H
LE8AB: equ 0E8ABH
LE8C1: equ 0E8C1H
LE908: equ 0E908H
LE90A: equ 0E90AH
LE931: equ 0E931H
LE94B: equ 0E94BH
LE956: equ 0E956H
LE96A: equ 0E96AH
LE9A4: equ 0E9A4H
LE9A8: equ 0E9A8H
LE9AD: equ 0E9ADH
LEA1A: equ 0EA1AH
LEA1C: equ 0EA1CH
LEA36: equ 0EA36H
LEA39: equ 0EA39H
LEA3D: equ 0EA3DH
LEA42: equ 0EA42H
LEA4A: equ 0EA4AH
LEA4C: equ 0EA4CH
LEA60: equ 0EA60H
LEA74: equ 0EA74H
LEA8F: equ 0EA8FH
LEAAC: equ 0EAACH
LEACB: equ 0EACBH
LEAF1: equ 0EAF1H
LEB06: equ 0EB06H
LEB1B: equ 0EB1BH
LEB3E: equ 0EB3EH
LEB56: equ 0EB56H
LEB77: equ 0EB77H
LEB8C: equ 0EB8CH
LEBAD: equ 0EBADH
MON: equ 0EA52H
MZ1R12: equ 0E800H
ST1X: equ 0E80CH
SUM: equ 0E91DH
SUMCK1: equ 0E926H
SUMCK2: equ 0E939H
SUMCK3: equ 0E92DH
WCK1: equ 0EA01H
WCK2: equ 0EA05H
WCK3: equ 0EA09H

BIN
software/asm/quickdisk_mz-1e05.obj
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72
software/asm/quickdisk_mz-1e05.sym
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@@ -1,72 +0,0 @@
ADJ: equ 0F273H
BOOT: equ 0F0BFH
BREAD: equ 0F1DEH
BSY0: equ 0F1D8H
BSYOF0: equ 0F1C6H
BSYOF1: equ 0F1D3H
BSYOF2: equ 0F1C3H
BSYOFF: equ 0F1BEH
BSYON: equ 0F19FH
BSYON0: equ 0F1A7H
BSYON1: equ 0F1B4H
BSYON2: equ 0F1A4H
BSYONE: equ 0F1B7H
CMDOT1: equ 0F18CH
CMDOT2: equ 0F285H
CNVRT: equ 0F2CDH
DLY1M: equ 0F2F1H
DLY60M: equ 0F2F8H
DLY80U: equ 0F2EAH
DLYT: equ 0F2FCH
ERCK1: equ 0F2BAH
ERJMP: equ 0F2C7H
ERRET: equ 0F2C5H
ERRET1: equ 0F2C1H
ERRM0: equ 0F0F4H
ERRM1: equ 0F0C8H
ERRTR1: equ 0F0ACH
ERRTRT: equ 0F0A2H
FDCC: equ 0F105H
FDX: equ 0F006H
INTER: equ 0F28FH
IPLM0: equ 0F0D6H
IPLM3: equ 0F0E6H
IPLMC: equ 0F0B8H
L_F007: equ 0F007H
L_F051: equ 0F051H
L_F057: equ 0F057H
L_F05C: equ 0F05CH
L_F093: equ 0F093H
L_F111: equ 0F111H
L_F189: equ 0F189H
L_F213: equ 0F213H
L_F214: equ 0F214H
L_F23F: equ 0F23FH
L_F25D: equ 0F25DH
L_F25E: equ 0F25EH
L_F282: equ 0F282H
MASTE: equ 0F09AH
MCHECK: equ 0F031H
MOFF: equ 0F167H
MTD1: equ 0F154H
MTON: equ 0F14EH
MZ_1E05: equ 0F000H
NOTIO: equ 0F0A4H
PARST1: equ 0F232H
PARST2: equ 0F262H
RCLB: equ 0F17FH
RE3: equ 0F217H
RE4: equ 0F1F8H
RE6: equ 0F1F6H
RE8: equ 0F1E4H
READY: equ 0F113H
REDY0: equ 0F12BH
REDY1: equ 0F149H
REDY2: equ 0F148H
REND: equ 0F22DH
SEEK: equ 0F15FH
SIDST: equ 0F252H
SJP: equ 0F022H
STERROR: equ 0F298H
TRANS0: equ 0F2D9H
TRANS1: equ 0F2E0H

BIN
software/asm/quickdisk_mz-1e14.obj
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161
software/asm/quickdisk_mz-1e14.sym
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@@ -1,161 +0,0 @@
..LPTX: equ 0E98EH
.LPTX: equ 0E989H
?ERX: equ 0E8EBH
?ERX1: equ 0EA4CH
BDR: equ 0EE3BH
BGETLX: equ 0E8F8H
BRKC: equ 0EFECH
DIREFC: equ 0EC4CH
DIRIOP: equ 0EC2CH
DIRMSG: equ 0ED5DH
DIRMTF: equ 0EC53H
DISCLR: equ 0EB45H
DMR: equ 0EE6FH
DMR1: equ 0EE77H
DSFLNA: equ 0EB7BH
DSPATR: equ 0EC67H
DUMPX: equ 0EA78H
FDCK: equ 0E8DEH
FILESH: equ 0EB6FH
FILSCH: equ 0EBDCH
FNEND: equ 0EECCH
FNINP: equ 0EADCH
GOTOX: equ 0E910H
HDPCL: equ 0ED08H
HEXIYX: equ 0E906H
HPNFE: equ 0EE87H
HPS: equ 0EE51H
HPS1: equ 0EE84H
IOE41: equ 0EFC0H
IOE46: equ 0EFC3H
IOE50: equ 0EFC6H
IOE53: equ 0EFC9H
IOE54: equ 0EFCCH
IOFRS: equ 0EBD1H
LDFNCK: equ 0EC00H
LE800: equ 0E800H
LE80A: equ 0E80AH
LE868: equ 0E868H
LE86B: equ 0E86BH
LE871: equ 0E871H
LE87D: equ 0E87DH
LE941: equ 0E941H
LE954: equ 0E954H
LE999: equ 0E999H
LEA5B: equ 0EA5BH
LEA6A: equ 0EA6AH
LEA76: equ 0EA76H
LEA85: equ 0EA85H
LEA86: equ 0EA86H
LEA8D: equ 0EA8DH
LEAA0: equ 0EAA0H
LEAC7: equ 0EAC7H
LEAC9: equ 0EAC9H
LEAD3: equ 0EAD3H
LEAD6: equ 0EAD6H
LEAF3: equ 0EAF3H
LEB00: equ 0EB00H
LEB08: equ 0EB08H
LEB0C: equ 0EB0CH
LEB14: equ 0EB14H
LEB1E: equ 0EB1EH
LEB20: equ 0EB20H
LEB22: equ 0EB22H
LEB27: equ 0EB27H
LEB37: equ 0EB37H
LEB8B: equ 0EB8BH
LEBAC: equ 0EBACH
LEBBD: equ 0EBBDH
LECA1: equ 0ECA1H
LECA4: equ 0ECA4H
LECA5: equ 0ECA5H
LECB6: equ 0ECB6H
LECBA: equ 0ECBAH
LECFC: equ 0ECFCH
LED4C: equ 0ED4CH
LEDF3: equ 0EDF3H
LOADX: equ 0E914H
LPARA0: equ 0EB97H
LPARA1: equ 0EB9AH
LPRNTX: equ 0E9A2H
LREDY: equ 0EEE5H
LSINT: equ 0EED6H
MCORX: equ 0E9D9H
MCORX1: equ 0E9DCH
MCRX2: equ 0EA05H
MCRX3: equ 0EA08H
MGHDE: equ 0ED27H
MGNFE: equ 0ED15H
MGNRE: equ 0ED33H
MGUFE: equ 0ED40H
MON: equ 0E880H
MSGQ01: equ 0ED6EH
MSGQ02: equ 0ED79H
MSGQ03: equ 0ED84H
MSGQ04: equ 0ED8FH
MSGQ05: equ 0ED9AH
MSGQ07: equ 0EDA5H
MSGQ10: equ 0EDB0H
MSGQ11: equ 0EDBBH
MSGQ??: equ 0EDC6H
MSGQOK: equ 0ED11H
MSGTRM: equ 0ED14H
MTOF: equ 0EF03H
MTON: equ 0EEB7H
MZ1E14: equ 0E800H
NRCK: equ 0EFA8H
PENX: equ 0E99EH
PLOTX: equ 0E997H
PMSGX: equ 0E9B8H
PMSGX1: equ 0E9BBH
PTESTX: equ 0E968H
PTRNX: equ 0E993H
PTST0X: equ 0E96DH
PTST1X: equ 0E983H
QBT: equ 0E835H
QD: equ 0EC18H
QDHPC: equ 0EE0DH
QDIOS: equ 0E807H
QDIOS1: equ 0EDD1H
QDOFF: equ 0EF03H
QDOKM: equ 0ECC8H
QDRC: equ 0EE14H
QDRCK: equ 0EC0CH
QDRD: equ 0EE1AH
QER04: equ 0EC51H
QERMF: equ 0ECF1H
QERTRT: equ 0ECD2H
QL: equ 0EB5DH
QLINF: equ 0EBEEH
QMEIN: equ 0EDF8H
QREDY: equ 0EE8BH
QUICK: equ 0E8CBH
RDATA: equ 0EFB3H
RDATANRCK: equ 0EFA8H
RDAX: equ 0E9C9H
RDCR1: equ 0EF92H
RDCR2: equ 0EF97H
RDCRC: equ 0EF90H
RTY: equ 0EDD6H
RTY4: equ 0EDF6H
SAVEX: equ 0EA0CH
SAVX1: equ 0EA3CH
SGX: equ 0EA6DH
SIOLD: equ 0EFE1H
ST1X: equ 0E884H
ST1X1: equ 0E8DCH
ST1X2: equ 0E986H
ST2X: equ 0E892H
SYNCA: equ 0EF81H
SYNCL1: equ 0EF2EH
SYNCL2: equ 0EF18H
SYNCW0: equ 0EF47H
SYNCW01: equ 0EF70H
SYNCW1: equ 0EF59H
SYNCW2: equ 0EF63H
SYNCW3: equ 0EF73H
TIMW: equ 0EFD4H
TIMW1: equ 0EFD5H
TIMW2: equ 0EFD7H
TMLPL: equ 0EF31H
VRFYX: equ 0EA5EH

2
software/asm/sa1510.asm
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@@ -70,7 +70,7 @@ SS1: LD (SWRK),A
JR FD2
ST1: CALL NL
LD A,03EH
LD A,02AH
CALL PRNT
LD DE,BUFER
CALL GETL

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software/asm/sharpmz-test.obj
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252
software/asm/sharpmz-test.sym
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@@ -1,252 +0,0 @@
?ER: equ 0C1ACH
?RDD: equ 0C1E5H
?RDI: equ 0C1BAH
?TMR1: equ 0C854H
?TMR1A: equ 0C857H
?TMR2: equ 0C85EH
?TMRD: equ 0C837H
?TMST: equ 0C71FH
ABCD: equ 0C72BH
AMPM: equ 119BH
ARARA: equ 0C6EEH
ATRB: equ 10F0H
BANKMSG: equ 0CC53H
BITMSG: equ 0CC4BH
BUFER: equ 11A3H
CDEF: equ 0C7C0H
CKS1: equ 0C406H
CKS2: equ 0C415H
CKS3: equ 0C419H
CKS4: equ 0C41DH
CKSUM: equ 0C400H
CLEAR1: equ 0BFB7H
COMNT: equ 1108H
CSMDT: equ 1199H
DLY1: equ 0C424H
DLY12: equ 0C43BH
DLY12A: equ 0C43EH
DLY1A: equ 0C426H
DLY1S: equ 0C6F2H
DLY2: equ 0C42BH
DLY2A: equ 0C42DH
DLY3: equ 0C432H
DONEMSG: equ 0CC37H
DPRNT: equ 1194H
DSPXY: equ 1171H
DTADR: equ 1104H
EDG0: equ 0C2C9H
EDG1: equ 0C2C1H
EDG2: equ 0C2CFH
EDG3: equ 0C2D7H
EDGE: equ 0C2BBH
EXADR: equ 1106H
FLASH: equ 118EH
FLPST: equ 118FH
FLSDT: equ 1192H
FLSST: equ 1191H
GAP: equ 0C445H
GAP0: equ 0C45AH
GAP1: equ 0C461H
GAP1A: equ 0C498H
GAP1B: equ 0C472H
GAP1C: equ 0C48FH
GAP1D: equ 0C478H
GAP2: equ 0C49FH
GAP2A: equ 0C4DEH
GAP2B: equ 0C4ADH
GAP2C: equ 0C4D6H
GAP2D: equ 0C4B6H
GAP3: equ 0C4E6H
GAP3A: equ 0C525H
GAP3B: equ 0C4F4H
GAP3C: equ 0C51DH
GAP3D: equ 0C4FDH
GAPCK: equ 0C537H
GAPCK1: equ 0C549H
GAPCK2: equ 0C54BH
GAPCK3: equ 0C55BH
GETL1: equ 0BFC1H
GETL2: equ 0BFCFH
GRAM0: equ 0BF07H
GRAM1: equ 0BF0DH
GRAMINIT: equ 0BF03H
GRAMTEST: equ 0BF19H
GRAMTEST0: equ 0BF1FH
GRAMTEST1: equ 0BF25H
GRAPHICS: equ 0BF36H
GRPHIND: equ 0BF5CH
GRPHPOS: equ 0CC5BH
HELP: equ 0C890H
IBUFE: equ 10F0H
INITGRPH: equ 0BF7AH
INITMEM: equ 0BFA8H
KANAF: equ 1170H
L0323: equ 0C750H
L0324: equ 0C6F6H
L0330: equ 0C791H
L0336: equ 0C7C9H
L0340: equ 0C813H
L047D: equ 0C5D8H
L04C2: equ 0C629H
L04C4: equ 0C633H
LOA0: equ 0C0CDH
LOAD: equ 0C0C7H
LONG: equ 0C577H
LOOP: equ 0BFFBH
LOOP1: equ 0C000H
LOOP10: equ 0C0C0H
LOOP11: equ 0C0C2H
LOOP1a: equ 0C00CH
LOOP1b: equ 0C012H
LOOP2: equ 0C023H
LOOP3: equ 0C041H
LOOP4: equ 0C066H
LOOP5: equ 0C06DH
LOOP6: equ 0C07FH
LOOP7: equ 0C090H
LOOP8: equ 0C098H
LOOP9: equ 0C0B8H
MANG: equ 1173H
MEMTEST: equ 0BFF9H
MEND: equ 0CDDEH
MOT1: equ 0C396H
MOT2: equ 0C39DH
MOT3: equ 0C39FH
MOT4: equ 0C3A7H
MOT5: equ 0C3CAH
MOT7: equ 0C3A5H
MOT8: equ 0C3BEH
MOT9: equ 0C3C7H
MOTOR: equ 0C384H
MSG1: equ 0C9B7H
MSG2: equ 0C9B9H
MSG3: equ 0C9BFH
MSGGAP: equ 0CB70H
MSGN7: equ 0C9CAH
MSGOK: equ 0C9D4H
MSGTAPE: equ 0CBDBH
MSG_CHKSUM_MZ1: equ 0CAF6H
MSG_CHKSUM_MZ2: equ 0CB24H
MSG_CHKSUM_TP1: equ 0CB0DH
MSG_CHKSUM_TP2: equ 0CB3BH
MSG_ERRCHKSUM: equ 0C9D8H
MSG_ERRWRITE: equ 0C9E7H
MSG_GAPCK: equ 0CA33H
MSG_HELP1: equ 0C8CFH
MSG_HELP2: equ 0C8EAH
MSG_HELP3: equ 0C903H
MSG_HELP4: equ 0C91AH
MSG_HELP5: equ 0C932H
MSG_HELP6: equ 0C94FH
MSG_INITGR: equ 0C98DH
MSG_INITM: equ 0C99BH
MSG_LOADEXEC: equ 0CA6CH
MSG_LOADFILE: equ 0CA3EH
MSG_LOADFROM: equ 0CA55H
MSG_LOADSIZE: equ 0CA83H
MSG_MOTORSTP: equ 0CA16H
MSG_MOTORTG: equ 0CA08H
MSG_READTAPE: equ 0C9F3H
MSG_SAVEEXEC: equ 0CAC8H
MSG_SAVEFILE: equ 0CA9AH
MSG_SAVEFROM: equ 0CAB1H
MSG_SAVESIZE: equ 0CADFH
MSG_SPC: equ 0CBD2H
MSG_SPCS: equ 0CBBFH
MSG_TAPEMARK: equ 0C9FEH
MSG_TIMERTST: equ 0CBEBH
MSG_TIMERVAL: equ 0CBFCH
MSG_TIMERVAL2: equ 0CC0CH
MSG_TIMERVAL3: equ 0CC1CH
MSG_TPMARK: equ 0CA22H
MSG_WDATA: equ 0CB62H
MSG_WGAPL: equ 0CB9CH
MSG_WGAPL2: equ 0CBADH
MSG_WGAPS: equ 0CB7DH
MSG_WGAPS2: equ 0CB8AH
MSG_WHDR: equ 0CB52H
MST1: equ 0C3EBH
MST2: equ 0C3F2H
MST3: equ 0C3FDH
MSTOP: equ 0C3D9H
NAME: equ 10F1H
NDE: equ 0C719H
OCTV: equ 11A0H
OKCHECK: equ 0CC28H
OKMSG: equ 0CC32H
ONTYO: equ 119FH
QER: equ 0C19EH
QVRFY: equ 0C66BH
QWRD: equ 0C5D0H
QWRI: equ 0C59CH
RATIO: equ 11A1H
RBY1: equ 0C2EAH
RBY2: equ 0C303H
RBY3: equ 0C30EH
RBYTE: equ 0C2DEH
RD1: equ 0C1C8H
RD2: equ 0C1E3H
RDD1: equ 0C1FBH
RDD2: equ 0C207H
RET1: equ 0C665H
RET2: equ 0C276H
RET3: equ 0C366H
RTAPE: equ 0C209H
RTP0: equ 0C256H
RTP1: equ 0C20EH
RTP2: equ 0C214H
RTP3: equ 0C22EH
RTP4: equ 0C276H
RTP5: equ 0C287H
RTP6: equ 0C2B6H
RTP7: equ 0C2B2H
RTP8: equ 0C285H
RTP9: equ 0C2B8H
SAVE: equ 0C11CH
SHORT: equ 0C55EH
SIZE: equ 1102H
SPCS2: equ 0C640H
SPCS3: equ 0C653H
SPV: equ 10F0H
START: equ 0BF6BH
STRGF: equ 1193H
SUMDT: equ 1197H
SWRK: equ 119DH
TATRB: equ 0CC5DH
TCOMNT: equ 0CC75H
TDTADR: equ 0CC71H
TEMPW: equ 119EH
TESTBUF: equ 0CC5DH
TESTEND: equ 0CDDEH
TESTSTART: equ 0CCDDH
TEXADR: equ 0CC73H
TIMERTST: equ 0C6FFH
TIMFG: equ 119CH
TIMIN: equ 0C86CH
TITLE: equ 0C96CH
TITLE_SAVE: equ 0C9A7H
TM0: equ 0C331H
TM1: equ 0C33AH
TM2: equ 0C33DH
TM3: equ 0C350H
TM4: equ 0C366H
TM4A: equ 0C36AH
TM4B: equ 0C372H
TMARK: equ 0C312H
TMCNT: equ 1195H
TNAME: equ 0CC5EH
TSIZE: equ 0CC6FH
TVF1: equ 0C699H
TVF2: equ 0C69FH
TVF3: equ 0C6B3H
TVRFY: equ 0C694H
WBY1: equ 0C6E1H
WBYTE: equ 0C6DBH
WRI1: equ 0C5AAH
WRI2: equ 0C5C7H
WRI3: equ 0C5CDH
WTAP1: equ 0C5F0H
WTAP2: equ 0C601H
WTAP3: equ 0C665H
WTAP3A: equ 0C613H
WTAPE: equ 0C5E6H

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software/asm/tapecheck.obj
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192
software/asm/tapecheck.sym
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@@ -1,192 +0,0 @@
?ER: equ 0C23BH
?RDD: equ 0C274H
?RDI: equ 0C249H
AMPM: equ 119BH
ATRB: equ 10F0H
BANKMSG: equ 0C888H
BITMSG: equ 0C880H
BUFER: equ 11A3H
CKS1: equ 0C495H
CKS2: equ 0C4A4H
CKS3: equ 0C4A8H
CKS4: equ 0C4ACH
CKSUM: equ 0C48FH
CLEAR1: equ 0C043H
COMNT: equ 1108H
CSMDT: equ 1199H
DLY1: equ 0C4B3H
DLY12: equ 0C4CAH
DLY12A: equ 0C4CDH
DLY1A: equ 0C4B5H
DLY2: equ 0C4BAH
DLY2A: equ 0C4BCH
DLY3: equ 0C4C1H
DONEMSG: equ 0C86CH
DPRNT: equ 1194H
DSPXY: equ 1171H
DTADR: equ 1104H
EDG0: equ 0C358H
EDG1: equ 0C350H
EDG2: equ 0C35EH
EDG3: equ 0C366H
EDGE: equ 0C34AH
EXADR: equ 1106H
FLASH: equ 118EH
FLPST: equ 118FH
FLSDT: equ 1192H
FLSST: equ 1191H
GAP: equ 0C4D4H
GAP1: equ 0C4E8H
GAP1A: equ 0C4EBH
GAP2: equ 0C4F0H
GAP3: equ 0C4F6H
GAPCK: equ 0C502H
GAPCK1: equ 0C514H
GAPCK2: equ 0C516H
GAPCK3: equ 0C526H
GETL1: equ 0C04DH
GETL2: equ 0C05BH
GRAM0: equ 0C07CH
GRAM1: equ 0C080H
GRAMINIT: equ 0C076H
GRPHPOS: equ 0C890H
IBUFE: equ 10F0H
INITGRPH: equ 0C018H
INITMEM: equ 0C03DH
KANAF: equ 1170H
L047D: equ 0C5A3H
L04C2: equ 0C5E8H
L04C4: equ 0C5EAH
LOA0: equ 0C16BH
LOAD: equ 0C165H
LONG: equ 0C542H
LOOP: equ 0C08EH
LOOP1: equ 0C093H
LOOP10: equ 0C15EH
LOOP11: equ 0C160H
LOOP1a: equ 0C09FH
LOOP1b: equ 0C0A5H
LOOP2: equ 0C0B6H
LOOP3: equ 0C0D4H
LOOP4: equ 0C104H
LOOP5: equ 0C10BH
LOOP6: equ 0C11DH
LOOP7: equ 0C12EH
LOOP8: equ 0C136H
LOOP9: equ 0C156H
MANG: equ 1173H
MEMTEST: equ 0C08CH
MEND: equ 0CA13H
MOT1: equ 0C425H
MOT2: equ 0C42CH
MOT3: equ 0C42EH
MOT4: equ 0C436H
MOT5: equ 0C459H
MOT7: equ 0C434H
MOT8: equ 0C44DH
MOT9: equ 0C456H
MOTOR: equ 0C413H
MSG1: equ 0C681H
MSG2: equ 0C683H
MSG3: equ 0C689H
MSGN7: equ 0C694H
MSGOK: equ 0C69EH
MSG_CHKSUM_MZ1: equ 0C7C0H
MSG_CHKSUM_MZ2: equ 0C7EEH
MSG_CHKSUM_TP1: equ 0C7D7H
MSG_CHKSUM_TP2: equ 0C805H
MSG_ERRCHKSUM: equ 0C6A2H
MSG_ERRWRITE: equ 0C6B1H
MSG_GAPCK: equ 0C6FDH
MSG_HELP: equ 0C83EH
MSG_LOADEXEC: equ 0C736H
MSG_LOADFILE: equ 0C708H
MSG_LOADFROM: equ 0C71FH
MSG_LOADSIZE: equ 0C74DH
MSG_MOTORSTP: equ 0C6E0H
MSG_MOTORTG: equ 0C6D2H
MSG_READTAPE: equ 0C6BDH
MSG_SAVEEXEC: equ 0C792H
MSG_SAVEFILE: equ 0C764H
MSG_SAVEFROM: equ 0C77BH
MSG_SAVESIZE: equ 0C7A9H
MSG_TAPEMARK: equ 0C6C8H
MSG_TPMARK: equ 0C6ECH
MST1: equ 0C47AH
MST2: equ 0C481H
MST3: equ 0C48CH
MSTOP: equ 0C468H
NAME: equ 10F1H
OCTV: equ 11A0H
OKCHECK: equ 0C85DH
OKMSG: equ 0C867H
ONTYO: equ 119FH
QER: equ 0C22DH
QVRFY: equ 0C5FEH
QWRD: equ 0C59BH
QWRI: equ 0C567H
RATIO: equ 11A1H
RBY1: equ 0C379H
RBY2: equ 0C392H
RBY3: equ 0C39DH
RBYTE: equ 0C36DH
RD1: equ 0C257H
RD2: equ 0C272H
RDD1: equ 0C28AH
RDD2: equ 0C296H
RET1: equ 0C5F8H
RET2: equ 0C305H
RET3: equ 0C3F5H
RTAPE: equ 0C298H
RTP0: equ 0C2E5H
RTP1: equ 0C29DH
RTP2: equ 0C2A3H
RTP3: equ 0C2BDH
RTP4: equ 0C305H
RTP5: equ 0C316H
RTP6: equ 0C345H
RTP7: equ 0C341H
RTP8: equ 0C314H
RTP9: equ 0C347H
SAVE: equ 0C1BAH
SHORT: equ 0C529H
SIZE: equ 1102H
SPV: equ 10F0H
START: equ 0C000H
STRGF: equ 1193H
SUMDT: equ 1197H
SWRK: equ 119DH
TATRB: equ 0C892H
TCOMNT: equ 0C8AAH
TDTADR: equ 0C8A6H
TEMPW: equ 119EH
TESTBUF: equ 0C892H
TESTEND: equ 0CA13H
TESTSTART: equ 0C912H
TEXADR: equ 0C8A8H
TIMFG: equ 119CH
TITLE: equ 0C81CH
TM0: equ 0C3C0H
TM1: equ 0C3C9H
TM2: equ 0C3CCH
TM3: equ 0C3DFH
TM4: equ 0C3F5H
TM4A: equ 0C3F9H
TM4B: equ 0C401H
TMARK: equ 0C3A1H
TMCNT: equ 1195H
TNAME: equ 0C893H
TSIZE: equ 0C8A4H
TVF1: equ 0C62CH
TVF2: equ 0C632H
TVF3: equ 0C646H
TVRFY: equ 0C627H
WBY1: equ 0C674H
WBYTE: equ 0C66EH
WRI1: equ 0C575H
WRI2: equ 0C592H
WRI3: equ 0C598H
WTAP1: equ 0C5BAH
WTAP2: equ 0C5CBH
WTAP3: equ 0C5F8H
WTAPE: equ 0C5B0H

2
software/mif/combined_mainmemory.mif
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@@ -12,7 +12,7 @@ CONTENT BEGIN
0060: 71 21 00 d8 18 03 c3 35 10 cd e3 09 21 79 03 3e;
0070: c3 32 38 10 22 39 10 3e 04 32 9e 11 cd be 02 cd;
0080: 09 00 11 00 01 df cd e5 02 3e ff 32 9d 11 21 00;
0090: e8 36 55 18 35 cd 09 00 3e 3e cd 12 00 11 a3 11;
0090: e8 36 55 18 35 cd 09 00 3e 2a cd 12 00 11 a3 11;
00a0: cd 03 00 1a 13 fe 0d 28 ec fe 4a 28 0e fe 4c 28;
00b0: 28 fe 46 28 12 fe 42 28 08 18 e8 cd 10 04 38 d5;
00c0: e9 3a 9d 11 2f 18 c4 21 00 f0 7e b7 20 c7 e9 fe;

4
software/mif/combined_mrom.mif
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@@ -2700,7 +2700,7 @@ a850: 4d 07 06 ff 21 f1 10 cd d8 0f 3e 16 cd 12 00 3e;
a860: 71 21 00 d8 18 03 c3 35 10 cd e3 09 21 79 03 3e;
a870: c3 32 38 10 22 39 10 3e 04 32 9e 11 cd be 02 cd;
a880: 09 00 11 00 01 df cd e5 02 3e ff 32 9d 11 21 00;
a890: e8 36 55 18 35 cd 09 00 3e 3e cd 12 00 11 a3 11;
a890: e8 36 55 18 35 cd 09 00 3e 2a cd 12 00 11 a3 11;
a8a0: cd 03 00 1a 13 fe 0d 28 ec fe 4a 28 0e fe 4c 28;
a8b0: 28 fe 46 28 12 fe 42 28 08 18 e8 cd 10 04 38 d5;
a8c0: e9 3a 9d 11 2f 18 c4 21 00 f0 7e b7 20 c7 e9 fe;
@@ -2956,7 +2956,7 @@ b850: 4d 07 06 ff 21 f1 10 cd d8 0f 3e 16 cd 12 00 3e;
b860: 71 21 00 d8 18 03 c3 35 10 cd e3 09 21 79 03 3e;
b870: c3 32 38 10 22 39 10 3e 04 32 9e 11 cd be 02 cd;
b880: 09 00 11 00 01 df cd 20 01 3e ff 32 9d 11 21 00;
b890: e8 36 55 18 35 cd 09 00 3e 3e cd 12 00 11 a3 11;
b890: e8 36 55 18 35 cd 09 00 3e 2a cd 12 00 11 a3 11;
b8a0: cd 03 00 1a 13 fe 0d 28 ec fe 4a 28 0e fe 4c 28;
b8b0: 28 fe 46 28 12 fe 42 28 08 18 e8 cd 10 04 38 d5;
b8c0: e9 3a 9d 11 2f 18 c4 21 00 f0 7e b7 20 c7 e9 fe;

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