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8 Commits
v1.1rc1 ... v1.00

Author SHA1 Message Date
eaw
6ec826a2a6 Add VERSION file for CI/CD release numbering 2026-03-14 13:03:48 +00:00
eaw
5460c51fad Update README from eaw.app website content 2026-03-14 10:06:50 +00:00
Philip Smart
314e4e0966 Updated .gitignore to remove assemble_rfs.sh, originally a temp file. 2026-01-17 11:12:40 +00:00
Philip Smart
517ee7cf88 Updates and bug fixes. DASM fix still outstanding 2026-01-07 09:17:16 +00:00
Philip Smart
a0bcabb125 Interim updates for use with SFD700 2023-11-08 16:04:14 +00:00
Philip Smart
942782091b Added Kuma80 and updates for MZ700 2023-07-14 22:14:53 +01:00
Philip Smart
4bbccf56fd Updates for inclusion of the MZ-1500 2023-05-24 09:14:37 +01:00
Philip Smart
e3b363df6e Build updates for FusionX 2023-05-10 09:55:29 +01:00
59 changed files with 6903 additions and 2889 deletions
Expand all files Collapse all files

13
.gitignore vendored
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@@ -74,7 +74,6 @@ roms/SHARP_MZ80A_RFS_IMAGE_1.img
roms/cmp
tools/Master0.z80
tools/Master1.z80
tools/assemble_rfs.sh
src/tools/.flashmmcfg.c.swo
src/tools/x
CPM/1M44/DSK/CPM_1M44_RFS_1.DSK
@@ -201,3 +200,15 @@ dz80.ini
full.asm
full.bin
MZ800_IOCS.ref
asm/c2
asm/sa1510.asm.prekuma
roms/test.rom
tools/cpmchattr
tools/cpmchmod
tools/cpmcp
tools/cpmls
tools/cpmrm
tools/fsck.cpm
tools/fsed.cpm
tools/mkfs.cpm
tools/share/

3
.gitmodules vendored Normal file
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@@ -0,0 +1,3 @@
[submodule "cpmtools"]
path = cpmtools
url = https://github.com/lipro-cpm4l/cpmtools.git

920
README.md vendored
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File diff suppressed because it is too large Load Diff

1
VERSION vendored Normal file
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@@ -0,0 +1 @@
1.00

1915
asm/cbios.asm
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File diff suppressed because it is too large Load Diff

52
asm/cbios_bank1.asm
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@@ -16,6 +16,10 @@
;- additional and different hardware. The SPI is now onboard the PCB and
;- not using the printer interface card.
;- Mar 2021 - Updates for the RFS v2.1 board.
;- Jun 2023 - Updates to accommodate the Kuma 40/80 upgrade. INTEN is permanently
;- enabled as PC2 is requisitioned to act as the 40/80 switch so ?MODE adjusted
;- to setup the 8253 timer with a long 655 second interrupt to get around the
;- problem where ?PRNT enables interrupts prior to the hook being setup.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -348,8 +352,18 @@ OPTBL: DB 001H
LD (HL),E ; Place current time in Counter 2
LD (HL),D
DEC HL
LD (HL),03BH ; Place divisor in Counter 1, = 315, thus 31500/315 = 100
LD (HL),001H
IF BUILD_MZ80A = 1
LD (HL),03BH ; Place divisor in Counter 1, = 315, thus 31500/315 = 100
LD (HL),001H
ENDIF
IF BUILD_MZ700 = 1
LD (HL),09CH ; Place divisor in Counter 1, = 156, thus 15611/156 = 100
LD (HL),000H
ENDIF
IF BUILD_MZ1500 = 1
LD (HL),09CH ; Place divisor in Counter 1, = 156, thus 15611/156 = 100
LD (HL),000H
ENDIF
NOP
NOP
NOP
@@ -377,11 +391,35 @@ OPTBL: DB 001H
; START OF KEYBOARD FUNCTIONALITY (INTR HANDLER SEPERATE IN CBIOS)
;-------------------------------------------------------------------------------
?MODE: LD HL,KEYPF
?MODE: ;
; 8255 PPI
;
LD HL,KEYPF
LD (HL),08AH
LD (HL),007H ; Set Motor to Off.
LD (HL),004H ; Disable interrupts by setting INTMSK to 0.
IF BUILD_KUMA = 0
LD (HL),004H ; Disable interrupts by setting INTMSK to 0.
ELSE
IF BUILD_80C = 1
LD (HL),005H ; Kuma upgrade, set display to 80 columns.
ELSE
LD (HL),004H ; Kuma upgrade, set display to 40 columns.
ENDIF
ENDIF
LD (HL),001H ; Set VGATE to 1.
;
; 8253 Timer.
;
LD HL,CONTF
LD (HL),074H ; Set Counter 1, read/load lsb first then msb, mode 2 rate generator, binary
LD (HL),0B0H ; Set Counter 2, read/load lsb first then msb, mode 0 interrupt on terminal count, binary
DEC HL
LD DE,0FFFFH ; 100Hz coming into Timer 2 from Timer 1, set divisor to maximum, ie. set interrupts per second.
LD (HL),E ; Place current time in Counter 2
LD (HL),D
DEC HL
LD (HL),03BH ; Place divisor in Counter 1, = 315, thus 31500/315 = 100Hz
LD (HL),001H
RET
; Method to check if a key has been pressed and stored in buffer..
@@ -451,6 +489,6 @@ GETKY2: LD A,(KEYCOUNT) ; No ke
;-------------------------------------------------------------------------------
; Align to end of bank.
ALIGN UROMADDR + 07F8h
ORG UROMADDR + 07F8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ALIGN UROMADDR + 07F7h
ORG UROMADDR + 07F7h
DB 021H,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFH

6
asm/cbios_bank2.asm
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@@ -1463,6 +1463,6 @@ RCP: LD HL,(CURSORPSAV) ; (curr
;-------------------------------------------------------------------------------
; Align to end of bank.
ALIGN UROMADDR + 07F8h
ORG UROMADDR + 07F8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ALIGN UROMADDR + 07F7h
ORG UROMADDR + 07F7h
DB 022H,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFH

6
asm/cbios_bank3.asm
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@@ -891,7 +891,7 @@ SDC_WRITE1: RET
;-------------------------------------------------------------------------------
; Align to end of bank.
ALIGN UROMADDR + 07F8h
ORG UROMADDR + 07F8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ALIGN UROMADDR + 07F7h
ORG UROMADDR + 07F7h
DB 023H,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFH

6
asm/cbios_bank4.asm
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@@ -636,6 +636,6 @@ DATAOVRMSG: DB "DISK ERROR - DATA OVERRUN", CR, NUL
CRCERRMSG: DB "DISK ERROR - CRC ERROR", CR, NUL
; Align to end of bank.
ALIGN UROMADDR + 07F8h
ORG UROMADDR + 07F8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ALIGN UROMADDR + 07F7h
ORG UROMADDR + 07F7h
DB 024H,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFH

19
asm/include/cpm_definitions.asm
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@@ -10,12 +10,13 @@
;- Copyright: (c) 2019-23 Philip Smart <philip.smart@net2net.org>
;-
;- History: Jan 2020 - Initial version.
; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the
; additional and different hardware. The SPI is now onboard the PCB and
; not using the printer interface card.
; Mar 2021 - Changes to work with the RFS v2.1 board.
;- May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the
;- additional and different hardware. The SPI is now onboard the PCB and
;- not using the printer interface card.
;- Mar 2021 - Changes to work with the RFS v2.1 board.
;- Apr 2021 - Removed ROM and RAM Drive functionality as it provided no performance or
;- use benefit over SD which are much larger and RW.
;- May 2023 - Updates to accommodate RFS use on a FusionX board.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -39,13 +40,19 @@ HW_SPI_ENA EQU 1 ; Set t
SW_SPI_ENA EQU 0 ; Set to 1 if software SPI is present on the RFS PCB v2 board.
PP_SPI_ENA EQU 0 ; Set to 1 if using the SPI interface via the Parallel Port, ie. for RFS PCB v1 which doesnt have SPI onboard.
; Build time options, only set to '1' to build, '0' to disable, only 1 can be set to '1'.
; Build time options, only set to '1' to build, '0' to disable, only set one 40C/80C at a time. Set KUMA 80C option if Kuma upgrade being targetted otherwise will default to 40/80 column card.
; IF BUILD_VERSION = 0
BUILD_80C EQU 1 ; Build for an MZ-80A with a 40/80 column card.
BUILD_40C EQU 0 ; Build for a standard 40 column MZ-80A.
BUILD_KUMA EQU 0 ; Enable support for the Kuma 40/80 column upgrade.
BUILD_MZ80A EQU 1 ; Build for the Sharp MZ-80A base hardware.
BUILD_MZ700 EQU 0 ; Build for the Sharp MZ-700 base hardware.
BUILD_MZ1500 EQU 0 ; Build for the Sharp MZ-1500 base hardware.
; ENDIF
; IF BUILD_VERSION = 1
;BUILD_80C EQU 0 ; Build for an MZ-80A with a 40/80 column card.
;BUILD_80C_KUMA EQU 0 ; If set, 80 column mode is provided by the Kuma upgrade and not the 40/80 column card.
;BUILD_40C EQU 1 ; Build for a standard 40 column MZ-80A.
; ENDIF
@@ -79,7 +86,7 @@ MAXDISKS EQU 7 ; Max n
KEYBUFSIZE EQU 16 ; Ensure this is a power of 2, max size 256.
; Debugging
ENADEBUG EQU 0 ; Enable debugging logic, 1 = enable, 0 = disable
ENADEBUG EQU 1 ; Enable debugging logic, 1 = enable, 0 = disable
;-----------------------------------------------

143
asm/include/macros.asm
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@@ -31,4 +31,145 @@ PAD: MACRO ?address
;
ALIGN_FIT8: MACRO ?size
ds (($ + ?size - 1) >> 8) != ($ >> 8) && (100H - ($ & 0FFH)) || 0
ENDM
ENDM
HWSELROM: MACRO
IF BUILD_ROMDISK = 1
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
HWSEL1: LD A,(BNKCTRLRST)
DJNZ HWSEL1 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting.
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
ENDIF ; 22 bytes.
; MODE_MZ1200 0
; MODE_MZ80A 0
; MODE_MZ700 1
; MODE_MZ80B 2
; MODE_MZ800 3
; MODE_MZ1500 4
; MODE_MZ2000 5
; MODE_MZ2200 6
IF BUILD_SFD700 = 1
IN A,(SFD700_MODE)
OR A
LD A,BNKDEFMROM_MZ80A ; Setup default MROM for an MZ80A, this is a 4K Window into the UROM at F000.
JR Z, HWSEL11
LD A,BNKDEFMROM_MZ700 ; Setup default MROM for an MZ700, this is a 4K Window into the UROM at F000.
HWSEL11: OUT (REG_FXXX),A
LD (ROMBK1),A
LD A,BNKDEFUROM ; Setup default UROM, this is a 2K Window into the UROM at E800 and contains the RFS.
OUT (REG_EXXX),A
LD (ROMBK2),A
NOP
ENDIF
ENDM
HWSELROM2: MACRO
IF BUILD_ROMDISK = 1
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
HWSEL2: LD A,(BNKCTRLRST)
DJNZ HWSEL2 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
NOP ; Nops to allocate space for missing LD (ROMCTL),A present in first bank.
NOP
NOP
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
NOP ; Nops to allocate space for Bank 0 JP to startup code.
NOP
NOP
ENDIF ; 25 bytes.
IF BUILD_SFD700 = 1
IN A,(SFD700_MODE)
OR A
LD A,BNKDEFMROM_MZ80A ; Setup default MROM for an MZ80A, this is a 4K Window into the UROM at F000.
JR Z,HWSEL21
LD A,BNKDEFMROM_MZ700 ; Setup default MROM for an MZ700, this is a 4K Window into the UROM at F000.
HWSEL21: OUT (REG_FXXX),A
LD A,BNKDEFUROM ; Setup default UROM, this is a 2K Window into the UROM at E800 and contains the RFS.
OUT (REG_EXXX),A
NOP ; Nops to allocate space to match RomDisk block.
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ENDIF
ENDM
; Macro to select which part of the FlashROM appears in the Monitor ROM 0000:0FFF Window.
; On the SFD700 board, for ease of coding as the Monitor ROM doesnt exist but the Floppy ROM F000:FFFF window does,
; then on this board, MROM refers to the F000:FFFF window when working with code which is compatible across the RomDisk, SFD700 etc..
HWSELMROM: MACRO
IF BUILD_ROMDISK = 1
LD (BNKSELMROM),A
ENDIF
IF BUILD_SFD700 = 1
OUT (REG_FXXX),A
ENDIF
ENDM
; Macro to perform the in-situ bank switch. RomDisk it is a simple register load, for the SFD700
; depending on the target bank, we need to bring in the complimentary FXXX bank as needed.
BNKSWSEL: MACRO
IF BUILD_ROMDISK = 1
LD (BNKSELUSER),A
ENDIF
IF BUILD_SFD700 = 1
OUT (REG_EXXX),A ; Execute active bank switch for E000:EFFF.
CP ROMBANK6 ; ROMBANK6/7 page in ROM from E300:FFFF
JR C,BNKSWJMP
INC A ; FXXX are 4K banks, EXXX are 2K banks.
JR BNKSWJMP2
BNKSWJMP: LD A,(ROMBK1) ; All other banks place the current active ROM into F000:FXXX space.
BNKSWJMP2: OUT (REG_FXXX),A
ENDIF
ENDM
; Macro to return from a bank switch.
BNKSWSELRET:MACRO
IF BUILD_ROMDISK = 1
LD (BNKSELUSER),A
ENDIF
IF BUILD_SFD700 = 1
OUT (REG_EXXX),A ; Execute active bank switch.
LD A,(ROMBK1) ; Ensure the current active ROM is switched to the F000:FXXX space.
OUT (REG_FXXX),A
ENDIF
ENDM
; Macro to select which part of the FlashROM appears in the User ROM E800:EFFF window.
HWSELUROM: MACRO
IF BUILD_ROMDISK = 1
LD (BNKSELUSER),A
ENDIF
IF BUILD_SFD700 = 1
OUT (REG_EXXX),A
ENDIF
ENDM
; Macro which is generally specific to the RomDisk, the code enables the Bank paging registers.
SETCODELTCH:MACRO
IF BUILD_ROMDISK = 1
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting.
ENDIF
IF BUILD_SFD700 = 1
NOP
NOP
NOP
NOP
NOP
ENDIF
ENDM

44
asm/include/msbasic_definitions.asm
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@@ -16,6 +16,8 @@
; Jun 2020 - Copied and strpped from TZFS for BASIC.
; Mar 2021 - Updates to run on v2.1 RFS board and provide SD card CLOAD/CSAVE and DIR
; along with bug fixes.
;- May 2023 - Updates to allow running on a FusionX board.
;- Jun 2023 - Updates to accommodate a Kuma 80 Column upgrade.
;
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -44,6 +46,9 @@
; Build options. Set just one to '1' the rest to '0'.
; NB: As there are now 4 versions and 1 or more need to be built, ie. MZ-80A and RFS version for RFS, a flag is set in the file
; BASIC_build.asm which configures the equates below for the correct build.
BUILD_KUMA EQU 1 ; Enable support for Kuma 40/80 column upgrade.
; MZ-80A Build
IF BUILD_VERSION = 0
BUILD_MZ80A EQU 1 ; Build for the standard Sharp MZ80A, no lower memory. Manually change MAXMEM above.
BUILD_RFS EQU 0 ; Build for standard RFS with SD enhancements.
@@ -52,22 +57,25 @@ BUILD_TZFS EQU 0 ; Build
BUILD_80C EQU 0
INCLUDE_ANSITERM EQU 1 ; Include the Ansi terminal emulation processor in the build.
ENDIF
; RFS 40 Build
IF BUILD_VERSION = 1
BUILD_MZ80A EQU 0
BUILD_RFS EQU 1
BUILD_RFSTZ EQU 0
BUILD_TZFS EQU 0
BUILD_80C EQU 1
INCLUDE_ANSITERM EQU 1 ; Include the Ansi terminal emulation processor in the build.
ENDIF
IF BUILD_VERSION = 2
BUILD_MZ80A EQU 0
BUILD_RFS EQU 1
BUILD_RFSTZ EQU 0
BUILD_TZFS EQU 0
BUILD_80C EQU 0
INCLUDE_ANSITERM EQU 1 ; Include the Ansi terminal emulation processor in the build.
ENDIF
; RFS 80 Build
IF BUILD_VERSION = 2
BUILD_MZ80A EQU 0
BUILD_RFS EQU 1
BUILD_RFSTZ EQU 0
BUILD_TZFS EQU 0
BUILD_80C EQU 1
INCLUDE_ANSITERM EQU 1 ; Include the Ansi terminal emulation processor in the build.
ENDIF
; RFS/TZ Build
IF BUILD_VERSION = 3
BUILD_MZ80A EQU 0
BUILD_RFS EQU 0
@@ -76,6 +84,7 @@ BUILD_TZFS EQU 0
BUILD_80C EQU 1
INCLUDE_ANSITERM EQU 1 ; Include the Ansi terminal emulation processor in the build.
ENDIF
; TZFS Build
IF BUILD_VERSION = 4
BUILD_MZ80A EQU 0
BUILD_RFS EQU 0
@@ -115,6 +124,11 @@ CTAPESAVE EQU 4
; Debugging
ENADEBUG EQU 0 ; Enable debugging logic, 1 = enable, 0 = disable
; RFS ROM addresses.
UROMADDR EQU 0E800H ; Start of User ROM Address space.
UROMBSTBL EQU UROMADDR + 020H ; Entry point to the bank switching table.
RFSJMPTABLE EQU UROMADDR + 000B0H ; Start of jump table.
;-----------------------------------------------
; CMT Object types.
;-----------------------------------------------
@@ -142,13 +156,13 @@ QVRFY EQU 0002Dh
;-------------------------------------------------------
; Function entry points in the RFS ROM.
;-------------------------------------------------------
CMT_RDINF EQU 0E886H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU 0E889H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU 0E88CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU 0E88FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU 0E892H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU 0E895H ; UROMADDR+95H - SD directory command.
CNV_ATOS EQU 0E898H ; UROMADDR+98H - Convert an ASCII string into Sharp ASCII
CMT_RDINF EQU RFSJMPTABLE + 06H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU RFSJMPTABLE + 09H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU RFSJMPTABLE + 0CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU RFSJMPTABLE + 0FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU RFSJMPTABLE + 12H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU RFSJMPTABLE + 15H ; UROMADDR+95H - SD directory command.
CNV_ATOS EQU RFSJMPTABLE + 18H ; UROMADDR+98H - Convert an ASCII string into Sharp ASCII
;-----------------------------------------------
; BASIC ERROR CODE VALUES

123
asm/include/rfs_definitions.asm
View File

@@ -18,6 +18,10 @@
;- processor all operations are done by the Z80 under RFS.
;- March 2021- Updates to accommodate the RFS v2.1 board along with back porting TZFS
;- developments.
;- May 2023 - Updates to accommodate RFS use on a FusionX board.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -40,7 +44,13 @@
HW_SPI_ENA EQU 1 ; Set to 1 if hardware SPI is present on the RFS PCB v2 board.
SW_SPI_ENA EQU 0 ; Set to 1 if software SPI is present on the RFS PCB v2 board.
PP_SPI_ENA EQU 0 ; Set to 1 if using the SPI interface via the Parallel Port, ie. for RFS PCB v1 which doesnt have SPI onboard.
FUSIONX_ENA EQU 1 ; Set to 1 if using RFS on the tranZPUter FusionX board.
FUSIONX_ENA EQU 0 ; Set to 1 if using RFS on the tranZPUter FusionX board.
KUMA80_ENA EQU 0 ; Target has Kuma 40/80 upgrade installed.
VIDEOMODULE_ENA EQU 0 ; Target has 40/80 column colour video module installed.
BUILD_ROMDISK EQU 0 ; RFS is built for the MZ-80A RomDisk card.
BUILD_SFD700 EQU 1 ; RFS is built for the SFD700 Floppy Disk Controller.
;BUILD_MZ80A EQU 0 ; RFS is customised to operate on an MZ-80A.
;BUILD_MZ700 EQU 1 ; RFS is customised to operate on an MZ-700.
; Debugging
ENADEBUG EQU 0 ; Enable debugging logic, 1 = enable, 0 = disable
@@ -50,9 +60,14 @@ ENADEBUG EQU 0 ; Enabl
;-----------------------------------------------
UROMADDR EQU 0E800H ; Start of User ROM Address space.
UROMBSTBL EQU UROMADDR + 020H ; Entry point to the bank switching table.
RFSJMPTABLE EQU UROMADDR + 00080H ; Start of jump table.
RFSJMPTABLE EQU UROMADDR + 000B0H ; Start of jump table.
FDCROMADDR EQU 0F000H
IF BUILD_SFD700 = 1
BNKDEFMROM_MZ80A EQU 0 ; Default MROM (FDC) selected, 1st 4k slot..
BNKDEFMROM_MZ700 EQU 1 ; Default MROM (FDC) selected, 2nd 4k slot..
BNKDEFUROM EQU 2 ; Default UROM (RFS) selected, starts at 8K.
ENDIF
;-----------------------------------------------
; Common character definitions.
@@ -140,30 +155,24 @@ BRKEY EQU 0001Eh
MELDY EQU 00030h
?TMST EQU 00033h
MONIT: EQU 00000h
SS: EQU 00089h
ST1: EQU 00095h
HLHEX EQU 00410h
_2HEX EQU 0041Fh
?MODE: EQU 0074DH
?KEY EQU 008CAh
PRNT3 EQU 0096Ch
?ADCN EQU 00BB9h
?DACN EQU 00BCEh
?DSP: EQU 00DB5H
?BLNK EQU 00DA6h
?DPCT EQU 00DDCh
PRTHL: EQU 003BAh
PRTHX: EQU 003C3h
HEX: EQU 003F9h
PRNT3 EQU 0096Ch
?ADCN EQU 00BB9h
?DSP: EQU 00DB5H
DPCT: EQU 00DDCh
DLY12: EQU 00DA7h
DLY12A: EQU 00DAAh
?RSTR1: EQU 00EE6h
MOTOR: EQU 006A3H
HEX: EQU 003F9h
CKSUM: EQU 0071AH
GAP: EQU 0077AH
WTAPE: EQU 00485H
MSTOP: EQU 00700H
MOTOR80A: EQU 006A3H
MOTOR700: EQU 0069FH
WTAPE80A: EQU 00485H
WTAPE700: EQU 0048AH
DLY12: EQU 00DA7h
;-----------------------------------------------
; Memory mapped ports in hardware.
@@ -189,6 +198,9 @@ INVDSP: EQU 0E014H
NRMDSP: EQU 0E015H
SCLDSP: EQU 0E200H
SCLBASE: EQU 0E2H
;
; RomDisk memory mapped ports
;
BNKCTRLRST: EQU 0EFF8H ; Bank control reset, returns all registers to power up default.
BNKCTRLDIS: EQU 0EFF9H ; Disable bank control registers by resetting the coded latch.
HWSPIDATA: EQU 0EFFBH ; Hardware SPI Data register (read/write).
@@ -222,6 +234,8 @@ BNKCTRLDEF EQU BBMOSI+SDCS+BBCLK ; Defau
SPI_OUT EQU 0FFH
SPI_IN EQU 0FEH
;
; RomDisk
;
DOUT_LOW EQU 000H
DOUT_HIGH EQU 004H
DOUT_MASK EQU 004H
@@ -233,6 +247,8 @@ CLOCK_MASK EQU 0FDH
CS_LOW EQU 000H
CS_HIGH EQU 001H
;
; tranZPUter SW
;
MMCFG EQU 060H ; Memory management configuration latch.
SETXMHZ EQU 062H ; Select the alternate clock frequency.
SET2MHZ EQU 064H ; Select the system 2MHz clock frequency.
@@ -252,6 +268,22 @@ MMIO4 EQU 0E4H ; MZ-70
MMIO5 EQU 0E5H ; MZ-700/MZ-800 Memory Management Set 5
MMIO6 EQU 0E6H ; MZ-700/MZ-800 Memory Management Set 6
MMIO7 EQU 0E7H ; MZ-700/MZ-800 Memory Management Set 7
;
; SFD700
;
REG_EXXX EQU 060H ; A write copies D6:0 into the EXXX page address register to set a uniform 4K block in the region E300:EFFF window.
REG_FXXX EQU 061H ; A write copies D6:0 into the FXXX page address register to set a uniform 4k block in the region F000:FFFF.
REG_MEMMODE EQU 062H ; A write with D0 = low enables FlashROM, D0 = high enables RAM.
SFD700_MODE EQU 063H ; FDC Interface card configured target mode.
FDC_CMD EQU 0D8H ; WD1773 Command Register.
FDC_STATUS EQU 0D8H ; WD1773 Status Register.
FDC_TRACK EQU 0D9H ; WD1773 Track Register.
FDC_SECTOR EQU 0DAH ; WD1773 Sector Register.
FDC_DATA EQU 0DBH ; WD1773 Data Register.
FDC_DRIVE EQU 0DCH ; FDC Drive Select. D2 = 1 to enable, D1:0 = FDC number. D7 = Motor Enable.
FDC_SIDE EQU 0DDH ; FDC Side Select. D0 = Side.
FDC_DDEN EQU 0DEH ; FDC Double Density Enable.
FDC_IRQ EQU 0DFH ; A write enables WD1773 interrupts, a read disables WD1773 interrupts.
;-----------------------------------------------
; CPLD Configuration constants.
@@ -320,6 +352,13 @@ RFSSECTSZ EQU 256
MROMSIZE EQU 4096
UROMSIZE EQU 2048
FNSIZE EQU 17
IF BUILD_ROMDISK = 1
MROMSTART: EQU 00000H
ENDIF
IF BUILD_SFD700 = 1
MROMSTART: EQU 0F000H
ENDIF
;
; Monitor ROM Jump Table definitions.
;
@@ -337,21 +376,41 @@ MROMLOAD: EQU MROMJMPTBL + 00006H
; 8-15 are reserved for CPM code in
; the User ROM bank.
;-----------------------------------------------
MROMPAGES EQU 8
IF BUILD_ROMDISK = 1
MROMPAGES EQU 8
ENDIF
IF BUILD_SFD700 = 1
MROMPAGES EQU 12 ; 10 Pages (8 but Bank6/7 are 2 pages) + 2 pages for ROMs
ENDIF
USRROMPAGES EQU 12 ; Monitor ROM : User ROM
ROMBANK0 EQU 0 ; MROM SA1510 40 Char : RFS Bank 0 - Main RFS Entry point and functions.
ROMBANK1 EQU 1 ; MROM SA1510 80 Char : RFS Bank 1 - Floppy disk controller and utilities.
ROMBANK2 EQU 2 ; CPM 2.2 CBIOS : RFS Bank 2 - SD Card controller and utilities.
ROMBANK3 EQU 3 ; RFS Utilities : RFS Bank 3 - Cmdline tools (Memory, Printer, Help)
ROMBANK4 EQU 4 ; MZ700 1Z-013A 40C : RFS Bank 4 - CMT Utilities.
ROMBANK5 EQU 5 ; MZ700-1Z-013A 80C : RFS Bank 5
ROMBANK6 EQU 6 ; MZ-80B IPL : RFS Bank 6
ROMBANK7 EQU 7 ; Free : RFS Bank 7 - Memory and timer test utilities.
ROMBANK8 EQU 8 ; : CBIOS Bank 1 - Utilities
ROMBANK9 EQU 9 ; : CBIOS Bank 2 - Screen / ANSI Terminal
ROMBANK10 EQU 10 ; : CBIOS Bank 3 - SD Card
ROMBANK11 EQU 11 ; : CBIOS Bank 4 - Floppy disk controller.
IF BUILD_ROMDISK = 1
ROMBANK0 EQU 0 ; MROM SA1510 40 Char : RFS Bank 0 - Main RFS Entry point and functions.
ROMBANK1 EQU 1 ; MROM SA1510 80 Char : RFS Bank 1 - Floppy disk controller and utilities.
ROMBANK2 EQU 2 ; CPM 2.2 CBIOS : RFS Bank 2 - SD Card controller and utilities.
ROMBANK3 EQU 3 ; RFS Utilities : RFS Bank 3 - Cmdline tools (Memory, Printer, Help)
ROMBANK4 EQU 4 ; MZ700 1Z-013A 40C : RFS Bank 4 - CMT Utilities.
ROMBANK5 EQU 5 ; MZ700-1Z-013A 80C : RFS Bank 5
ROMBANK6 EQU 6 ; MZ-80B IPL : RFS Bank 6
ROMBANK7 EQU 7 ; Free : RFS Bank 7 - Memory and timer test utilities.
ROMBANK8 EQU 8 ; : CBIOS Bank 1 - Utilities
ROMBANK9 EQU 9 ; : CBIOS Bank 2 - Screen / ANSI Terminal
ROMBANK10 EQU 10 ; : CBIOS Bank 3 - SD Card
ROMBANK11 EQU 11 ; : CBIOS Bank 4 - Floppy disk controller.
ENDIF
IF BUILD_SFD700 = 1
ROMBANK0 EQU 0 + BNKDEFUROM ; : RFS Bank 0 - Main RFS Entry point and functions.
ROMBANK1 EQU 1 + BNKDEFUROM ; : RFS Bank 1 - Floppy disk controller and utilities.
ROMBANK2 EQU 2 + BNKDEFUROM ; : RFS Bank 2 - SD Card controller and utilities.
ROMBANK3 EQU 3 + BNKDEFUROM ; : RFS Bank 3 - Cmdline tools (Memory, Printer, Help)
ROMBANK4 EQU 4 + BNKDEFUROM ; : RFS Bank 4 - CMT Utilities.
ROMBANK5 EQU 5 + BNKDEFUROM ; : RFS Bank 5
ROMBANK6 EQU 6 + BNKDEFUROM ; : RFS Bank 6
ROMBANK7 EQU 8 + BNKDEFUROM ; : RFS Bank 7 - Memory and timer test utilities.
ROMBANK8 EQU 10 + BNKDEFUROM ; : CBIOS Bank 1 - Utilities
ROMBANK9 EQU 11 + BNKDEFUROM ; : CBIOS Bank 2 - Screen / ANSI Terminal
ROMBANK10 EQU 12 + BNKDEFUROM ; : CBIOS Bank 3 - SD Card
ROMBANK11 EQU 13 + BNKDEFUROM ; : CBIOS Bank 4 - Floppy disk controller.
ENDIF
; MMC/SD command (SPI mode)
CMD0 EQU 64 + 0 ; GO_IDLE_STATE

4
asm/monitor_1z-013a.asm
View File

@@ -2,6 +2,8 @@
COLW: EQU 40 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 0
MODE80C:EQU 0 ; Configure for 80 column mode monitor.
KUMABIN:EQU 0 ; Generate original Kuma Monitor Binary (=1)
KUMA80: EQU 0 ; Kuma upgrade installed, enable 80 column mode.
INCLUDE "1z-013a.asm"

4
asm/monitor_80c_1z-013a.asm
View File

@@ -2,6 +2,8 @@
COLW: EQU 80 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
MODE80C:EQU 1
MODE80C:EQU 1 ; Configure for 80 column mode monitor.
KUMABIN:EQU 0 ; Generate original Kuma Monitor Binary (=1)
KUMA80: EQU 0 ; Kuma upgrade installed, enable 80 column mode.
INCLUDE "1z-013a.asm"

4
asm/monitor_80c_sa1510.asm
View File

@@ -3,6 +3,8 @@ COLW: EQU 80 ; Width of the display screen (ie. colum
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
SCRLW: EQU COLW / 8 ; Number of 8 byte regions in a line for hardware scroll.
MODE80C:EQU 1
MODE80C:EQU 1 ; Configure for 80 column mode monitor.
KUMABIN:EQU 0 ; Generate original Kuma Monitor Binary (=1)
KUMA80: EQU 1 ; Kuma upgrade installed, enable 80 column mode.
INCLUDE "sa1510.asm"

4
asm/monitor_80c_sa1510_hiload.asm
View File

@@ -3,6 +3,8 @@ COLW: EQU 80 ; Width of the display screen (ie. colum
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
SCRLW: EQU COLW / 8 ; Number of 8 byte regions in a line for hardware scroll.
MODE80C:EQU 1
MODE80C:EQU 1 ; Configure for 80 column mode monitor.
KUMABIN:EQU 0 ; Generate original Kuma Monitor Binary (=1)
KUMA80: EQU 0 ; Kuma upgrade installed, enable 80 column mode.
INCLUDE "sa1510_hiload.asm"

10
asm/monitor_kuma_sa1510.asm Normal file
View File

@@ -0,0 +1,10 @@
; Configurable parameters.
COLW: EQU 80 ; Width of the display screen (ie. columns).
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
SCRLW: EQU COLW / 8 ; Number of 8 byte regions in a line for hardware scroll.
MODE80C:EQU 0 ; Configure for 80 column mode monitor.
KUMABIN:EQU 1 ; Generate original Kuma Monitor Binary (=1)
KUMA80: EQU 0 ; Kuma upgrade installed, enable 80 column mode.
INCLUDE "sa1510.asm"

4
asm/monitor_sa1510.asm
View File

@@ -3,6 +3,8 @@ COLW: EQU 40 ; Width of the display screen (ie. colum
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
SCRLW: EQU COLW / 8 ; Number of 8 byte regions in a line for hardware scroll.
MODE80C:EQU 0
MODE80C:EQU 0 ; Configure for 80 column mode monitor.
KUMABIN:EQU 0 ; Generate original Kuma Monitor Binary (=1)
KUMA80: EQU 0 ; Kuma upgrade installed, enable 80 column mode.
INCLUDE "sa1510.asm"

4
asm/monitor_sa1510_hiload.asm
View File

@@ -3,6 +3,8 @@ COLW: EQU 40 ; Width of the display screen (ie. colum
ROW: EQU 25 ; Number of rows on display screen.
SCRNSZ: EQU COLW * ROW ; Total size, in bytes, of the screen display area.
SCRLW: EQU COLW / 8 ; Number of 8 byte regions in a line for hardware scroll.
MODE80C:EQU 0
MODE80C:EQU 0 ; Configure for 80 column mode monitor.
KUMABIN:EQU 0 ; Generate original Kuma Monitor Binary (=1)
KUMA80: EQU 0 ; Kuma upgrade installed, enable 80 column mode.
INCLUDE "sa1510_hiload.asm"

33
asm/msbasic.asm
View File

@@ -184,11 +184,17 @@ INIT80CHAR: IF BUILD_RFS = 1
LD A, 0FFH
LD (SPAGE), A
; Change to 80 character mode.
LD HL,DSPCTL ; Setup address of display control register latch.
LD A, 128 ; 80 char mode.
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
; 40/80 Column card upgrade?
IF BUILD_KUMA = 0
; Change to 80 character mode.
LD HL,DSPCTL ; Setup address of display control register latch.
LD A, 128 ; 80 char mode.
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
ELSE ; Kuma 80 column upgrade?
LD A, 05H ; Set the INTEN bit to enable 80 column mode.
LD (KEYPF),A
ENDIF
ELSE
LD A, ROMBANK0 ; Switch to 40char monitor SA-1510.
LD (ROMBK1),A
@@ -223,8 +229,11 @@ INITANSI: IF INCLUDE_ANSITERM = 1 ; If the ansi terminal emulator is buil
LD HL,00000H
CALL TIMESET
;
LD A,05H ; Enable interrupts at hardware level, this must be done before switching memory mode.
LD (KEYPF),A
; The Kuma upgrade uses INTEN to switch between 40/80 columns so ignore if target is for a Kuma upgrade.
IF BUILD_KUMA = 0
LD A,05H ; Enable interrupts at hardware level, this must be done before switching memory mode.
LD (KEYPF),A
ENDIF
;
MEMSW1: IF BUILD_TZFS+BUILD_RFSTZ > 0
LD A,TZMM_MZ700_2 ; Enable the full 64K memory range before starting BASIC initialisation.
@@ -6711,7 +6720,15 @@ ADD3216: ADD HL,BC
MODE: LD HL,KEYPF
LD (HL),08AH
LD (HL),007H ; Set Motor to Off.
LD (HL),004H ; Disable interrupts by setting INTMSK to 0.
IF BUILD_KUMA = 0
LD (HL),004H ; Disable interrupts by setting INTMSK to 0.
ELSE
IF BUILD_80C = 1
LD (HL),005H ; Set Kuma display to 80 column mode.
ELSE
LD (HL),004H ; Set Kuma display to 40 column mode.
ENDIF
ENDIF
LD (HL),001H ; Set VGATE to 1.
RET

534
asm/mz-1e05.asm Normal file
View File

@@ -0,0 +1,534 @@
; V1.10
;
; To compile use:
;
; AS80 [1.31] - Assembler for 8080/8085/Z80 microprocessor.
;
; Available from:
; - http://www.falstaff.demon.co.uk/cross.html
; - ftp://ftp.simtel.net/pub/simtelnet/msdos/crossasm/as80_131.zip
; - and many Simtel mirrors.
;
; as80 -i -l -n -x2 -v -z mz-1e05.asm
; Bring in additional resources.
INCLUDE "rfs_definitions.asm"
INCLUDE "macros.asm"
;
;----< MFM Minifloppy control >----
;
;
; Call condition
;
; Case of disk initialize
; Drive N = IX+0 (0 - 3)
;
;
; Case of sequential read & write
; Drive N = IX+0 (0 - 3)
;
; Sector addrs = IX+1,2 (0 - $045F) H C S
; (0 - 1119) -> 70 x 16 sectors -> 2 x 35 x 16
; Byte size = IX+3,4
; Address = IX+5,6
; Next track = IX+7
; Next sector = IX+8
; Start track = IX+9
; Start sector = IX+10
;
;
; I/O Port address
;
;
; Subroutine work
;
BPRO EQU 0CF00H
BUF EQU 011A3H
BPARA EQU BPRO - 23 ; BootPARAmeter
CMD EQU BPARA + 11 ; CoMmanD
MTFG EQU CMD + 1 ; MoTorFlaG
CLBF0 EQU MTFG + 1
CLBF1 EQU CLBF0 + 1
CLBF2 EQU CLBF1 + 1
CLBF3 EQU CLBF2 + 1
VRFCNT EQU CLBF3 + 1 ; VeRiFyCouNT
STAFG EQU VRFCNT + 1 ; STAtusFlaG
;
;
;--------< Ercode map >--------
;
; 50 : Not ready
; 41 : Data error
; Track 80 err
; Write protect err
; Seek err
; CRC err
; Lost data
; 54 : Unformat
; Recode not found
; 56 : Invalid data
;
;
ORG 0F000H
MZ_1E05: NOP
LD HL,000ADH
JR L_F007
FDX: EX (SP),HL
L_F007: LD (BPARA + 21),HL
XOR A
LD DE,0
CALL ?TMST
CALL FDCC ; FD i/o check
JP NZ,NOTIO
LD DE,BPARA ; destination address
LD HL,BOOT ; source address
LD BC,11 ; 11 bytes
LDIR ; copy
SJP: LD IX,BPARA
CALL BREAD ; read from drive 0, sector 0,
;
LD HL,BPRO ; compare this address
LD DE,IPLMC ; with the IPL MasterCode
LD B,7 ; this are 7 bytes : 3,'IPLPRO'
MCHECK: LD C,(HL)
LD A,(DE)
CP C
JP NZ,MASTE ; not equal than MasterError
INC HL
INC DE
DJNZ MCHECK
; else Master was found
LD DE,IPLM0 ; 'IPL IS LOADING'
RST 018H
LD DE,BPRO + 7 ; NAME
RST 018H
LD HL,(BPRO + 016H) ; TARGETADDRESS from BootBlock
LD A,H
OR L
JR NZ,L_F051 ; if it is != 0 than normal file
LD HL,(BPRO + 018H) ; TARGETADDRESS from BootBlock
LD A,H
OR L
JR Z,L_F057 ; if it is also 0 than ROM replace file
L_F051: XOR A ; else normal file,
LD HL,(BPRO + 018H) ; TARGETADDRESS from BootBlock
JR L_F05C
L_F057: LD A,0FFH ; target is at $0000, bankswitching is needed
LD HL,01200H ; for now use temporary buffer at $1200
L_F05C: LD (0CEFDH),A
LD (IX + 5),L ; set the TargetAddress
LD (IX + 6),H
LD HL,(BPRO + 014H) ; BYTE SIZE from BootBlock
LD (IX + 3),L
LD (IX + 4),H
LD HL,(BPRO + 01EH) ; START SECTOR from BootBlock
LD (IX + 1),L
LD (IX + 2),H
;
CALL BREAD
CALL MOFF
LD A,(0CEFDH)
CP 0FFH
JR NZ,L_F093
OUT (0E0H),A
LD HL,01200H ; SourceAddress
LD DE,(BPRO + 016H) ; TargetAddress
LD BC,(BPRO + 014H) ; ByteCounter
LDIR ; copy
L_F093: LD BC,00200H ; Default code
LD HL,(BPRO + 018H) ; TARGET/EXECUTION ADDRESS from BootBlock
JP (HL)
MASTE: CALL MOFF
LD DE,ERRM1 ; 'NOT MASTER'
JR ERRTR1
ERRTRT: CP 50
NOTIO: LD DE,IPLM3 ; 'MAKE READY FD'
JR Z,ERRTR1
LD DE,ERRM0 ; 'FD:LOADING ERROR'
ERRTR1: CALL 00009H
RST 018H
LD SP,010EEH
LD HL,(BPARA + 21)
EX (SP),HL
RET
;
;
; PARAMETER SETTING
;
IPLMC: DB 003H ; IPL MASTER FLAG
DB "IPLPRO"
BOOT: DB 000H ; DRIVE NO.
DW 00000H ; SECTOR ADDR.
DW 00100H ; IFM BYTE SIZE
DW BPRO ; IFM LOADING ADDR.
DW 00000H ; IX+7,8 (track 0, sector 0)
ERRM1: DB "FD:NOT MASTER",00DH
IPLM0: DB "IPL IS LOADING ",00DH
IPLM3: DB "MAKE READY FD",00DH
ERRM0: DB "FD:LOADING ERROR",00DH
FDCC: LD A,0A5H
LD B,A
OUT (FDC_TRACK),A
CALL DLY80U
IN A,(FDC_TRACK)
CP B
RET
L_F111: DB 000H, 000H
;
;
; READY CHECK
;
READY: LD A,(MTFG)
RRCA
CALL NC,MTON
LD A,(IX + 0) ; DRIVE NO SET
OR 084H
OUT (FDC_DRIVE),A ; DRIVE SELECT MOTON
XOR A
LD (CMD),A
CALL DLY60M
LD HL,0
REDY0: DEC HL
LD A,H
OR L
JR Z,REDY1
IN A,(FDC_CMD) ; STATUS GET
CPL
RLCA
JR C,REDY0
LD C,(IX + 0)
LD HL,CLBF0
LD B,000H
ADD HL,BC
BIT 0,(HL)
JR NZ,REDY2
CALL RCLB
SET 0,(HL)
REDY2: RET
REDY1: LD A,032H
JP ERJMP
;
;
; MOTOR ON
;
MTON: LD A,080H
OUT (FDC_DRIVE),A
LD B,16
MTD1: CALL DLY60M
DJNZ MTD1
LD A,1
LD (MTFG),A
RET
;
;
; SEEK TREATMENT
;
SEEK: LD A,01BH ; 1x = SEEK,
CALL CMDOT1 ; load head, no verify, max stepping rate
AND 099H
RET
;
;
; MOTOR OFF
;
MOFF: PUSH AF
CALL DLY1M ; 1000 US DELAY
XOR A
OUT (FDC_DRIVE),A
LD (CLBF0),A
LD (CLBF1),A
LD (CLBF2),A
LD (CLBF3),A
LD (MTFG),A
POP AF
RET
;
;
; RECALIBRATION
;
RCLB: LD A,00BH ; 0x = RESTORE (seek track 0)
CALL CMDOT1 ; load head, no verify, max stepping rate
AND 085H
XOR 004H
RET Z
L_F189: JP ERRORX
;
;
; COMMAND OUT ROUTINE
;
CMDOT1: LD (CMD),A
CPL
OUT (FDC_CMD),A
CALL BSYON
CALL DLY60M
IN A,(FDC_CMD)
CPL
LD (STAFG),A
RET
;
;
; BUSY AND WAIT
;
BSYON: PUSH DE
PUSH HL
CALL BSY0
BSYON2: LD HL,00000H
BSYON0: DEC HL
LD A,H
OR L
JR Z,BSYON1
IN A,(FDC_CMD)
RRCA
JR NC,BSYON0
POP HL
POP DE
RET
;
BSYON1: DEC E
JR NZ,BSYON2
BSYONE: LD A,029H
POP HL
POP DE
JP ERJMP
;
BSYOFF: PUSH DE
PUSH HL
CALL BSY0
BSYOF2: LD HL,00000H
BSYOF0: DEC HL
LD A,H
OR L
JR Z,BSYOF1
IN A,(FDC_CMD) ; Status Register
RRCA
JR C,BSYOF0
POP HL
POP DE
RET
;
BSYOF1: DEC E
JR NZ,BSYOF2
JR BSYONE
;
BSY0: CALL DLY80U
LD E,007H
RET
;
;
; SEQUENTIAL READ
;
BREAD: CALL CNVRT
CALL PARST1 ; HL = IX + 5,6 (TargetAddress)
RE8: CALL SIDST
CALL SEEK
JP NZ,ERJMP
CALL PARST2 ; C = DataRegister
DI ; disable interrupts
LD A,094H ; 9x = READ SECTOR, multiple records
CALL CMDOT2 ; compare for side 0, 15ms delay,
RE6: ; disable side select compare
LD B,0 ; ByteCounter = 0, to load 256 bytes of the sector
RE4: IN A,(FDC_CMD)
RRCA
JR C,RE3
RRCA
JR C,RE4
INI ; (HL) = in(C), B = B - 1 , HL = HL + 1
JR NZ,RE4
INC (IX + 8) ; NextSector = NextSector + 1
LD A,(IX + 8)
CP 011H ; if NextSector = 17
JR Z,L_F213 ; than end
DEC D ; else SectorCounter = SectorCounter - 1
JR NZ,RE6 ; if SectorCounter = 0
JR L_F214 ; than end
L_F213: DEC D
L_F214: CALL INTER
RE3: EI ; enable interrupts
IN A,(FDC_CMD)
CPL
LD (STAFG),A
AND 0FFH
JR NZ,ERRORX
CALL ADJ ; adjust sector and track
JP Z,REND
LD A,(IX + 7) ; track
JR RE8
REND: LD A,080H
OUT (FDC_DRIVE),A ; motor on
RET
;
;
; PARAMETER SET
;
;
PARST1: CALL READY
LD D,(IX + 4) ; D = bytes to read (highbyte) (256 bytes)
LD A,(IX + 3) ; A = bytes to read (lowbyte)
OR A ; if A = 0
JR Z,L_F23F ; than it's ok
INC D ; else read 256 bytes more (1 sector)
L_F23F: LD A,(IX + 10) ; NextSector = StartSector
LD (IX + 8),A
LD A,(IX + 9) ; NextTrack = StartTrack
LD (IX + 7),A
LD L,(IX + 5) ; HL = TargetAddress
LD H,(IX + 6)
RET
;
;
; SIZE SEEK SET
;
SIDST: SRL A
CPL
OUT (FDC_DATA),A
JR NC,L_F25D ; NC than Head 0
LD A,1 ; else Head 1
JR L_F25E
L_F25D: XOR A
L_F25E: CPL
OUT (FDC_SIDE),A ; set HeadSelect
RET
;
;
; TRACK & SECTOR SET
;
PARST2: LD C,FDC_DATA
LD A,(IX + 7) ; A = NextTrack
SRL A
CPL
OUT (FDC_TRACK),A
LD A,(IX + 8) ; A = NextSector
CPL
OUT (FDC_SECTOR),A
RET
;
;
; ADJUST SECT & TRACK
;
ADJ: LD A,(IX + 8) ; A = NextSector
CP 17 ; if NextSector = 17
JR NZ,L_F282 ; than the border is not reached
LD A,001H ; else
LD (IX + 8),A ; NextSector = 1
INC (IX + 7) ; NextTrack = NextTrack + 1
L_F282: LD A,D
OR A
RET
;
;
; COMMAND OUT & WAIT
;
CMDOT2: LD (CMD),A
CPL
OUT (FDC_CMD),A
CALL BSYOFF
RET
;
;
; FORCE INTERRUPT
;
INTER: LD A,0D8H
CPL
OUT (FDC_CMD),A
CALL BSYON
RET
;
;
; STATUS CHECK
;
ERRORX: LD A,(CMD)
CP 00BH ; Restore (seek track 0)
JR Z,ERCK1
CP 01BH ; Seek
JR Z,ERCK1
CP 0F4H ; Write track
JR Z,ERCK1
LD A,(STAFG)
BIT 7,A
JR NZ,ERRET
BIT 6,A
JR NZ,ERRET1
BIT 4,A
LD A,54
JR NZ,ERJMP
JR ERRET1
ERCK1: LD A,(STAFG)
BIT 7,A
JR NZ,ERRET
ERRET1: LD A,41
JR ERJMP
ERRET: LD A,50
ERJMP: CALL MOFF
JP ERRTRT
;
;
; SECTOR TO TRACK & SECTOR CONVERT
;
CNVRT: LD B,0 ; TrackCounter = 0
LD DE,16 ; 16 sectors per track
LD L,(IX + 1) ; HL = SectorAddress
LD H,(IX + 2)
XOR A
TRANS0: SBC HL,DE ; SectorAddress - SectorPerTrack
JR C,TRANS1 ; if < 0 than ready
INC B ; else TrackCounter = TrackCounter + 1
JR TRANS0 ; next try
TRANS1: ADD HL,DE ; undo the last substraction
LD H,B
INC L ; adjust sector (sector is 1..16 and not 0..15)
LD (IX + 9),H ; set StartTrack
LD (IX + 10),L ; set StartSector
RET
;
;
; TIME DELAY ( 1m & 60m & 80u )
;
DLY80U: PUSH DE
LD DE,15
JP DLYT
DLY1M: PUSH DE
LD DE,160
JP DLYT
DLY60M: PUSH DE
LD DE,8230
DLYT: DEC DE
LD A,E
OR D
JR NZ,DLYT
POP DE
RET
ALIGN 0FFF0H
ORG 0FFF0H
DB " 84.03.14 V1.0A"

3
asm/mz80afi.asm
View File

@@ -7,9 +7,10 @@
;
; on Thursday, 06 of February 2020 at 01:38 PM
;
i ; Bring in additional resources.
; Bring in additional resources.
INCLUDE "rfs_definitions.asm"
INCLUDE "macros.asm"
SS: EQU 00089h
;======================================

643
asm/rfs.asm
View File

@@ -10,17 +10,23 @@
;- Credits:
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
; or without the K64 I/O processor. RFS wont use the K64 processor all
; operations are done by the Z80 under RFS.
;- April 2021- Updates for the v2.1 RFS board.
;- History: v1.0 July 2019 - Merged 2 utilities to create this compilation.
;- v2.0 May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- v2.0 July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
;- or without the K64 I/O processor. RFS wont use the K64 processor all
;- operations are done by the Z80 under RFS.
;- v2.1 April 2021- Updates for the v2.1 RFS board.
;- v2.2 June 2023 - Updates for the Kuma 40/80 upgrade and FusionX.
;- v2.3 Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;- v2.31 Dec 2025 - Bug fixes. Disabled internal floppy control logic for SFD700 as it is not
;- needed, AFI ROM always needs to be present, especially for MZ-80A.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -40,6 +46,98 @@
; Bring in additional resources.
INCLUDE "rfs_definitions.asm"
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
ENDIF
; Monitor command table (SFD700). This table contains the list of recognised commands along with the
; handler function and bank in which it is located.
;
; 7 6 5:3 2:0
; END MATCH BANK SIZE
CMDTABLE2: IF BUILD_SFD700 = 1
DB 000H | 000H | 038H | 003H
DB "ASM" ; Assembler.
DW ASM_MAIN
DB 000H | 000H | 000H | 005H
DB "BASIC" ; Load and run BASIC SA-5510.
DW LOADBASIC
DB 000H | 000H | 020H | 001H
DB 'B' ; Bell.
DW SGX
DB 000H | 000H | 000H | 003H
DB "CPM" ; Load and run CPM.
DW LOADCPM
DB 000H | 000H | 018H | 002H
DB "CP" ; Copy Memory.
DW MCOPY
DB 000H | 000H | 018H | 001H
DB 'C' ; Clear Memory.
DW INITMEMX
DB 000H | 000H | 038H | 004H
DB "DASM" ; Disassembler.
DW DASM_MAIN
DB 000H | 000H | 018H | 001H
DB 'D' ; Dump Memory.
DW DUMPX
DB 000H | 000H | 008H | 001H
DB 'F' ; 'F' RFS Floppy boot code.
DW FDCK
DB 000H | 000H | 030H | 001H
DB 'H' ; Help screen.
DW HELP
DB 000H | 000H | 000H | 002H
DB "IR" ; List ROM directory.
DW DIRROM
DB 000H | 000H | 000H | 001H
DB 'J' ; Jump to address.
DW GOTOX
DB 000H | 000H | 020H | 004H
DB "LTNX" ; Load from CMT without auto execution.
DW LOADTAPENX
DB 000H | 000H | 020H | 002H
DB "LT" ; Load from CMT
DW LOADTAPE
DB 000H | 000H | 000H | 004H
DB "LRNX" ; Load from ROM without auto execution.
DW LOADROMNX
DB 000H | 000H | 000H | 002H
DB "LR" ; Load from ROM
DW LOADROM
DB 000H | 000H | 020H | 001H
DB "L" ; Original Load from CMT
DW LOADTAPE
DB 000H | 000H | 018H | 001H
DB 'M' ; Edit Memory.
DW MCORX
DB 000H | 000H | 018H | 001H
DB 'P' ; Printer test.
DW PTESTX
DB 000H | 000H | 020H | 001H
DB 'R' ; Memory test.
DW MEMTEST
DB 000H | 000H | 020H | 002H
DB "ST" ; Save to CMT
DW SAVEX
DB 000H | 000H | 020H | 001H
DB 'S' ; Save to CMT
DW SAVEX
DB 000H | 000H | 000H | 004H
DB "TEST" ; A test function used in debugging.
DW LOCALTEST
DB 000H | 000H | 020H | 001H
DB 'T' ; Timer test.
DW TIMERTST
DB 000H | 000H | 000H | 001H
DB 'V' ; Verify CMT Save.
DW VRFYX
DB 080H | 000H | 000H | 001H
ENDIF
IF BUILD_SFD700 = 1
ALIGN UROMADDR
ENDIF
;============================================================
;
@@ -48,20 +146,11 @@
;============================================================
ORG UROMADDR
;--------------------------------
; Common code spanning all banks.
;--------------------------------
ROMFS: NOP
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
ROMFS_0: LD A,(BNKCTRLRST)
DJNZ ROMFS_0 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting.
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
HWSELROM ; Select the first ROM.
JP ROMFS_1 ; Skip the reset vector.
JP 00000H ; Other banks will switch at this point thus forcing a full reset.
@@ -116,10 +205,10 @@ BKSW0_0: PUSH HL ; Place
LD HL, BKSWRET0 ; Place bank switchers return address on stack.
EX (SP),HL
LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it.
LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value.
BNKSWSEL
JP (HL) ; Jump to required function.
BKSWRET0: POP AF ; Get bank which called us.
LD (BNKSELUSER), A ; Return to that bank.
BNKSWSELRET
POP AF
RET ; Return to caller.
@@ -161,12 +250,11 @@ ROMFS_1:
ROMFS_2: LD (HL),A
INC HL
DJNZ ROMFS_2
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting.
LD A,(ROMBK1)
ROMFS_3: LD (BNKSELMROM),A ; start up.
SETCODELTCH ; On RomDisk setup coded latch to default.
LD A, (ROMBK1)
ROMFS_3: HWSELMROM ; start up.
LD A, (ROMBK2)
LD (BNKSELUSER),A
HWSELUROM
;-------------------------------------------------------------------------------
; START OF RFS INITIALISATION AND COMMAND ENTRY PROCESSOR FUNCTIONALITY.
@@ -174,42 +262,61 @@ ROMFS_3: LD (BNKSELMROM),A ; start
;
; Replacement command processor in place of the SA1510 command processor.
;
MONITOR: IF FUSIONX_ENA = 0
IN A,(CPLDINFO) ; See if a tranZPUter board is present.
AND 0E7H ; Mask out the CPLD Version and host HW.
LD C,A
CP 020H ; Upper bits specify the version, should be at least 1.
JR C,CHKTZ1
AND 007H ; Get Hardware, should be an MZ-80A for RFS.
CP MODE_MZ80A
LD A,C
JR Z,CHKTZ1
XOR A
CHKTZ1: AND 0E0H
MONITOR: IF FUSIONX_ENA+BUILD_SFD700 = 0
IN A,(CPLDINFO) ; See if a tranZPUter board is present.
AND 0E7H ; Mask out the CPLD Version and host HW.
LD C,A
CP 020H ; Upper bits specify the version, should be at least 1.
JR C,CHKTZ1
AND 007H ; Get Hardware, should be an MZ-80A for RFS.
CP MODE_MZ80A
LD A,C
JR Z,CHKTZ1
XOR A
CHKTZ1: AND 0E0H
ELSE
XOR A
XOR A
ENDIF
LD (TZPU), A ; Flag = 0 if no tranZPUter present otherwise contains version (1 - 15).
LD HL,DSPCTL ; Setup address of display control register latch.
IF VIDEOMODULE_ENA = 1
LD HL,DSPCTL ; Setup address of display control register latch.
ENDIF
;
XOR A ; Set the initial SDCFS active drive number.
LD (SDDRIVENO),A
;
LD A, (ROMBK1)
CP 1
JR Z, SET80CHAR
CP 0
JR NZ, SIGNON
IF BUILD_ROMDISK = 1
LD A, (ROMBK1) ; Is the 80column MZ-80A monitor active? Yes, set display as 80col.
CP 1
JR Z, SET80CHAR
CP 0
JR NZ, SIGNON
ENDIF
IF BUILD_SFD700 = 1 ; Ensure in 40 column mode.
ENDIF
;
SET40CHAR: LD A, 0 ; Using MROM in Bank 0 = 40 char mode.
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
SET40CHAR: IF VIDEOMODULE_ENA = 1
XOR A ; Using MROM in Bank 0 = 40 char mode.
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
ENDIF
IF KUMA80_ENA = 1 ; Kuma modification toggles the INTEN bit PC2 of the 8255 to switch mode, 0 = 40 column.
LD A,04H
LD (KEYPF),A
ENDIF
XOR A
LD (SCRNMODE), A
LD (SPAGE), A ; Allow MZ80A scrolling
JR SIGNON
SET80CHAR: LD A, 128 ; Using MROM in Bank 1 = 80 char mode.
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
SET80CHAR: IF VIDEOMODULE_ENA = 1
LD A, 128 ; Using MROM in Bank 1 = 80 char mode.
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
ENDIF
IF KUMA80_ENA = 1 ; Kuma modification toggles the INTEN bit PC2 of the 8255 to switch mode, 1 = 80 column.
LD A,05H
LD (KEYPF),A
ENDIF
LD A, 1
LD (SCRNMODE), A
LD A, 0FFH
@@ -233,21 +340,23 @@ SIGNON3: LD HL,PRINTMSG
; JR ST1X
; Initialise SD card, report any errors.
LD HL, SDINIT ; SD Card Initialisation
CALL BKSW0to2 ; Call the initialisation routine.
LD A,L
OR A ; 0 = No error.
JR Z,ST1X
IF BUILD_ROMDISK = 1
LD HL, SDINIT ; SD Card Initialisation
CALL BKSW0to2 ; Call the initialisation routine.
LD A,L
OR A ; 0 = No error.
JR Z,ST1X
; Place error code in C to print as a number and report with the error message.
ADD A,'0'
LD C,A
LD DE,MSGSDINITER
LD HL,PRINTMSG
CALL BKSW0to6
; Place error code in C to print as a number and report with the error message.
ADD A,'0'
LD C,A
LD DE,MSGSDINITER
LD HL,PRINTMSG
CALL BKSW0to6
ENDIF
; Command processor, table based.
; A line is inpt then a comparison made with entries in the table. If a match is found then the bank and function
; A line is input then a comparison made with entries in the table. If a match is found then the bank and function
; address are extracted and a call to the function @ given bank made. The commands can be of variable length
; but important to not that longer commands using the same letters as shorter commands must appear first in the table.
;
@@ -274,7 +383,12 @@ ST1X: CALL NL ; Comma
;
CMDCMP: XOR A ; Clear the result variable used by interbank calls. Some functions set this variable and we act on it.
LD (RESULT),A
LD HL,CMDTABLE
IF BUILD_ROMDISK = 1
LD HL,CMDTABLE
ENDIF
IF BUILD_SFD700 = 1
LD HL,CMDTABLE2 ; SFD700 Command table located in lower location.
ENDIF
CMDCMP0: LD DE,BUFER+1 ; First command byte after the * prompt.
LD A,(HL)
CP 000H
@@ -304,9 +418,9 @@ CMDCMP3: LD A,(HL) ; Comma
INC HL
LD H,(HL)
LD L,A
PUSH HL
PUSH HL ; Push the address of the function to be called.
LD (TMPADR),DE ; Store the key buffer location where arguments start.
LD A,C
LD A,C ; Get back command properties, ie. bank number
SRL A
SRL A
SRL A
@@ -318,7 +432,7 @@ CMDCMP3: LD A,(HL) ; Comma
LD DE,BKSW0to1 - BKSW0to0 ; DE is the number of bytes between bank switch calls.
OR A
JR Z,CMDCMP5
CMDCMP4: ADD HL,DE
CMDCMP4: ADD HL,DE ; Basically adding the bank size to the address to get ROM location.
DJNZ CMDCMP4
CMDCMP5: EX DE,HL ; Address of bank switch function into DE.
POP HL ; Get address of command into HL.
@@ -326,13 +440,18 @@ CMDCMP5: EX DE,HL ; Addre
PUSH BC ; Address to return to after command is executed.
PUSH DE ; Now jump to DE which will switch to the correct bank and execute function at HL.
LD DE,(TMPADR)
RET
RET ; Return to address in DE, which is the required bank.
CMDCMP6: LD DE,CMDCMPEND ; Put return address onto stack.
PUSH DE
LD DE,(TMPADR) ; For the current bank, just jump to the function.
JP (HL)
CMDNOCMP: LD DE,MSGBADCMD
CMDNOCMP: LD A,(BUFER+1) ; If nothing was entered, ignore line otherwise print questions to show command wasnt recognised.
OR A
JR Z,CMDCMPEND
CP 00DH
JR Z,CMDCMPEND
LD DE,MSGBADCMD
LD HL,PRINTMSG
CALL BKSW0to6
CMDCMPEND: LD A,(RESULT)
@@ -341,120 +460,122 @@ CMDCMPEND: LD A,(RESULT)
LD HL,(EXADR)
JP (HL)
; Monitor command table. This table contains the list of recognised commands along with the
; Monitor command table (ROMDISK). This table contains the list of recognised commands along with the
; handler function and bank in which it is located.
;
; 7 6 5:3 2:0
; END MATCH BANK SIZE
CMDTABLE: DB 000H | 000H | 000H | 002H ; Bit 2:0 = Command Size, 5:3 = Bank, 6 = Command match, 7 = Command table end.
DB "40" ; 40 Char screen mode.
DW SETMODE40
DB 000H | 000H | 000H | 002H
DB "80" ; 80 Char screen mode.
DW SETMODE80
;DB 000H | 000H | 000H | 004H
;DB "7008" ; Switch to 80 column MZ700 mode.
;DW SETMODE7008
;DB 000H | 000H | 000H | 003H
;DB "700" ; Switch to 40 column MZ700 mode.
;DW SETMODE700
DB 000H | 000H | 000H | 005H
DB "BASIC" ; Load and run BASIC SA-5510.
DW LOADBASIC
DB 000H | 000H | 020H | 001H
DB 'B' ; Bell.
DW SGX
DB 000H | 000H | 000H | 003H
DB "CPM" ; Load and run CPM.
DW LOADCPM
DB 000H | 000H | 018H | 002H
DB "CP" ; Copy Memory.
DW MCOPY
DB 000H | 000H | 018H | 001H
DB 'C' ; Clear Memory.
DW INITMEMX
DB 000H | 000H | 018H | 001H
DB 'D' ; Dump Memory.
DW DUMPX
DB 000H | 000H | 010H | 002H
DB "EC" ; Erase file.
DW ERASESD
DB 000H | 000H | 008H | 001H
DB 'F' ; RFS Floppy boot code.
DW FLOPPY
DB 000H | 000H | 008H | 001H
DB 0AAH ; Original Floppy boot code.
DW FDCK
DB 000H | 000H | 030H | 001H
DB 'H' ; Help screen.
DW HELP
DB 000H | 000H | 000H | 002H
DB "IR" ; List ROM directory.
DW DIRROM
DB 000H | 000H | 010H | 002H
DB "IC" ; List SD Card directory.
DW DIRSDCARD
DB 000H | 000H | 000H | 001H
DB 'J' ; Jump to address.
DW GOTOX
DB 000H | 000H | 020H | 004H
DB "LTNX" ; Load from CMT without auto execution.
DW LOADTAPENX
DB 000H | 000H | 020H | 002H
DB "LT" ; Load from CMT
DW LOADTAPE
DB 000H | 000H | 000H | 004H
DB "LRNX" ; Load from ROM without auto execution.
DW LOADROMNX
DB 000H | 000H | 000H | 002H
DB "LR" ; Load from ROM
DW LOADROM
DB 000H | 000H | 010H | 004H
DB "LCNX" ; Load from SDCARD without auto execution.
DW LOADSDCARDX
DB 000H | 000H | 010H | 002H
DB "LC" ; Load from SD CARD
DW LOADSDCARD
DB 000H | 000H | 020H | 001H
DB "L" ; Original Load from CMT
DW LOADTAPE
DB 000H | 000H | 018H | 001H
DB 'M' ; Edit Memory.
DW MCORX
DB 000H | 000H | 018H | 001H
DB 'P' ; Printer test.
DW PTESTX
DB 000H | 000H | 038H | 001H
DB 'R' ; Memory test.
DW MEMTEST
DB 000H | 000H | 018H | 004H
DB "SD2T" ; Copy SD Card to Tape.
DW SD2TAPE
DB 000H | 000H | 010H | 002H
DB "SC" ; Save to SD CARD
DW SAVESDCARD
DB 000H | 000H | 020H | 002H
DB "ST" ; Save to CMT
DW SAVEX
DB 000H | 000H | 020H | 001H
DB 'S' ; Save to CMT
DW SAVEX
DB 000H | 000H | 000H | 004H
DB "TEST" ; A test function used in debugging.
DW LOCALTEST
DB 000H | 000H | 018H | 004H
DB "T2SD" ; Copy Tape to SD Card.
DW TAPE2SD
DB 000H | 000H | 038H | 001H
DB 'T' ; Timer test.
DW TIMERTST
DB 000H | 000H | 000H | 001H
DB 'V' ; Verify CMT Save.
DW VRFYX
DB 000H | 000H | 000H | 001H
DB 'X' ; Exchange to hi load rom so DRAM = 0000:0CFFF
DW HIROM
DB 080H | 000H | 000H | 001H
CMDTABLE: IF BUILD_ROMDISK = 1
DB 000H | 000H | 000H | 002H ; Bit 2:0 = Command Size, 5:3 = Bank, 6 = Command match, 7 = Command table end.
DB "40" ; 40 Char screen mode.
DW SETMODE40
DB 000H | 000H | 000H | 002H
DB "80" ; 80 Char screen mode.
DW SETMODE80
;DB 000H | 000H | 000H | 004H
;DB "7008" ; Switch to 80 column MZ700 mode.
;DW SETMODE7008
;DB 000H | 000H | 000H | 003H
;DB "700" ; Switch to 40 column MZ700 mode.
;DW SETMODE700
DB 000H | 000H | 000H | 005H
DB "BASIC" ; Load and run BASIC SA-5510.
DW LOADBASIC
DB 000H | 000H | 020H | 001H
DB 'B' ; Bell.
DW SGX
DB 000H | 000H | 000H | 003H
DB "CPM" ; Load and run CPM.
DW LOADCPM
DB 000H | 000H | 018H | 002H
DB "CP" ; Copy Memory.
DW MCOPY
DB 000H | 000H | 018H | 001H
DB 'C' ; Clear Memory.
DW INITMEMX
DB 000H | 000H | 018H | 001H
DB 'D' ; Dump Memory.
DW DUMPX
DB 000H | 000H | 010H | 002H
DB "EC" ; Erase file.
DW ERASESD
DB 000H | 000H | 008H | 001H
DB 'F' ; 'F' RFS Floppy boot code.
DW FLOPPY
DB 000H | 000H | 008H | 001H
DB 0AAH ; 'f' Original Floppy boot code.
DW FDCK
DB 000H | 000H | 030H | 001H
DB 'H' ; Help screen.
DW HELP
DB 000H | 000H | 000H | 002H
DB "IR" ; List ROM directory.
DW DIRROM
DB 000H | 000H | 010H | 002H
DB "IC" ; List SD Card directory.
DW DIRSDCARD
DB 000H | 000H | 000H | 001H
DB 'J' ; Jump to address.
DW GOTOX
DB 000H | 000H | 020H | 004H
DB "LTNX" ; Load from CMT without auto execution.
DW LOADTAPENX
DB 000H | 000H | 020H | 002H
DB "LT" ; Load from CMT
DW LOADTAPE
DB 000H | 000H | 000H | 004H
DB "LRNX" ; Load from ROM without auto execution.
DW LOADROMNX
DB 000H | 000H | 000H | 002H
DB "LR" ; Load from ROM
DW LOADROM
DB 000H | 000H | 010H | 004H
DB "LCNX" ; Load from SDCARD without auto execution.
DW LOADSDCARDX
DB 000H | 000H | 010H | 002H
DB "LC" ; Load from SD CARD
DW LOADSDCARD
DB 000H | 000H | 020H | 001H
DB "L" ; Original Load from CMT
DW LOADTAPE
DB 000H | 000H | 018H | 001H
DB 'M' ; Edit Memory.
DW MCORX
DB 000H | 000H | 018H | 001H
DB 'P' ; Printer test.
DW PTESTX
DB 000H | 000H | 020H | 001H
DB 'R' ; Memory test.
DW MEMTEST
DB 000H | 000H | 018H | 004H
DB "SD2T" ; Copy SD Card to Tape.
DW SD2TAPE
DB 000H | 000H | 010H | 002H
DB "SC" ; Save to SD CARD
DW SAVESDCARD
DB 000H | 000H | 020H | 002H
DB "ST" ; Save to CMT
DW SAVEX
DB 000H | 000H | 020H | 001H
DB 'S' ; Save to CMT
DW SAVEX
DB 000H | 000H | 000H | 004H
DB "TEST" ; A test function used in debugging.
DW LOCALTEST
DB 000H | 000H | 018H | 004H
DB "T2SD" ; Copy Tape to SD Card.
DW TAPE2SD
DB 000H | 000H | 020H | 001H
DB 'T' ; Timer test.
DW TIMERTST
DB 000H | 000H | 000H | 001H
DB 'V' ; Verify CMT Save.
DW VRFYX
DB 000H | 000H | 000H | 001H
DB 'X' ; Exchange to hi load rom so DRAM = 0000:0CFFF
DW HIROM
DB 080H | 000H | 000H | 001H
ENDIF
;-------------------------------------------------------------------------------
; END OF RFS INITIALISATION AND COMMAND ENTRY PROCESSOR FUNCTIONALITY.
@@ -491,29 +612,47 @@ HEXIYX2: POP AF ; Waste
;
;====================================
HIROM: LD A, (MEMSW) ; Swap ROM into high range slot.
LD A, ROMBANK2
LD (ROMBK1),A ; Save bank being enabled.
LD (BNKSELMROM),A ; Switch to the hiload rom in bank 2.
JP 0C000H
HIROM: IF BUILD_ROMDISK = 1
LD A, (MEMSW) ; Swap ROM into high range slot.
LD A, ROMBANK2
LD (ROMBK1),A ; Save bank being enabled.
HWSELMROM ; Switch to the hiload rom in bank 2.
JP 0C000H
ENDIF
SETMODE40: LD A, ROMBANK0 ; Switch to 40Char monitor.
LD (ROMBK1),A
LD (BNKSELMROM),A
LD HL,DSPCTL ; Setup address of display control register latch.
LD A, 0
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
JP MONIT
SETMODE40: IF BUILD_ROMDISK = 1
LD A, ROMBANK0 ; Switch to 40Char monitor.
LD (ROMBK1),A
HWSELMROM
IF VIDEOMODULE_ENA = 1
LD HL,DSPCTL ; Setup address of display control register latch.
LD A, 0
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
ENDIF
IF KUMA80_ENA = 1 ; Kuma80 modification uses INTEN on PC@ of 8255, 0 = 40 column.
LD A,04H
LD (KEYPF),A
ENDIF
JP MONIT
ENDIF
SETMODE80: LD A, ROMBANK1 ; Switch to 80char monitor.
LD (ROMBK1),A
LD (BNKSELMROM),A
LD HL,DSPCTL ; Setup address of display control register latch.
LD A, 128
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
JP MONIT
SETMODE80: IF BUILD_ROMDISK = 1
LD A, ROMBANK1 ; Switch to 80char monitor.
LD (ROMBK1),A
HWSELMROM
IF VIDEOMODULE_ENA = 1
LD HL,DSPCTL ; Setup address of display control register latch.
LD A, 128
LD E,(HL) ; Dummy operation to enable latch write via multivibrator.
LD (HL), A
ENDIF
IF KUMA80_ENA = 1 ; Kuma80 modification uses INTEN on PC@ of 8255, 0 = 40 column.
LD A,05H
LD (KEYPF),A
ENDIF
JP MONIT
ENDIF
NOTZPU: LD DE,MSGNOTZINST ; No tranZPUter installed.
LD HL,PRINTMSG
@@ -612,8 +751,10 @@ _PRTDBG: IF ENADEBUG = 1
PUSH DE
PUSH BC
PUSH AF
LD A,(ROMBK1)
LD (BNKSELMROM),A ; Set the MROM bank back to original.
IF BUILD_ROMDISK = 1
LD A,(ROMBK1)
HWSELMROM ; Set the MROM bank back to original.
ENDIF
CALL PRTHL ; HL
LD A, ' '
CALL PRNT
@@ -638,8 +779,10 @@ _PRTDBG: IF ENADEBUG = 1
CALL PRNT
; CALL NL
; CALL GETKY
LD A,(WRKROMBK1)
LD (BNKSELMROM),A ; Set the MROM bank back to scanned bank.
IF BUILD_ROMDISK = 1
LD A,(WRKROMBK1)
HWSELMROM ; Set the MROM bank back to scanned bank.
ENDIF
POP AF
POP BC
POP DE
@@ -651,8 +794,10 @@ _PRTMZF: PUSH BC
PUSH DE
PUSH HL
;
LD A,(ROMBK1) ; Ensure main MROM is switched in.
LD (BNKSELMROM),A
IF BUILD_ROMDISK = 1
LD A,(ROMBK1) ; Ensure main MROM is switched in.
HWSELMROM
ENDIF
;
LD A,(SCRNMODE)
CP 0
@@ -718,15 +863,16 @@ PRTMZF2: LD L,A
PRTMZF3: XOR A
PRTMZF4: OR A
PUSH AF
LD A, (WRKROMBK1)
LD (BNKSELMROM),A
IF BUILD_ROMDISK = 1
LD A, (WRKROMBK1)
HWSELMROM
ENDIF
POP AF
POP HL
POP DE
POP BC
RET
; Method to list the directory of the ROM devices.
;
DIRROM: ;DI ; Disable interrupts as we are switching out the main rom.
@@ -742,23 +888,25 @@ DIRROM: ;DI ; Disab
LD D,0 ; File numbering start.
;
; Get directory of User ROM.
; Get directory of User ROM (RomDisk).
;
LD A,ROMBANK3
LD (WRKROMBK1),A
LD (BNKSELMROM),A
CALL DIRMROM
IF BUILD_ROMDISK = 1
LD A,ROMBANK3
LD (WRKROMBK1),A
HWSELMROM
CALL DIRMROM
ENDIF
;
; Scan MROM Bank
; B = Bank Page
; C = Block in page
;
LD B,MROMPAGES ; First 8 pages are reserved in MROM bank.
LD B,MROMPAGES ; First set of pages are reserved in MROM bank.
LD C,0 ; Block in page.
;
DIRNXTPG: LD A,B
LD (WRKROMBK1), A
LD (BNKSELMROM),A ; Select bank.
HWSELMROM ; Select bank.
PUSH BC ; Preserve bank count/block number.
PUSH DE ; Preserve file numbering.
@@ -771,7 +919,7 @@ DIRNXTPG: LD A,B
ENDIF
LD B,A
LD C,0
LD HL,RFS_ATRB ; Add block offset to get the valid block address.
LD HL,MROMSTART ; Add block offset to get the valid block address.
ADD HL,BC
CALL ISMZF
POP DE
@@ -793,7 +941,7 @@ DIRNXTPG2: LD A,B
JR NZ, DIRNXTPG
DIRNXTPGX: LD A,(ROMBK1)
LD (BNKSELMROM),A ; Set the MROM bank back to original.
HWSELMROM ; Set the MROM bank back to original.
;EI ; No need to block interrupts now as MROM bank restored.
RET ; End of scan, return to monitor
@@ -820,14 +968,14 @@ FINDMZF: PUSH DE
; C = Block in page
;
FINDMZF0: POP DE ; Get file sequence number in D.
LD B,MROMPAGES ; First 4 pages are reserved in User ROM bank.
LD B,MROMPAGES ; First set of pages are reserved in User ROM bank.
LD C,0 ; Block in page.
FINDMZF1: LD A,B
LD (WRKROMBK1), A
LD (BNKSELMROM),A ; Select bank.
HWSELMROM ; Select bank.
FINDMZF2: PUSH BC ; Preserve bank count/block number.
PUSH DE ; Preserve file numbering.
LD HL,RFS_ATRB ; Add block offset to get the valid block.
LD HL,MROMSTART ; Add block offset to get the valid block.
LD A,C
IF RFSSECTSZ >= 512
RLCA
@@ -843,7 +991,7 @@ FINDMZF2: PUSH BC ; Prese
POP DE
POP BC
LD A,(ROMBK1)
LD (BNKSELMROM),A ; Set the MROM bank back to original.
HWSELMROM ; Set the MROM bank back to original.
JR NZ, FINDMZF4 ; Z set if we found an MZF record.
INC HL ; Save address of filename.
PUSH HL
@@ -864,7 +1012,7 @@ FINDMZF3: POP HL
LD DE,(TMPADR) ; Original DE put onto stack, original filename into HL
LD BC,FNSIZE
LD A,(WRKROMBK1)
LD (BNKSELMROM),A ; Select correct bank for comparison.
HWSELMROM ; Select correct bank for comparison.
CALL CMPSTRING
POP BC
POP DE
@@ -885,7 +1033,7 @@ FINDMZF5: LD A,B
FINDMZFYES: ; Flag set by previous test.
FINDMZFNO: PUSH AF
LD A,(ROMBK1)
LD (BNKSELMROM),A ; Set the MROM bank back to original.
HWSELMROM ; Set the MROM bank back to original.
POP AF
RET
@@ -901,17 +1049,18 @@ LOADROM1: ;DI
PUSH HL ; Preserve execute flag.
EX DE,HL ; User ROM expects HL to have the filename pointer.
PUSH HL ; Save pointer to filename for FINDMZF in Monitor ROM.
; D = File sequence number.
LD D,0 ; File numbering start.
;
LD A,ROMBANK3 ; Activate the RFS Utilities MROM bank.
LD (WRKROMBK1), A
LD (BNKSELMROM),A
CALL MFINDMZF ; Try and find the file in User ROM via MROM utility.
POP HL
JR Z,MROMLOAD0
IF BUILD_ROMDISK = 1
PUSH HL ; Save pointer to filename for FINDMZF in Monitor ROM.
LD A,ROMBANK3 ; Activate the RFS Utilities MROM bank.
LD (WRKROMBK1), A
HWSELMROM
CALL MFINDMZF ; Try and find the file in User ROM via MROM utility.
POP HL
JR Z,MROMLOAD0
ENDIF
;
CALL FINDMZF ; Find the bank and block where the file resides. HL = filename.
JR Z, LROMLOAD
@@ -921,13 +1070,13 @@ LOADROM1: ;DI
MROMLOAD0: PUSH BC ; Preserve bank and block where MZF file found.
PUSH AF
LD A,(ROMBK1) ; Page in monitor so we can print a message.
LD (BNKSELMROM),A
HWSELMROM
LD DE,MSGLOAD+1 ; Skip initial CR.
LD BC,NAME
LD HL,PRINTMSG
CALL BKSW0to6
LD A,(WRKROMBK1) ; Revert to MROM bank to load the application.
LD (BNKSELMROM),A
HWSELMROM
POP AF
POP BC
;
@@ -936,7 +1085,7 @@ MROMLOAD0: PUSH BC ; Prese
LROMNTFND: POP HL ; Dont need execute flag anymore so waste it.
LD A,(ROMBK1)
LD (BNKSELMROM),A
HWSELMROM
LD HL,PRINTMSG
LD DE,MSGNOTFND ; Not found
CALL BKSW0to6
@@ -948,7 +1097,7 @@ LOADROMEND:;EI
;
LROMLOAD: PUSH BC
;
PUSH BC
PUSH BC ; Print Loading <file>
LD DE,MSGLOAD+1
LD BC,NAME
LD HL,PRINTMSG
@@ -957,10 +1106,10 @@ LROMLOAD: PUSH BC
;
LD A,B
LD (WRKROMBK1),A
LD (BNKSELMROM),A
HWSELMROM
;
LD DE, IBUFE ; Copy the header into the work area.
LD HL, 00000h ; Add block offset to get the valid block.
LD HL, MROMSTART ; Add block offset to get the valid block.
LD A,C
IF RFSSECTSZ >= 512
RLCA
@@ -988,10 +1137,10 @@ LROMLOAD: PUSH BC
; C = Block
LROMLOAD2: LD A, B
LD (WRKROMBK1), A
LD (BNKSELMROM),A
HWSELMROM
LROMLOAD3: PUSH BC
LD HL, 00000h
LD HL, MROMSTART
LD A, C
IF RFSSECTSZ >= 512
RLCA
@@ -1040,7 +1189,7 @@ LROMLOAD7: LD A, B
LROMLOAD8: POP BC
LROMLOAD5: POP HL ; Retrieve execute flag.
LD A,(ROMBK1)
LD (BNKSELMROM),A ; Set the MROM bank back to original.
HWSELMROM ; Set the MROM bank back to original.
LD A,L ; Autoexecute turned off?
CP 0FFh
JP Z,LROMLOAD9 ; Go back to monitor if it has been, else execute.
@@ -1331,12 +1480,16 @@ DEFAULTFNE: EQU $
;
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0AAh
IF BUILD_SFD700 = 1
ALIGN 0F000H
ENDIF
MEND:
;
; Include all other banks which make up the RFS User cited ROM.
; Include all other banks which make up the RFS User sited ROM.
;
INCLUDE "rfs_bank1.asm"
INCLUDE "rfs_bank2.asm"

718
asm/rfs_bank1.asm
View File

@@ -11,13 +11,16 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; Mar 2023 - Fixed Floppy bug where the driver letter entered wasnt recognised.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Mar 2023 - Fixed Floppy bug where the driver letter entered wasnt recognised.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -34,31 +37,25 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK1"
ALIGN UROMADDR
ENDIF
;============================================================
;
; USER ROM BANK 1 - Floppy Disk Controller functions.
;
;============================================================
ORG UROMADDR
ORG UROMADDR
;--------------------------------
; Common code spanning all banks.
;--------------------------------
NOP
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
ROMFS1_0: LD A,(BNKCTRLRST)
DJNZ ROMFS1_0 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
NOP
NOP
NOP
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
NOP
NOP
NOP
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
HWSELROM2 ; Select the first ROM page.
;
; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H.
JP 00000H ; This is for safety!!
@@ -113,10 +110,10 @@ BKSW1_0: PUSH HL ; P
LD HL, BKSWRET1 ; Place bank switchers return address on stack.
EX (SP),HL
LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it.
LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value.
BNKSWSEL
JP (HL) ; Jump to required function.
BKSWRET1: POP AF ; Get bank which called us.
LD (BNKSELUSER), A ; Return to that bank.
BNKSWSELRET
POP AF
RET
@@ -142,369 +139,371 @@ FDCKROM: LD A,(0F000h)
OR A
RET
FLOPPY: PUSH DE ; Preserve pointer to input buffer.
LD DE,BPARA ; Copy disk parameter block into RAM work area. (From)
LD HL,PRMBLK ; (To)
LD BC,0000BH ; 11 bytes of config data.
LDIR ; BC=0, HL=F0E8, DE=1013
POP DE ; init 1001-1005, port $DC mit $00
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
CP 00Dh ;
JR NZ,GETBOOTDSK ;
CALL DSKINIT ; Initialise disk and flags.
L000F: LD DE,MSGBOOTDRV ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,011A3H ;
CALL GETL ;
LD A,(DE) ;
CP 01BH ; BREAK pressed?
JP Z,SS ;
LD HL,19 ; Check input value is in range 1-4.
ADD HL,DE ;
LD A,(HL) ;
CP 00DH ;
JR Z,L003A ;
GETBOOTDSK:CALL HEX ; Convert number to binary
JR C,L000F ; If illegal, loop back and re-prompt.
DEC A ;
CP 004H ; Check in range, if not loop back.
JR NC,L000F ;
LD (BPARA),A ; Store in parameter block.
L003A: LD IX,BPARA ; Point to drive number.,
CALL DSKREAD ; Read sector 1 of trk 0
LD HL,0CE00H ; Now compare the first 7 bytes of what was read to see if this is a bootable disk.
LD DE,DSKID ;
LD B,007H ;
L0049: LD C,(HL) ;
LD A,(DE) ;
CP C ;
JP NZ,L008C ; If NZ then this is not a master disk, ie not bootable, so error exit with message.
INC HL ;
INC DE ;
DJNZ L0049 ;
LD DE,MSGIPLLOAD ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,0CE07H ; Program name stored at 8th byte in boot sector.
LD HL,PRTFN
CALL BKSW1to6
LD HL,(0CE16H) ; Get the load address
LD (IX+005H),L ; And store in parameter block at 100D/100E
LD (IX+006H),H ;
INC HL
DEC HL
JR NZ, NOTCPM ; If load address is 0 then where loading CPM.
; LD A,(MEMSW) ; Page out ROM.
NOTCPM: LD HL,(0CE14H) ; Get the size
LD (IX+003H),L ; And store in parameter block at 100B/100C
LD (IX+004H),H ;
LD HL,(0CE1EH) ; Get logical sector number
LD (IX+001H),L ; And store in parameter block at 1009/100A
LD (IX+002H),H ;
CALL DSKREAD ; Read the required data and store in memory.
CALL DSKINIT ; Reset the disk ready for next operation.
LD HL,(0CE18H) ; Get the execution address
JP (HL) ; And execute.
FLOPPY: IF BUILD_ROMDISK = 1
PUSH DE ; Preserve pointer to input buffer.
LD DE,BPARA ; Copy disk parameter block into RAM work area. (From)
LD HL,PRMBLK ; (To)
LD BC,0000BH ; 11 bytes of config data.
LDIR ; BC=0, HL=F0E8, DE=1013
POP DE ; init 1001-1005, port $DC mit $00
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
CP 00Dh ;
JR NZ,GETBOOTDSK ;
CALL DSKINIT ; Initialise disk and flags.
L000F: LD DE,MSGBOOTDRV ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,011A3H ;
CALL GETL ;
LD A,(DE) ;
CP 01BH ; BREAK pressed?
JP Z,ST1X ;
LD HL,19 ; Check input value is in range 1-4.
ADD HL,DE ;
LD A,(HL) ;
CP 00DH ;
JR Z,L003A ;
GETBOOTDSK: CALL HEX ; Convert number to binary
JR C,L000F ; If illegal, loop back and re-prompt.
DEC A ;
CP 004H ; Check in range, if not loop back.
JR NC,L000F ;
LD (BPARA),A ; Store in parameter block.
L003A: LD IX,BPARA ; Point to drive number.,
CALL DSKREAD ; Read sector 1 of trk 0
LD HL,0CE00H ; Now compare the first 7 bytes of what was read to see if this is a bootable disk.
LD DE,DSKID ;
LD B,007H ;
L0049: LD C,(HL) ;
LD A,(DE) ;
CP C ;
JP NZ,L008C ; If NZ then this is not a master disk, ie not bootable, so error exit with message.
INC HL ;
INC DE ;
DJNZ L0049 ;
LD DE,MSGIPLLOAD ;
LD HL,PRINTMSG
CALL BKSW1to6
LD DE,0CE07H ; Program name stored at 8th byte in boot sector.
LD HL,PRTFN
CALL BKSW1to6
LD HL,(0CE16H) ; Get the load address
LD (IX+005H),L ; And store in parameter block at 100D/100E
LD (IX+006H),H ;
INC HL
DEC HL
JR NZ, NOTCPM ; If load address is 0 then where loading CPM.
;LD A,(MEMSW) ; Page out ROM.
NOTCPM: LD HL,(0CE14H) ; Get the size
LD (IX+003H),L ; And store in parameter block at 100B/100C
LD (IX+004H),H ;
LD HL,(0CE1EH) ; Get logical sector number
LD (IX+001H),L ; And store in parameter block at 1009/100A
LD (IX+002H),H ;
CALL DSKREAD ; Read the required data and store in memory.
CALL DSKINIT ; Reset the disk ready for next operation.
LD HL,(0CE18H) ; Get the execution address
JP (HL) ; And execute.
DSKLOADERR:LD DE,MSGLOADERR ; Loading error message
JR L008F ; (+003h)
DSKLOADERR: LD DE,MSGLOADERR ; Loading error message
JR L008F ; (+003h)
L008C: LD DE,MSGDSKNOTMST ; This is not a boot/master disk message.
L008F: LD HL,PRINTMSG
CALL BKSW1to6
LD DE,ERRTONE ; Play error tone.
CALL MELDY
;
LD SP,(TMPSTACKP) ; Recover the correct stack pointer before exit.
RET ; JP SS
L008C: LD DE,MSGDSKNOTMST ; This is not a boot/master disk message.
L008F: LD HL,PRINTMSG
CALL BKSW1to6
LD DE,ERRTONE ; Play error tone.
CALL MELDY
;
LD SP,(TMPSTACKP) ; Recover the correct stack pointer before exit.
RET ; JP SS
L0104: LD A,(MOTON) ; motor on flag
RRCA ; motor off?
CALL NC,DSKMOTORON ; yes, set motor on and wait
LD A,(IX+000H) ;drive no
OR 084H ;
OUT (0DCH),A ; Motor on for drive 0-3
XOR A ;
LD (FDCCMD),A ; clr latest FDC command byte
LD HL,00000H ;
L0119: DEC HL ;
LD A,H ;
OR L ;
JP Z,DSKERR ; Reset and print message that this is not a bootable disk.
IN A,(0D8H) ; Status register.
CPL ;
RLCA ;
JR C,L0119 ; Wait on motor off (bit 7)
LD C,(IX+000H) ; Drive number
LD HL,TRK0FD1 ; 1 track 0 flag for each drive
LD B,000H ;
ADD HL,BC ; Compute related flag 1002/1003/1004/1005
BIT 0,(HL) ;
JR NZ,L0137 ;
CALL DSKSEEKTK0 ; Seek track 0.
SET 0,(HL) ; Set bit 0 of trk 0 flag
L0137: RET
L0104: LD A,(MOTON) ; motor on flag
RRCA ; motor off?
CALL NC,DSKMOTORON ; yes, set motor on and wait
LD A,(IX+000H) ;drive no
OR 084H ;
OUT (0DCH),A ; Motor on for drive 0-3
XOR A ;
LD (FDCCMD),A ; clr latest FDC command byte
LD HL,00000H ;
L0119: DEC HL ;
LD A,H ;
OR L ;
JP Z,DSKERR ; Reset and print message that this is not a bootable disk.
IN A,(0D8H) ; Status register.
CPL ;
RLCA ;
JR C,L0119 ; Wait on motor off (bit 7)
LD C,(IX+000H) ; Drive number
LD HL,TRK0FD1 ; 1 track 0 flag for each drive
LD B,000H ;
ADD HL,BC ; Compute related flag 1002/1003/1004/1005
BIT 0,(HL) ;
JR NZ,L0137 ;
CALL DSKSEEKTK0 ; Seek track 0.
SET 0,(HL) ; Set bit 0 of trk 0 flag
L0137: RET
; Turn disk motor on.
DSKMOTORON:LD A,080H
OUT (0DCH),A ; Motor on
LD B,010H ;
L013E: CALL L02C7 ;
DJNZ L013E ; Wait until becomes ready.
LD A,001H ; Set motor on flag.
LD (MOTON),A ;
RET
; Turn disk motor on.
DSKMOTORON: LD A,080H
OUT (0DCH),A ; Motor on
LD B,010H ;
L013E: CALL L02C7 ;
DJNZ L013E ; Wait until becomes ready.
LD A,001H ; Set motor on flag.
LD (MOTON),A ;
RET
L0149: LD A,01BH
CALL DSKCMD
AND 099H
RET
L0149: LD A,01BH
CALL DSKCMD
AND 099H
RET
; Initialise drive and reset flags, Set motor off
DSKINIT: XOR A
OUT (0DCH),A ; Motor on/off
LD (TRK0FD1),A ; Track 0 flag drive 1
LD (TRK0FD2),A ; Track 0 flag drive 2
LD (TRK0FD3),A ; Track 0 flag drive 3
LD (TRK0FD4),A ; Track 0 flag drive 4
LD (MOTON),A ; Motor on flag
RET
; Initialise drive and reset flags, Set motor off
DSKINIT: XOR A
OUT (0DCH),A ; Motor on/off
LD (TRK0FD1),A ; Track 0 flag drive 1
LD (TRK0FD2),A ; Track 0 flag drive 2
LD (TRK0FD3),A ; Track 0 flag drive 3
LD (TRK0FD4),A ; Track 0 flag drive 4
LD (MOTON),A ; Motor on flag
RET
DSKSEEKTK0:LD A,00BH ; Restore command, seek track 0.
CALL DSKCMD ; Send command to FDC.
AND 085H ; Process result.
XOR 004H
RET Z
JP DSKERR
DSKSEEKTK0: LD A,00BH ; Restore command, seek track 0.
CALL DSKCMD ; Send command to FDC.
AND 085H ; Process result.
XOR 004H
RET Z
JP DSKERR
DSKCMD: LD (FDCCMD),A ; Store latest FDC command.
CPL ; Compliment it (FDC bit value is reversed).
OUT (0D8H),A ; Send command to FDC.
CALL L017E ; Wait to become ready.
IN A,(0D8H) ; Get status register.
CPL ; Inverse (FDC is reverse bit logic).
RET
DSKCMD: LD (FDCCMD),A ; Store latest FDC command.
CPL ; Compliment it (FDC bit value is reversed).
OUT (0D8H),A ; Send command to FDC.
CALL L017E ; Wait to become ready.
IN A,(0D8H) ; Get status register.
CPL ; Inverse (FDC is reverse bit logic).
RET
L017E: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L0185: LD HL,00000H
L0188: DEC HL
LD A,H
OR L
JR Z,L0196 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR C,L0188 ; (-00bh)
POP HL
POP DE
RET
L017E: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L0185: LD HL,00000H
L0188: DEC HL
LD A,H
OR L
JR Z,L0196 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR C,L0188 ; (-00bh)
POP HL
POP DE
RET
L0196: DEC E
JR NZ,L0185 ; (-014h)
JP DSKERR
L0196: DEC E
JR NZ,L0185 ; (-014h)
JP DSKERR
L019C: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L01A3: LD HL,00000H
L01A6: DEC HL
LD A,H
OR L
JR Z,L01B4 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR NC,L01A6 ; (-00bh)
POP HL
POP DE
RET
L019C: PUSH DE
PUSH HL
CALL L02C0
LD E,007H
L01A3: LD HL,00000H
L01A6: DEC HL
LD A,H
OR L
JR Z,L01B4 ; (+009h)
IN A,(0D8H)
CPL
RRCA
JR NC,L01A6 ; (-00bh)
POP HL
POP DE
RET
L01B4: DEC E
JR NZ,L01A3 ; (-014h)
JP DSKERR
L01B4: DEC E
JR NZ,L01A3 ; (-014h)
JP DSKERR
; Read disk starting at the first logical sector in param block 1009/100A
; Continue reading for the given size 100B/100C and store in the location
; Pointed to by the address stored in the parameter block. 100D/100E
DSKREAD: CALL L0220 ; Compute logical sector-no to track-no & sector-no, retries=10
L01BD: CALL L0229 ; Set current track & sector, get load address to HL
L01C0: CALL L0249 ; Set side reg
CALL L0149 ; Command 1b output (seek)
JR NZ,L0216 ;
CALL L0259 ; Set track & sector reg
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As below. L03FE
LD IY,L01DF ; Read sector into memory.
;DI
LD A,094H ; Latest FDC command byte
CALL L028A
L01DB: LD B,000H
JP (IX)
; Read disk starting at the first logical sector in param block 1009/100A
; Continue reading for the given size 100B/100C and store in the location
; Pointed to by the address stored in the parameter block. 100D/100E
DSKREAD: CALL L0220 ; Compute logical sector-no to track-no & sector-no, retries=10
L01BD: CALL L0229 ; Set current track & sector, get load address to HL
L01C0: CALL L0249 ; Set side reg
CALL L0149 ; Command 1b output (seek)
JR NZ,L0216 ;
CALL L0259 ; Set track & sector reg
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As below. L03FE
LD IY,L01DF ; Read sector into memory.
;DI
LD A,094H ; Latest FDC command byte
CALL L028A
L01DB: LD B,000H
JP (IX)
; Get data from disk sector to staging area (CE00).
L01DF: INI
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
JP NZ, 0F3FEH ; This is crucial, as the Z80 is running at 2MHz it is not fast enough so needs
; Get data from disk sector to staging area (CE00).
L01DF: INI
LD A,(DE) ; If not at the end of the line, then process as the boot disk number.
JP NZ, 0F3FEH ; This is crucial, as the Z80 is running at 2MHz it is not fast enough so needs
; hardware acceleration in the form of a banked ROM, if disk not ready jumps to IX, if
; data ready, jumps to IY. L03FE
POP IX
INC (IX+008H) ; Increment current sector number
LD A,(IX+008H) ; Load current sector number
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As above. L03FE
CP 011H ; Sector 17? Need to loop to next track.
JR Z,L01FB
DEC D
JR NZ,L01DB
JR L01FC ; (+001h)
POP IX
INC (IX+008H) ; Increment current sector number
LD A,(IX+008H) ; Load current sector number
PUSH IX ; Save 1008H
LD IX, 0F3FEH ; As above. L03FE
CP 011H ; Sector 17? Need to loop to next track.
JR Z,L01FB
DEC D
JR NZ,L01DB
JR L01FC ; (+001h)
L01FB: DEC D
L01FC: CALL L0294
CALL L02D2
POP IX
IN A,(0D8H)
CPL
AND 0FFH
JR NZ,L0216 ; (+00bh)
CALL L0278
JP Z,L021B
LD A,(IX+007H)
JR L01C0 ; (-056h)
L01FB: DEC D
L01FC: CALL L0294
CALL L02D2
POP IX
IN A,(0D8H)
CPL
AND 0FFH
JR NZ,L0216 ; (+00bh)
CALL L0278
JP Z,L021B
LD A,(IX+007H)
JR L01C0 ; (-056h)
L0216: CALL L026A
JR L01BD ; (-05eh)
L0216: CALL L026A
JR L01BD ; (-05eh)
L021B: LD A,080H
OUT (0DCH),A ; Motor on
RET
L021B: LD A,080H
OUT (0DCH),A ; Motor on
RET
L0220: CALL L02A3 ; compute logical sector no to track no & sector no
LD A,00AH ; 10 retries
LD (RETRIES),A
RET
L0220: CALL L02A3 ; compute logical sector no to track no & sector no
LD A,00AH ; 10 retries
LD (RETRIES),A
RET
; Set current track & sector, get load address to HL
L0229: CALL L0104
LD D,(IX+004H) ; Number of sectors to read
LD A,(IX+003H) ; Bytes to read
OR A ; 0?
JR Z,L0236 ; Yes
INC D ; Number of sectors to read + 1
L0236: LD A,(IX+00AH) ; Start sector number
LD (IX+008H),A ; To current sector number
LD A,(IX+009H) ; Start track number
LD (IX+007H),A ; To current track number
LD L,(IX+005H) ; Load address low byte
LD H,(IX+006H) ; Load address high byte
RET
; Set current track & sector, get load address to HL
L0229: CALL L0104
LD D,(IX+004H) ; Number of sectors to read
LD A,(IX+003H) ; Bytes to read
OR A ; 0?
JR Z,L0236 ; Yes
INC D ; Number of sectors to read + 1
L0236: LD A,(IX+00AH) ; Start sector number
LD (IX+008H),A ; To current sector number
LD A,(IX+009H) ; Start track number
LD (IX+007H),A ; To current track number
LD L,(IX+005H) ; Load address low byte
LD H,(IX+006H) ; Load address high byte
RET
; Compute side/head.
L0249: SRL A ; Track number even?
CPL ;
OUT (0DBH),A ; Output track no.
JR NC,L0254 ; Yes, even, set side/head 1
LD A,001H ; No, odd, set side/head 0
JR L0255
; Compute side/head.
L0249: SRL A ; Track number even?
CPL ;
OUT (0DBH),A ; Output track no.
JR NC,L0254 ; Yes, even, set side/head 1
LD A,001H ; No, odd, set side/head 0
JR L0255
; Set side/head register.
L0254: XOR A ; Side 0
L0255: CPL ; Side 1
OUT (0DDH),A ; Side/head register.
RET
; Set side/head register.
L0254: XOR A ; Side 0
L0255: CPL ; Side 1
OUT (0DDH),A ; Side/head register.
RET
; Set track and sector register.
L0259: LD C,0DBH
LD A,(IX+007H) ; Current track number
SRL A
CPL
OUT (0D9H),A ; Track reg
LD A,(IX+008H) ; Current sector number
CPL
OUT (0DAH),A ; Sector reg
RET
; Set track and sector register.
L0259: LD C,0DBH
LD A,(IX+007H) ; Current track number
SRL A
CPL
OUT (0D9H),A ; Track reg
LD A,(IX+008H) ; Current sector number
CPL
OUT (0DAH),A ; Sector reg
RET
L026A: LD A,(RETRIES)
DEC A
LD (RETRIES),A
JP Z,DSKERR
CALL DSKSEEKTK0
RET
L026A: LD A,(RETRIES)
DEC A
LD (RETRIES),A
JP Z,DSKERR
CALL DSKSEEKTK0
RET
L0278: LD A,(IX+008H)
CP 011H
JR NZ,L0287 ; (+008h)
LD A,001H
LD (IX+008H),A
INC (IX+007H)
L0287: LD A,D
OR A
RET
L0278: LD A,(IX+008H)
CP 011H
JR NZ,L0287 ; (+008h)
LD A,001H
LD (IX+008H),A
INC (IX+007H)
L0287: LD A,D
OR A
RET
L028A: LD (FDCCMD),A
CPL
OUT (0D8H),A
CALL L019C
RET
L028A: LD (FDCCMD),A
CPL
OUT (0D8H),A
CALL L019C
RET
L0294: LD A,0D8H
CPL
OUT (0D8H),A
CALL L017E
RET
L0294: LD A,0D8H
CPL
OUT (0D8H),A
CALL L017E
RET
DSKERR: CALL DSKINIT
JP DSKLOADERR
DSKERR: CALL DSKINIT
JP DSKLOADERR
; Logical sector number to physical track and sector.
L02A3: LD B,000H
LD DE,00010H ; No of sectors per trk (16)
LD L,(IX+001H) ; Logical sector number
LD H,(IX+002H) ; 2 bytes in length
XOR A
L02AF: SBC HL,DE ; Subtract 16 sectors/trk
JR C,L02B6 ; Yes, negative value
INC B ; Count track
JR L02AF ; Loop
L02B6: ADD HL,DE ; Reset HL to the previous
LD H,B ; Track
INC L ; Correction +1
LD (IX+009H),H ; Start track no
LD (IX+00AH),L ; Start sector no
RET
; Logical sector number to physical track and sector.
L02A3: LD B,000H
LD DE,00010H ; No of sectors per trk (16)
LD L,(IX+001H) ; Logical sector number
LD H,(IX+002H) ; 2 bytes in length
XOR A
L02AF: SBC HL,DE ; Subtract 16 sectors/trk
JR C,L02B6 ; Yes, negative value
INC B ; Count track
JR L02AF ; Loop
L02B6: ADD HL,DE ; Reset HL to the previous
LD H,B ; Track
INC L ; Correction +1
LD (IX+009H),H ; Start track no
LD (IX+00AH),L ; Start sector no
RET
L02C0: PUSH DE
LD DE,00007H
JP L02CB
L02C0: PUSH DE
LD DE,00007H
JP L02CB
L02C7: PUSH DE
LD DE,01013H
L02CB: DEC DE
LD A,E
OR D
JR NZ,L02CB ; (-005h)
POP DE
RET
L02C7: PUSH DE
LD DE,01013H
L02CB: DEC DE
LD A,E
OR D
JR NZ,L02CB ; (-005h)
POP DE
RET
L02D2: PUSH AF
LD A,(0119CH)
CP 0F0H
JR NZ,L02DB ; (+001h)
;EI
L02DB: POP AF
RET
L02D2: PUSH AF
LD A,(0119CH)
CP 0F0H
JR NZ,L02DB ; (+001h)
;EI
L02DB: POP AF
RET
;wait on bit 0 and bit 1 = 0 of state reg
L0300: IN A,(0D8H) ; State reg
RRCA
JR C,L0300 ; Wait on not busy
RRCA
JR C,L0300 ; Wait on data reg ready
JP (IY) ; to f1df
;wait on bit 0 and bit 1 = 0 of state reg
L0300: IN A,(0D8H) ; State reg
RRCA
JR C,L0300 ; Wait on not busy
RRCA
JR C,L0300 ; Wait on data reg ready
JP (IY) ; to f1df
ENDIF
;-------------------------------------------------------------------------------
; END OF FLOPPY DISK CONTROLLER FUNCTIONALITY
@@ -532,6 +531,13 @@ PRMBLK: DB 000H, 000H, 000H, 000H, 001H, 000H, 0CEH, 000H, 000H, 000H,
L03FE: JP (IY)
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
; RomDisk, top 8 bytes are used by the control registers when enabled so dont use the space.
IF BUILD_ROMDISK = 1
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ENDIF
IF BUILD_SFD700 = 1
ALIGN 0F000H
ENDIF

73
asm/rfs_bank2.asm
View File

@@ -11,16 +11,19 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; July 2020 - Bug fixes and additions.
; July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
; or without the K64 I/O processor. RFS wont use the K64 processor all
; operations are done by the Z80 under RFS.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- July 2020 - Bug fixes and additions.
;- July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
;- or without the K64 I/O processor. RFS wont use the K64 processor all
;- operations are done by the Z80 under RFS.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -37,6 +40,13 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK2"
ALIGN UROMADDR
ENDIF
;===========================================================
;
; USER ROM BANK 2 - SD Card Controller functions.
@@ -48,25 +58,11 @@
; Common code spanning all banks.
;--------------------------------
NOP
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
ROMFS2_0: LD A,(BNKCTRLRST)
DJNZ ROMFS2_0 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
NOP
NOP
NOP
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
NOP
NOP
NOP
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
HWSELROM2 ; Select the first ROM page.
;
; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H.
JP 00000H ; This is for safety!!
;------------------------------------------------------------------------------------------
; Bank switching code, allows a call to code in another bank.
; This code is duplicated in each bank such that a bank switch doesnt affect logic flow.
@@ -117,10 +113,10 @@ BKSW2_0: PUSH HL ; P
LD HL, BKSWRET2 ; Place bank switchers return address on stack.
EX (SP),HL
LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it.
LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value.
BNKSWSEL
JP (HL) ; Jump to required function.
BKSWRET2: POP AF ; Get bank which called us.
LD (BNKSELUSER), A ; Return to that bank.
BNKSWSELRET
POP AF
RET
@@ -197,7 +193,7 @@ TDELAYB0: RRA
JR NC, TDELAYB1
OR 0
TDELAYB1: RRA
RET NC
;RET NC
RET
@@ -1360,7 +1356,7 @@ LOADSD9A: LD (DTADR),DE
LD (EXADR),DE
JR LOADSDX ; Exit with ok.
;
LOADSD10 CALL LOADSD9 ; Modularised file find as the CMT replacement functions need it.
LOADSD10: CALL LOADSD9 ; Modularised file find as the CMT replacement functions need it.
LD DE,MSGLOAD+1 ; Skip initial CR.
LD BC,NAME
CALL SDPRINT ; Print out the filename.
@@ -1592,14 +1588,13 @@ SAVESD9: LD DE,MSGSVFAIL ; Fail,
; END OF SD CONTROLLER FUNCTIONALITY
;-------------------------------------------------------------------------------
;--------------------------------------
;
; Message table - Refer to Bank 6 for
; all printable messages.
;
;--------------------------------------
; RomDisk, top 8 bytes are used by the control registers when enabled so dont use the space.
IF BUILD_ROMDISK = 1
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ENDIF
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
IF BUILD_SFD700 = 1
ALIGN 0F000H
ENDIF

54
asm/rfs_bank3.asm
View File

@@ -11,12 +11,15 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -38,6 +41,13 @@ COLW EQU 40
SCRNSZ EQU COLW * ROW
MODE80C EQU 0
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK3"
ALIGN UROMADDR
ENDIF
;===========================================================
;
; USER ROM BANK 3 - Monitor memory utilities.
@@ -49,20 +59,7 @@ MODE80C EQU 0
; Common code spanning all banks.
;--------------------------------
NOP
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
ROMFS3_0: LD A,(BNKCTRLRST)
DJNZ ROMFS3_0 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
NOP
NOP
NOP
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
NOP
NOP
NOP
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
HWSELROM2 ; Select the first ROM page.
;
; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H.
JP 00000H ; This is for safety!!
@@ -118,10 +115,10 @@ BKSW3_0: PUSH HL ; P
LD HL, BKSWRET3 ; Place bank switchers return address on stack.
EX (SP),HL
LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it.
LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value.
BNKSWSEL
JP (HL) ; Jump to required function.
BKSWRET3: POP AF ; Get bank which called us.
LD (BNKSELUSER), A ; Return to that bank.
BNKSWSELRET
POP AF
RET
@@ -543,6 +540,13 @@ SLPT: DB 01H ; TEXT
;
;--------------------------------------
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
; RomDisk, top 8 bytes are used by the control registers when enabled so dont use the space.
IF BUILD_ROMDISK = 1
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ENDIF
IF BUILD_SFD700 = 1
ALIGN 0F000H
ENDIF

449
asm/rfs_bank4.asm
View File

@@ -11,12 +11,15 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -33,6 +36,12 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK4"
ALIGN UROMADDR
ENDIF
;===========================================================
;
@@ -45,20 +54,7 @@
; Common code spanning all banks.
;--------------------------------
NOP
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
ROMFS4_0: LD A,(BNKCTRLRST)
DJNZ ROMFS4_0 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
NOP
NOP
NOP
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
NOP
NOP
NOP
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
HWSELROM2 ; Select the first ROM page.
;
; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H.
JP 00000H ; This is for safety!!
@@ -114,10 +110,10 @@ BKSW4_0: PUSH HL ; P
LD HL, BKSWRET4 ; Place bank switchers return address on stack.
EX (SP),HL
LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it.
LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value.
BNKSWSEL
JP (HL) ; Jump to required function.
BKSWRET4: POP AF ; Get bank which called us.
LD (BNKSELUSER), A ; Return to that bank.
BNKSWSELRET
POP AF
RET
@@ -219,8 +215,18 @@ CMTWRI: ;DI
LD HL,IBUFE
LD BC,00080H
CALL CKSUM
CALL MOTOR
JR C,CMTWRI2
IF BUILD_ROMDISK = 1
CALL MOTOR80A
ENDIF
IF BUILD_SFD700 = 1
IN A,(SFD700_MODE)
OR A
JR Z,CMTWRI80A
CALL MOTOR700
JR CMTWRI0
CMTWRI80A: CALL MOTOR80A
ENDIF
CMTWRI0: JR C,CMTWRI2
LD A,E
CP 0CCH
JR NZ,CMTWRI1
@@ -235,7 +241,17 @@ CMTWRI: ;DI
POP DE
POP HL
CMTWRI1: CALL GAP
CALL WTAPE
IF BUILD_ROMDISK = 1
CALL WTAPE80A
ENDIF
IF BUILD_SFD700 = 1
IN A,(SFD700_MODE)
OR A
JR Z,CMTWRI80A2
CALL WTAPE700
JR CMTWRI2
CMTWRI80A2: CALL WTAPE80A
ENDIF
CMTWRI2: POP HL
POP BC
POP DE
@@ -323,6 +339,376 @@ SGX: LD A,(SWRK)
; END OF CMT CONTROLLER FUNCTIONALITY
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; START OF MEMORY TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
MEMTEST: LD B,240 ; Number of loops
LOOP: LD HL,MEMSTART ; Start of checked memory,
LD D,0CFh ; End memory check CF00
LOOP1: LD A,000h
CP L
JR NZ,LOOP1b
CALL PRTHL ; Print HL as 4digit hex.
LD A,0C4h ; Move cursor left.
LD E,004h ; 4 times.
LOOP1a: CALL DPCT
DEC E
JR NZ,LOOP1a
LOOP1b: INC HL
LD A,H
CP D ; Have we reached end of memory.
JR Z,LOOP3 ; Yes, exit.
LD A,(HL) ; Read memory location under test, ie. 0.
CPL ; Subtract, ie. FF - A, ie FF - 0 = FF.
LD (HL),A ; Write it back, ie. FF.
SUB (HL) ; Subtract written memory value from A, ie. should be 0.
JR NZ,LOOP2 ; Not zero, we have an error.
LD A,(HL) ; Reread memory location, ie. FF
CPL ; Subtract FF - FF
LD (HL),A ; Write 0
SUB (HL) ; Subtract 0
JR Z,LOOP1 ; Loop if the same, ie. 0
LOOP2: LD A,16h
CALL PRNT ; Print A
CALL PRTHX ; Print HL as 4 digit hex.
CALL PRNTS ; Print space.
XOR A
LD (HL),A
LD A,(HL) ; Get into A the failing bits.
CALL PRTHX ; Print A as 2 digit hex.
CALL PRNTS ; Print space.
LD A,0FFh ; Repeat but first load FF into memory
LD (HL),A
LD A,(HL)
CALL PRTHX ; Print A as 2 digit hex.
NOP
JR LOOP4
LOOP3: CALL PRTHL
LD DE,OKCHECK
CALL MSG ; Print check message in DE
LD A,B ; Print loop count.
CALL PRTHX
LD DE,OKMSG
CALL MSG ; Print ok message in DE
CALL NL
DEC B
JR NZ,LOOP
LD DE,DONEMSG
CALL MSG ; Print check message in DE
JP ST1X
LOOP4: LD B,09h
CALL PRNTS ; Print space.
XOR A ; Zero A
SCF ; Set Carry
LOOP5: PUSH AF ; Store A and Flags
LD (HL),A ; Store 0 to bad location.
LD A,(HL) ; Read back
CALL PRTHX ; Print A as 2 digit hex.
CALL PRNTS ; Print space
POP AF ; Get back A (ie. 0 + C)
RLA ; Rotate left A. Bit LSB becomes Carry (ie. 1 first instance), Carry becomes MSB
DJNZ LOOP5 ; Loop if not zero, ie. print out all bit locations written and read to memory to locate bad bit.
XOR A ; Zero A, clears flags.
LD A,80h
LD B,08h
LOOP6: PUSH AF ; Repeat above but AND memory location with original A (ie. 80)
LD C,A ; Basically walk through all the bits to find which one is stuck.
LD (HL),A
LD A,(HL)
AND C
NOP
JR Z,LOOP8 ; If zero then print out the bit number
NOP
NOP
LD A,C
CPL
LD (HL),A
LD A,(HL)
AND C
JR NZ,LOOP8 ; As above, if the compliment doesnt yield zero, print out the bit number.
LOOP7: POP AF
RRCA
NOP
DJNZ LOOP6
JP ST1X
LOOP8: CALL LETNL ; New line.
LD DE,BITMSG ; BIT message
CALL MSG ; Print message in DE
LD A,B
DEC A
CALL PRTHX ; Print A as 2 digit hex, ie. BIT number.
CALL LETNL ; New line
LD DE,BANKMSG ; BANK message
CALL MSG ; Print message in DE
LD A,H
CP 50h ; 'P'
JR NC,LOOP9 ; Work out bank number, 1, 2 or 3.
LD A,01h
JR LOOP11
LOOP9: CP 90h
JR NC,LOOP10
LD A,02h
JR LOOP11
LOOP10: LD A,03h
LOOP11: CALL PRTHX ; Print A as 2 digit hex, ie. BANK number.
JR LOOP7
DLY1S: PUSH AF
PUSH BC
LD C,10
L0324: CALL DLY12
DEC C
JR NZ,L0324
POP BC
POP AF
RET
;-------------------------------------------------------------------------------
; END OF MEMORY TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; START OF TIMER TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
; Test the 8253 Timer, configure it as per the monitor and display the read back values.
TIMERTST: CALL NL
LD DE,MSG_TIMERTST
CALL MSG
CALL NL
LD DE,MSG_TIMERVAL
CALL MSG
LD A,01h
LD DE,8000h
CALL TIMERTST1
NDE: JP NDE
JP ST1X
TIMERTST1: ;DI
PUSH BC
PUSH DE
PUSH HL
LD (AMPM),A
LD A,0F0H
LD (TIMFG),A
ABCD: LD HL,0A8C0H
XOR A
SBC HL,DE
PUSH HL
INC HL
EX DE,HL
LD HL,CONTF ; Control Register
LD (HL),0B0H ; 10110000 Control Counter 2 10, Write 2 bytes 11, 000 Interrupt on Terminal Count, 0 16 bit binary
LD (HL),074H ; 01110100 Control Counter 1 01, Write 2 bytes 11, 010 Rate Generator, 0 16 bit binary
LD (HL),030H ; 00110100 Control Counter 1 01, Write 2 bytes 11, 010 interrupt on Terminal Count, 0 16 bit binary
LD HL,CONT2 ; Counter 2
LD (HL),E
LD (HL),D
LD HL,CONT1 ; Counter 1
LD (HL),00AH
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD (HL),00CH
LD (HL),0C0H
; LD HL,CONT2 ; Counter 2
; LD C,(HL)
; LD A,(HL)
; CP D
; JP NZ,L0323H
; LD A,C
; CP E
; JP Z,CDEF
;
L0323H: PUSH AF
PUSH BC
PUSH DE
PUSH HL
;
LD HL,CONTF ; Control Register
LD (HL),080H
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
;CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),040H
LD HL,CONT1 ; Counter 1
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
;CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
;CALL DLY1S
;
LD A,0C4h ; Move cursor left.
LD E,0Eh ; 4 times.
L0330: CALL DPCT
DEC E
JR NZ,L0330
;
; LD C,20
;L0324: CALL DLY12
; DEC C
; JR NZ,L0324
;
POP HL
POP DE
POP BC
POP AF
;
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CP D
JP NZ,L0323H
LD A,C
CP E
JP NZ,L0323H
;
;
PUSH AF
PUSH BC
PUSH DE
PUSH HL
CALL NL
CALL NL
CALL NL
LD DE,MSG_TIMERVAL2
CALL MSG
POP HL
POP DE
POP BC
POP AF
;
CDEF: POP DE
LD HL,CONT1
LD (HL),00CH
LD (HL),07BH
INC HL
L0336H: PUSH AF
PUSH BC
PUSH DE
PUSH HL
;
LD HL,CONTF ; Control Register
LD (HL),080H
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),040H
LD HL,CONT1 ; Counter 1
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL PRNTS
CALL DLY1S
;
LD HL,CONTF ; Control Register
LD (HL),000H
LD HL,CONT0 ; Counter 0
LD C,(HL)
LD A,(HL)
CALL PRTHX
LD A,C
CALL PRTHX
;
CALL DLY1S
;
LD A,0C4h ; Move cursor left.
LD E,0Eh ; 4 times.
L0340: CALL DPCT
DEC E
JR NZ,L0340
;
POP HL
POP DE
POP BC
POP AF
LD HL,CONT2 ; Counter 2
LD C,(HL)
LD A,(HL)
CP D
JR NZ,L0336H
LD A,C
CP E
JR NZ,L0336H
CALL NL
LD DE,MSG_TIMERVAL3
CALL MSG
POP HL
POP DE
POP BC
;EI
RET
;-------------------------------------------------------------------------------
; END OF TIMER TEST FUNCTIONALITY
;-------------------------------------------------------------------------------
;--------------------------------------
;
; Message table
;
;--------------------------------------
OKCHECK: DB ", CHECK: ", 0Dh
OKMSG: DB " OK.", 0Dh
DONEMSG: DB 11h
DB "RAM TEST COMPLETE.", 0Dh
BITMSG: DB " BIT: ", 0Dh
BANKMSG: DB " BANK: ", 0Dh
MSG_TIMERTST:
DB "8253 TIMER TEST", 0Dh, 00h
MSG_TIMERVAL:
DB "READ VALUE 1: ", 0Dh, 00h
MSG_TIMERVAL2:
DB "READ VALUE 2: ", 0Dh, 00h
MSG_TIMERVAL3:
DB "READ DONE.", 0Dh, 00h
;--------------------------------------
;
; Message table - Refer to bank 6 for
@@ -330,6 +716,13 @@ SGX: LD A,(SWRK)
;
;--------------------------------------
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
; RomDisk, top 8 bytes are used by the control registers when enabled so dont use the space.
IF BUILD_ROMDISK = 1
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ENDIF
IF BUILD_SFD700 = 1
ALIGN 0F000H
ENDIF

55
asm/rfs_bank5.asm
View File

@@ -11,13 +11,16 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; Mar 2021 - Add mapping utilities for Sharp<->ASCII conversion.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Mar 2021 - Add mapping utilities for Sharp<->ASCII conversion.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -34,6 +37,12 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK5"
ALIGN UROMADDR
ENDIF
;======================================
;
@@ -46,20 +55,7 @@
; Common code spanning all banks.
;--------------------------------
NOP
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
ROMFS5_0: LD A,(BNKCTRLRST)
DJNZ ROMFS5_0 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
NOP
NOP
NOP
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
NOP
NOP
NOP
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
HWSELROM2 ; Select the first ROM page.
;
; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H.
JP 00000H ; This is for safety!!
@@ -115,10 +111,10 @@ BKSW5_0: PUSH HL ; P
LD HL, BKSWRET5 ; Place bank switchers return address on stack.
EX (SP),HL
LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it.
LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value.
BNKSWSEL
JP (HL) ; Jump to required function.
BKSWRET5: POP AF ; Get bank which called us.
LD (BNKSELUSER), A ; Return to that bank.
BNKSWSELRET
POP AF
RET
@@ -205,6 +201,13 @@ SHARPTOASC: DB 000H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H
DB 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H ; 0xEF
DB 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H, 020H ; 0xFF
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
; RomDisk, top 8 bytes are used by the control registers when enabled so dont use the space.
IF BUILD_ROMDISK = 1
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ENDIF
IF BUILD_SFD700 = 1
ALIGN 0F000H
ENDIF

158
asm/rfs_bank6.asm
View File

@@ -11,15 +11,18 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: July 2019 - Merged 2 utilities to create this compilation.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
; July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
; or without the K64 I/O processor. RFS wont use the K64 processor all
; operations are done by the Z80 under RFS.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- July 2020 - Updated for the v2.1 hardware. RFS can run with a tranZPUter board with
;- or without the K64 I/O processor. RFS wont use the K64 processor all
;- operations are done by the Z80 under RFS.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify
@@ -36,6 +39,12 @@
;- along with this program. If not, see <http://www.gnu.org/licenses/>.
;--------------------------------------------------------------------------------------------------------
IF BUILD_SFD700 = 1
ORG 0E000H
ALIGN 0E300H
DB "BANK6"
ALIGN UROMADDR
ENDIF
;======================================
;
@@ -48,20 +57,7 @@
; Common code spanning all banks.
;--------------------------------
NOP
LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default.
ROMFS6_0: LD A,(BNKCTRLRST)
DJNZ ROMFS6_0 ; Apply the default number of coded latch reads to enable the bank control registers.
LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK.
LD (BNKCTRL),A
NOP
NOP
NOP
XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0
LD (BNKSELMROM),A
NOP
NOP
NOP
LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it.
HWSELROM2 ; Select the first ROM page.
;
; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H.
JP 00000H ; This is for safety!!
@@ -117,10 +113,10 @@ BKSW6_0: PUSH HL ; P
LD HL, BKSWRET6 ; Place bank switchers return address on stack.
EX (SP),HL
LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it.
LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value.
BNKSWSEL
JP (HL) ; Jump to required function.
BKSWRET6: POP AF ; Get bank which called us.
LD (BNKSELUSER), A ; Return to that bank.
BNKSWSELRET
POP AF
RET
@@ -280,39 +276,68 @@ PRTSTRE: POP DE
; Help text. Use of lower case, due to Sharp's non standard character set, is not easy, you have to manually code each byte
; hence using upper case.
; 1 40
HELPSCR: DB "0..9 - select RFS Drive.", 00DH
DB "40 - 40 col mode.", 00DH
DB "80 - 80 col mode.", 00DH
;DB "700 - Select MZ-700 Mode.", 00DH
;DB "7008 - Select MZ-700 80 col Mode.", 00DH
DB "B - toggle keyboard bell.", 00DH
DB "BASIC - Load BASIC SA-5510.", 00DH
DB "C - clear memory $1200-$D000.", 00DH
DB "CPXXXXYYYYZZZZ - copy memory", 00DH
DB " XXXX=src,YYYY=dst,ZZZZ=size", 00DH
DB "CPM - Load CPM.", 00DH
DB "DXXXX[YYYY] - dump mem XXXX to YYYY.", 00DH
DB "EC[FN]- erase file, FN=No, or Filename", 00DH
DB "F[X] - boot fd drive X.", 00DH
DB "f - boot fd original rom.", 00DH
DB "H - this help screen.", 00DH
DB "IR/IC - rfs dir listing rom/sd card.", 00DH
DB "JXXXX - jump to location XXXX.", 00DH
DB "LT[FN]- load tape, FN=Filename", 00DH
DB "LR[FN]- load rom, FN=No. or Filename", 00DH
DB "LC[FN]- load sdcard, FN=No. or Filename", 00DH
DB " - add NX for no exec, ie.LRNX.", 00DH
DB "MXXXX - edit memory starting at XXXX.", 00DH
DB "P - test printer.", 00DH
DB "R - test dram memory.", 00DH
DB "SD2T - copy sd card to tape.", 00DH
DB "ST[XXXXYYYYZZZZ] - save mem to tape.", 00DH
DB "SC[XXXXYYYYZZZZ] - save mem to card.", 00DH
DB " XXXX=start,YYYY=end,ZZZZ=exec", 00DH
DB "T - test timer.", 00DH
DB "T2SD - copy tape to sd card.", 00DH
DB "V - verify tape save.", 00DH
DB 000H
HELPSCR: IF BUILD_ROMDISK = 1
DB "0..9 - select RFS Drive.", 00DH
DB "40 - 40 col mode.", 00DH
DB "80 - 80 col mode.", 00DH
;DB "700 - Select MZ-700 Mode.", 00DH
;DB "7008 - Select MZ-700 80 col Mode.", 00DH
DB "B - toggle keyboard bell.", 00DH
DB "BASIC - Load BASIC SA-5510.", 00DH
DB "C - clear memory $1200-$D000.", 00DH
DB "CPXXXXYYYYZZZZ - copy memory", 00DH
DB " XXXX=src,YYYY=dst,ZZZZ=size", 00DH
DB "CPM - Load CPM.", 00DH
DB "DXXXX[YYYY] - dump mem XXXX to YYYY.", 00DH
DB "EC[FN]- erase file, FN=No, or Filename", 00DH
DB "F[X] - boot fd drive X.", 00DH
DB "f - boot fd original rom.", 00DH
DB "H - this help screen.", 00DH
DB "IR/IC - rfs dir listing rom/sd card.", 00DH
DB "JXXXX - jump to location XXXX.", 00DH
DB "LT[FN]- load tape, FN=Filename", 00DH
DB "LR[FN]- load rom, FN=No. or Filename", 00DH
DB "LC[FN]- load sdcard, FN=No. or Filename", 00DH
DB " - add NX for no exec, ie.LRNX.", 00DH
DB "MXXXX - edit memory starting at XXXX.", 00DH
DB "P - test printer.", 00DH
DB "R - test dram memory.", 00DH
DB "SD2T - copy sd card to tape.", 00DH
DB "ST[XXXXYYYYZZZZ] - save mem to tape.", 00DH
DB "SC[XXXXYYYYZZZZ] - save mem to card.", 00DH
DB " XXXX=start,YYYY=end,ZZZZ=exec", 00DH
DB "T - test timer.", 00DH
DB "T2SD - copy tape to sd card.", 00DH
DB "V - verify tape save.", 00DH
DB 000H
ENDIF
IF BUILD_SFD700 = 1
DB "ASMXXXX assemble into dest XXXX", 00DH
DB "B - toggle keyboard bell.", 00DH
DB "BASIC - Load BASIC SA-5510.", 00DH
DB "C - clear memory $1200-$D000.", 00DH
DB "CPXXXXYYYYZZZZ - copy memory", 00DH
DB " XXXX=src,YYYY=dst,ZZZZ=size", 00DH
;DB "CPM - Load CPM.", 00DH
DB "DXXXX[YYYY] - dump mem XXXX to YYYY.", 00DH
DB "DASMXXXX[YYYY]", 00DH
DB " disassemble XXXX to YYYY", 00DH
DB "F - boot fd.", 00DH
DB "H - this help screen.", 00DH
DB "IR - rfs rom dir listing.", 00DH
DB "JXXXX - jump to location XXXX.", 00DH
DB "LT[FN]- load tape, FN=Filename", 00DH
DB "LR[FN]- load rom, FN=No. or Filename", 00DH
DB " - add NX for no exec, ie.LRNX.", 00DH
DB "MXXXX - edit memory starting at XXXX.", 00DH
DB "P - test printer.", 00DH
DB "R - test dram memory.", 00DH
DB "ST[XXXXYYYYZZZZ] - save mem to tape.", 00DH
DB " XXXX=start,YYYY=end,ZZZZ=exec", 00DH
DB "T - test timer.", 00DH
DB "V - verify tape save.", 00DH
DB 000H
ENDIF
;-------------------------------------------------------------------------------
; END OF HELP SCREEN FUNCTIONALITY
@@ -455,7 +480,7 @@ ATBL: DB 0CCH ; NUL '\0' (null character)
;
;--------------------------------------
MSGSONTZ: DB "+ TZ" ; Version 2.x with version 2.1+ of tranZPUter board installed.
MSGSON: DB "+ RFS ", 0ABh, "2.1b **", 00DH, 000H ; Version 2.x-> as we are now using the v2.x PCB with 4 devices on-board
MSGSON: DB "+ RFS ", 0ABh, "2.31a **", 00DH, 000H ; Version 2.x-> as we are now using the v2.x PCB with 4 devices on-board
MSGNOTFND: DB "Not Found", 00DH, 000H
MSGRDIRLST: DB "ROM Directory:", 00DH, 000H
MSGTRM: DB 00DH, 000H
@@ -491,7 +516,16 @@ MSGNOTZINST:DB "No tranZPUter >=v2 card installed.", 00DH, 000H
MSGNOCMTDIR:DB "CMT has no directory.", 00DH, 000H
MSGINVDRV: DB "Invalid drive, SD=0..9 or C=CMT", 00DH, 000H
MSGNOVERIFY:DB "No Verify for SD!", 00DH, 000H
MSGNOINSTR: DB "Bad instruction.", 00DH, 000H
MSGNOPARAM: DB "Bad parameter.", 00DH, 000H
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
; RomDisk - Pad to EFFF boundary.
IF BUILD_ROMDISK = 1
ALIGN 0EFF8h
ORG 0EFF8h
DB 0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh
ENDIF
; SFD700 - Pad to 10000H
IF BUILD_SFD700 = 1
ALIGN 10000H
ENDIF

2039
asm/rfs_bank7.asm
View File

File diff suppressed because it is too large Load Diff

15
asm/rfs_mrom.asm
View File

@@ -13,12 +13,15 @@
;- Copyright: (c) 2018-2023 Philip Smart <philip.smart@net2net.org>
;-
;- History: Sep 2019 - Initial version.
; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
; latch adds additional instruction overhead as the control latches share
; the same address space as the Flash RAMS thus the extra hardware to
; only enable the control registers if a fixed number of reads is made
; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
; that no loop instruction is ever placed into EFF8H - EFFFH.
;- May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded
;- latch adds additional instruction overhead as the control latches share
;- the same address space as the Flash RAMS thus the extra hardware to
;- only enable the control registers if a fixed number of reads is made
;- into the upper 8 bytes which normally wouldnt occur. Caveat - ensure
;- that no loop instruction is ever placed into EFF8H - EFFFH.
;- Aug 2023 - Updates to make RFS run under the SFD700 Floppy Disk Interface board.
;- UROM remains the same, a 2K paged ROM, MROM is located at F000 when
;- RFS is built for the SFD700.
;-
;--------------------------------------------------------------------------------------------------------
;- This source file is free software: you can redistribute it and-or modify

24
asm/sa-5510_rfs.asm
View File

@@ -96,13 +96,23 @@ ONTYO EQU 0119FH
OCTV EQU 011A0H
RATIO EQU 011A1H
BUFER EQU 011A3H
CMT_RDINF EQU 0E886H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU 0E889H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU 0E88CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU 0E88FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU 0E892H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU 0E895H ; UROMADDR+95H - SD directory command.
PRGSTART EQU 011FDH ; Build includes the tape copy code under original build.
; RFS ROM addresses.
UROMADDR EQU 0E800H ; Start of User ROM Address space.
UROMBSTBL EQU UROMADDR + 020H ; Entry point to the bank switching table.
RFSJMPTABLE EQU UROMADDR + 000B0H ; Start of jump table.
;-------------------------------------------------------
; Function entry points in the RFS ROM.
;-------------------------------------------------------
CMT_RDINF EQU RFSJMPTABLE + 06H ; UROMADDR+86H - Tape/SD intercept handler - Read Header
CMT_RDDATA EQU RFSJMPTABLE + 09H ; UROMADDR+89H - Tape/SD intercept handler - Read Data
CMT_WRINF EQU RFSJMPTABLE + 0CH ; UROMADDR+80H - Tape/SD intercept handler - Write Header
CMT_WRDATA EQU RFSJMPTABLE + 0FH ; UROMADDR+8FH - Tape/SD intercept handler - Write Data
CMT_VERIFY EQU RFSJMPTABLE + 12H ; UROMADDR+92H - Tape/SD intercept handler - Verify Data
CMT_DIR EQU RFSJMPTABLE + 15H ; UROMADDR+95H - SD directory command.
CNV_ATOS EQU RFSJMPTABLE + 18H ; UROMADDR+98H - Convert an ASCII string into Sharp ASCII
PRGSTART EQU 011FDH ; Build includes the tape copy code under original build.
; Original build set the tape handlers to original.
IF BUILD_ORIG = 1

253
asm/sa1510.asm
View File

@@ -42,10 +42,14 @@ START: LD SP,STACK
CALL ?CLER ; Clear 256 bytes from NAME 10F1h to 11F0h
LD A,016H
CALL PRNT
IF MODE80C = 0
LD A,007H ; Black background, white characters. Bit 7 is clear as a write to bit 7 @ DFFFH selects 40Char mode.
IF KUMABIN = 1
LD A,0CFH
ELSE
LD A,017H ; Blue background, white characters in colour mode. Bit 7 is set as a write to bit 7 @ DFFFH selects 80Char mode.
IF MODE80C+KUMA80 = 0
LD A,007H ; Black background, white characters. Bit 7 is clear as a write to bit 7 @ DFFFH selects 40Char mode.
ELSE
LD A,017H ; Blue background, white characters in colour mode. Bit 7 is set as a write to bit 7 @ DFFFH selects 80Char mode.
ENDIF
ENDIF
LD HL,ARAM
JR STRT1
@@ -61,7 +65,7 @@ STRT1: CALL CLR8
CALL NL
LD DE,00100H
RST 018H
IF MODE80C = 0 ; For 80 char mode we need a hook to setup SPAGE mode.
IF MODE80C+KUMA80 = 0 ; For 80 char mode we need a hook to setup SPAGE mode.
CALL ?BEL
ELSE
CALL HOOK ; Call new routine to setup SPAGE.
@@ -130,53 +134,88 @@ LOAD: CALL ?RDI
JR C,ST1
JP (HL)
; LOADING
MSG?2: DB 04CH, 0B7H, 0A1H, 09CH
DB 0A6H, 0B0H, 097H, 020H
DB 00DH
; SIGN ON BANNER
MSG?3: DB "** MONITOR SA-1510 **", 0DH
; SIGN ON BANNER - Different for Kuma 80 BIOS
MSG?3: IF KUMABIN = 0
DB "** MONITOR SA-1510 **", 0DH
ELSE
DB "*K",0A5H,0B3H,0A1H," MZ-80A M",0B7H,0B0H,0A6H
DB 096H,0B7H,09DH,"*",00DH,"*",00DH
ENDIF
; For 80 Character mode we need some space, so shorten the Check Sum Error message.
;
; CHECK SUM ERROR
MSGE1: IF MODE80C = 0
MSGE1: IF MODE80C+KUMA80 = 0
DB 043H, 098H, 092H, 09FH, 0A9H, 020H, 0A4H, 0A5H
DB 0B3H, 020H, 092H, 09DH, 09DH, 0B7H, 09DH, 00DH
ELSE
DB "CK SUM?", 0DH
ENDIF
; Hook = 7 bytes.
HOOK: IF MODE80C = 1
; Hook = 7 bytes using space taken from Check Sum message.
HOOK: IF MODE80C+KUMA80 > 0
LD A,0FFH
LD (SPAGE),A
JP ?BEL ; Original called routine
ENDIF
; CR PAGE MODE1
.CR: CALL .MANG
RRCA
JP NC,CURS2
LD L,000H
INC H
CP ROW - 1 ; End of line?
JR Z,.CP1
INC H
JP CURS1
.CR: IF KUMABIN = 1
LD HL,(DSPXY)
JP CURS2
ELSE
CALL .MANG
RRCA
JP NC,CURS2
LD L,000H
INC H
CP ROW - 1 ; End of line?
JR Z,.CP1
INC H
JP CURS1
ENDIF
.CR1: IF KUMABIN = 1
NEG
LD (SPAGE),A
ADD A,004H
LD (KEYPF),A
RET
DB 00EH
ENDIF
.CP1: LD (DSPXY),HL
; SCROLLER
.SCROL: LD BC,SCRNSZ - COLW ; Scroll COLW -1 lines
.SCROL: IF KUMABIN = 1
LD BC, 0780H
ELSE
LD BC,SCRNSZ - COLW ; Scroll COLW -1 lines
ENDIF
LD DE,SCRN ; Start of the screen.
LD HL,SCRN + COLW ; Start of screen + 1 line.
IF KUMABIN = 1
LD HL,0D050H
ELSE
LD HL,SCRN + COLW ; Start of screen + 1 line.
ENDIF
LDIR
EX DE,HL
LD B,COLW ; Clear last line at bottom of screen.
IF KUMABIN = 1
LD B, 050H
ELSE
LD B,COLW ; Clear last line at bottom of screen.
ENDIF
CALL ?CLER
LD BC,0001AH
IF KUMABIN = 1
JP ?RSTR
ELSE
LD BC,0001AH
ENDIF
LD DE,MANG
LD HL,MANG + 1
LDIR
@@ -450,7 +489,7 @@ L02DB: LD A,(SUNDG)
RET
?BEL: PUSH DE
LD DE,00DB1H
LD DE,?BELD ;00DB1H
RST 030H
POP DE
RET
@@ -587,22 +626,46 @@ TIMIN: PUSH AF
EI
RET
.DSP03: EX DE,HL
LD (HL),001H
INC HL
LD (HL),000H
JP CURSR
.MANG2: LD A,(DSPXY + 1)
ADD A,L
LD L,A
LD A,(HL)
INC HL
RL (HL)
OR (HL)
RR (HL)
RRCA
EX DE,HL
LD HL,(DSPXY)
.DSP03: IF KUMABIN = 1
LD A,(SPAGE)
OR A
LD A,027H
RET Z
ADD A,A
INC A
RET
L03A7: PUSH BC
CALL .DSP03
LD B,A
LD A,L
CP B
POP BC
RET
L03B0: CALL .DSP03
LD L,A
XOR A
DEC H
RET
ELSE
EX DE,HL
LD (HL),001H
INC HL
LD (HL),000H
JP CURSR
.MANG2: LD A,(DSPXY + 1)
ADD A,L
LD L,A
LD A,(HL)
INC HL
RL (HL)
OR (HL)
RR (HL)
RRCA
EX DE,HL
LD HL,(DSPXY)
ENDIF
RET
LD C,H
@@ -1141,7 +1204,11 @@ L0743: DEC H
?MODE: LD HL,KEYPF
LD (HL),08AH
LD (HL),007H
LD (HL),005H
IF KUMABIN+KUMA80 > 0
LD (HL),005H
ELSE
LD (HL),004H
ENDIF
LD (HL),001H
RET
@@ -1264,13 +1331,17 @@ GETL5: CALL ?DPCT
JR AUTO2
CHGPA: XOR A
IF MODE80C = 1
IF MODE80C+KUMA80 > 0
JR CHGPK
ELSE
JR CHGPK1
ENDIF
CHGPK: LD A,0FFH
CHGPK1: LD (SPAGE),A
CHGPK1: IF KUMABIN = 1
CALL .CR1
ELSE
LD (SPAGE),A
ENDIF
LD A,0C6H
CALL ?DPCT
CHGP1: JP GETL0
@@ -1581,7 +1652,12 @@ REV2: JP ?RSTR
.MANG: LD HL,MANG
LD A,(SPAGE)
OR A
JP NZ,.MANG2
IF KUMABIN = 1
JR NZ,.MANG1 ; (+018H)
NOP
ELSE
JP NZ,.MANG2
ENDIF
LD A,(MGPNT)
.MANG3: SUB 008H
INC HL
@@ -2407,14 +2483,24 @@ DLY12A: CALL DLY3
CALL ?PONT
LD (HL),B
LD HL,(DSPXY)
LD A,L
DSP01: CP COLW - 1 ; End of line.
IF KUMABIN = 1
CALL L03A7
ELSE
LD A,L
ENDIF
DSP01: IF KUMABIN = 0
CP COLW - 1 ; End of line.
ENDIF
JR NZ,DSP04
CALL .MANG
JR C,DSP04
LD A,(SPAGE)
OR A
JP NZ,.DSP03
IF KUMABIN = 1
JP NZ,CURSR
ELSE
JP NZ,.DSP03
ENDIF
EX DE,HL
LD A,B
CP 007H
@@ -2535,8 +2621,12 @@ CURSU1: CALL MGP.D
JR CURS3
CURSR: LD HL,(DSPXY)
LD A,L
CP COLW - 1 ; End of line
IF KUMABIN = 1
CALL L03A7
ELSE
LD A,L
CP COLW - 1 ; End of line
ENDIF
JR NC,CURS2
INC L
JR CURS3
@@ -2555,8 +2645,12 @@ CURSL: LD HL,(DSPXY)
JR Z,CURS5A
DEC L
JR CURS3
CURS5A: LD L,COLW - 1 ; End of line
DEC H
CURS5A: IF KUMABIN = 1
CALL L03B0
ELSE
LD L,COLW - 1 ; End of line
DEC H
ENDIF
JP P,CURSU1
LD H,000H
LD (DSPXY),HL
@@ -2643,13 +2737,24 @@ INST: CALL .MANG
RRCA
LD L,COLW - 1 ; End of line
LD A,L
JR NC,INST1A
INC H
INST1A: CALL ?PNT1
PUSH HL
LD HL,(DSPXY)
JR NC,INST2
LD A,(COLW*2)-1 ; 04FH
IF KUMABIN = 1
JR NC,INST1B
LD A,028H
ADD A,L
LD L,A
INST1B: CALL ?PNT1
PUSH HL
LD HL,(DSPXY)
NOP
ELSE
JR NC,INST1A
INC H
INST1A: CALL ?PNT1
PUSH HL
LD HL,(DSPXY)
JR NC,INST2
LD A,(COLW*2)-1 ; 04FH
ENDIF
INST2: SUB L
LD B,A
POP DE
@@ -2720,16 +2825,30 @@ ROLU1: CALL MGP.I
PUSH HL
POP BC
LD DE,COLW
LD HL,SCRN - COLW
LD A,(SPAGE)
OR A
JR NZ,?PNT2
LD HL,(PAGETP)
SBC HL,DE
?PNT2: ADD HL,DE
DEC B
JP P,?PNT2
LD B,000H
IF KUMABIN = 1
LD HL,(PAGETP)
INC B
LD A,(SPAGE)
OR A
JR Z,L0FCE ; (+008H)
LD HL,0D000H
LD E,050H
JR L0FCE ; (+001H)
L0FCD: ADD HL,DE
L0FCE: DJNZ L0FCD ; (-003H)
NOP
ELSE
LD HL,SCRN - COLW
LD A,(SPAGE)
OR A
JR NZ,?PNT2
LD HL,(PAGETP)
SBC HL,DE
?PNT2: ADD HL,DE
DEC B
JP P,?PNT2
LD B,000H
ENDIF
ADD HL,BC
RES 3,H
POP DE

99
build.sh
View File

@@ -3,54 +3,71 @@
ROOT_DIR=`pwd`
SW_DIR=${ROOT_DIR}/
PROCESS_MZF_FILES=0
if [ "x$1" = '-m' ]; then
PROCESS_MZF_FILES=1
if [ "$1" = '-m' ]; then
PROCESS_MZF_FILES=1
fi
# Make sure cpmtools is compiled and available in the tools directory.
if [[ ! -f ${ROOT_DIR}/tools/cpmcp ]]; then
cd ${ROOT_DIR}/cpmtools
./configure -prefix=${ROOT_DIR}/tools -libdir=${ROOT_DIR}/tools/lib -bindir=${ROOT_DIR}/tools
make all
make install
cp ${ROOT_DIR}/config/diskdefs ${ROOT_DIR}/tools/share/
fi
# Update path to ensure we use our locally compiled tools.
export PATH=${ROOT_DIR}/tools:${PATH}
(
cd $SW_DIR
tools/assemble_rfs.sh
if [ $? != 0 ]; then
echo "RFS assembly failed..."
exit 1
fi
tools/assemble_cpm.sh
if [ $? != 0 ]; then
echo "CPM assembly failed..."
exit 1
fi
tools/assemble_roms.sh
if [ $? != 0 ]; then
echo "ROMS assembly failed..."
exit 1
fi
cd $SW_DIR
tools/assemble_rfs.sh
if [ $? != 0 ]; then
echo "RFS assembly failed..."
exit 1
fi
tools/assemble_cpm.sh
if [ $? != 0 ]; then
echo "CPM assembly failed..."
exit 1
fi
tools/assemble_roms.sh
if [ $? != 0 ]; then
echo "ROMS assembly failed..."
exit 1
fi
# Only needed if the program source tree changes, takes too long to run on every build!
if [[ ${PROCESS_MZF_FILES} -eq 1 ]]; then
tools/processMZFfiles.sh
if [ $? != 0 ]; then
echo "Failed to process MZF files into sectored variants...."
exit 1
fi
fi
# Only needed if the program source tree changes, takes too long to run on every build!
if [[ ${PROCESS_MFZ_FILES} -eq 1 ]]; then
tools/processMZFfiles.sh
if [ $? != 0 ]; then
echo "Failed to process MZF files into sectored variants...."
exit 1
fi
fi
tools/make_roms.sh
if [ $? != 0 ]; then
echo "ROM disk assembly failed..."
exit 1
fi
tools/make_cpmdisks.sh
if [ $? != 0 ]; then
echo "CPM disks assembly failed..."
exit 1
fi
tools/make_sdcard.sh
if [ $? != 0 ]; then
echo "SD card assembly failed..."
exit 1
fi
tools/make_roms.sh
if [ $? != 0 ]; then
echo "ROM disk assembly failed..."
exit 1
fi
tools/make_cpmdisks.sh
if [ $? != 0 ]; then
echo "CPM disks assembly failed..."
exit 1
fi
tools/make_sdcard.sh
if [ $? != 0 ]; then
echo "SD card assembly failed..."
exit 1
fi
)
if [ $? != 0 ]; then
exit 1
fi
echo ""
echo "Program ROMS via TL866 or similar using command:"
echo " minipro --infoic /dvlp/Projects/minipro/infoic.xml -p SST39SF040 -s -w roms/SFD700_256.bin"
echo ""
echo "Done!"

2
config/diskdefs vendored
View File

@@ -55,7 +55,7 @@ diskdef MZ80A-RFS-320
tracks 20
sectrk 128
blocksize 2048
maxdir 32
maxdir 64
skew 0
boottrk 0
os 2.2

1
cpmtools vendored Submodule

Submodule cpmtools added at e534e20c15

BIN
roms/SFD700.rom vendored Normal file
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BIN
roms/SHARP_MZ80A_RFS_IMAGE_0.img vendored
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BIN
roms/SHARP_MZ80A_RFS_IMAGE_2.img vendored
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BIN
roms/SHARP_MZ80A_RFS_IMAGE_6.img vendored
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BIN
roms/cbios.rom vendored
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BIN
roms/cbios_bank1.rom vendored
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BIN
roms/cbios_bank2.rom vendored
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BIN
roms/cbios_bank3.rom vendored
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BIN
roms/cbios_bank4.rom vendored
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BIN
roms/monitor_1Z-009B.rom vendored Executable file
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BIN
roms/monitor_1z-009b.rom vendored Executable file
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BIN
roms/monitor_sa1510.rom vendored
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BIN
roms/mz-1e05.rom vendored Normal file
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BIN
roms/mz-1e14.rom vendored Normal file
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BIN
roms/mz80afi_sfd700.rom vendored Normal file
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roms/rfs.rom vendored
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BIN
test vendored
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67
tools/assemble_rfs.sh Executable file
View File

@@ -0,0 +1,67 @@
#!/bin/bash
#########################################################################################################
##
## Name: assemble_rfs.sh
## Created: August 2018
## Author(s): Philip Smart
## Description: Sharp MZ series RFS ROM assembly tool
## This script takes Sharp MZ RFS ROMS in assembler format and compiles/assembles them
## into a ROM file using the GLASS Z80 assembler.
##
## Credits:
## Copyright: (c) 2018-23 Philip Smart <philip.smart@net2net.org>
##
## History: August 2018 - Initial script written.
## February 2023 - Updated as RFS extracted into seperate repository.
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
## it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This source file is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
ROOTDIR=`pwd | sed 's/\/tools//g'`
TOOLDIR=${ROOTDIR}/tools
JARDIR=${ROOTDIR}/tools
ASM=glass.jar
BUILDROMLIST="rfs rfs_mrom"
BUILDMZFLIST=""
ASMDIR=${ROOTDIR}/asm
ASMTMPDIR=${ROOTDIR}/tmp
INCDIR=${ROOTDIR}/asm/include
ROMDIR=${ROOTDIR}/roms
MZFDIR=${ROOTDIR}/MZB/Common
# Go through list and build image.
#
for f in ${BUILDROMLIST} ${BUILDMZFLIST}
do
echo "Assembling: $f..."
# Assemble the source.
echo "java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMTMPDIR}/${f}.obj ${ASMTMPDIR}/${f}.sym"
java -jar ${JARDIR}/${ASM} ${ASMDIR}/${f}.asm ${ASMTMPDIR}/${f}.obj ${ASMTMPDIR}/${f}.sym -I ${INCDIR}
# On successful compile, perform post actions else go onto next build.
#
if [ $? = 0 ]
then
# The object file is binary, no need to link, copy according to build group.
if [[ ${BUILDROMLIST} = *"${f}"* ]]; then
echo "Copy ${ASMTMPDIR}/${f}.obj to ${ROMDIR}/${f}.rom"
cp ${ASMTMPDIR}/${f}.obj ${ROMDIR}/${f}.rom
else
echo "Copy ${ASMTMPDIR}/${f}.obj to ${MZFDIR}/${f}.mzf"
cp ${ASMTMPDIR}/${f}.obj ${MZFDIR}/${f}.mzf
fi
fi
done

12
tools/assemble_roms.sh
View File

@@ -14,6 +14,7 @@
## History: August 2018 - Initial script written.
## March 2021 - Updated to compile different versions of Microsoft BASIC.
## February 2023 - Updated as RFS extracted into seperate repository.
## June 2023 - Updated to build KUMA version of monitor.
##
#########################################################################################################
## This source file is free software: you can redistribute it and#or modify
@@ -34,6 +35,7 @@ ROOTDIR=`pwd | sed 's/\/tools//g'`
TOOLDIR=${ROOTDIR}/tools
JARDIR=${ROOTDIR}/tools
ASM=glass.jar
# NB Kuma version of SA1510 monitor rom is enabled within the monitor_sa1510.asm or monitor_80c_sa1510.asm file.
#BUILDROMLIST="MZ80AFI rfs rfs_mrom IPL monitor_SA1510 monitor_80c_SA1510 monitor_mz-1r12 quickdisk_mz-1e05 quickdisk_mz-1e14 monitor_1Z-013A monitor_80c_1Z-013A"
BUILDROMLIST="monitor_sa1510_hiload monitor_80c_sa1510_hiload monitor_80c_sa1510 mz80afi monitor_sa1510 monitor_80c_sa1510 monitor_1z-013a monitor_80c_1z-013a ipl"
#BUILDMZFLIST="hi-ramcheck sharpmz-test"
@@ -62,19 +64,19 @@ do
# Special handling for the 4 version of MS BASIC.
if [[ ${SRCNAME} = "msbasic_mz80a" ]]; then
ASMNAME="msbasic.asm"
echo "BUILD_VERSION EQU 0" > ${INCDIR}/MSBASIC_BuildVersion.asm
echo "BUILD_VERSION EQU 0" > ${INCDIR}/msbasic_buildversion.asm
elif [[ ${SRCNAME} = "msbasic_rfs40" ]]; then
ASMNAME="msbasic.asm"
echo "BUILD_VERSION EQU 1" > ${INCDIR}/MSBASIC_BuildVersion.asm
echo "BUILD_VERSION EQU 1" > ${INCDIR}/msbasic_buildversion.asm
elif [[ ${SRCNAME} = "msbasic_rfs80" ]]; then
ASMNAME="msbasic.asm"
echo "BUILD_VERSION EQU 2" > ${INCDIR}/MSBASIC_BuildVersion.asm
echo "BUILD_VERSION EQU 2" > ${INCDIR}/msbasic_buildversion.asm
elif [[ ${SRCNAME} = "msbasic_rfstz" ]]; then
ASMNAME="msbasic.asm"
echo "BUILD_VERSION EQU 3" > ${INCDIR}/MSBASIC_BuildVersion.asm
echo "BUILD_VERSION EQU 3" > ${INCDIR}/msbasic_buildversion.asm
elif [[ ${SRCNAME} = "msbasic_tzfs" ]]; then
ASMNAME="msbasic.asm"
echo "BUILD_VERSION EQU 4" > ${INCDIR}/MSBASIC_BuildVersion.asm
echo "BUILD_VERSION EQU 4" > ${INCDIR}/msbasic_buildversion.asm
fi
# Assemble the source.

14
tools/make_cpmdisks.sh
View File

@@ -33,6 +33,11 @@
## along with this program. If not, see <http://www.gnu.org/licenses/>.
#########################################################################################################
echo "--------------------------------------------------------------------------------"
echo "cpmtool package contains a bug. If cpmcp aborts with malloc issue,"
echo "obtain and compile cpmtools locally and update path to point to your local copy."
echo "--------------------------------------------------------------------------------"
# These two variables configure which CPM images and disks to build. If only 1 CPM_RFS ROM Drive is needed,
# remove it fro the lists.
#BUILDCPMLIST="cpm22 CPM_RFS_1"
@@ -125,10 +130,11 @@ echo "Creating CPM Disks from all the directories in:$CPM_PATH} matching this fi
# Build the SD Card images, these images differ as they are larger and combine more programs in one disk under different user numbers.
# Copy a blank image to create the new disk.
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK1.RAW;
# cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK1.RAW;
# Copy the CPM files from the linux filesystem into the CPM Disk under the CPM filesystem.
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK0.RAW;
echo "SDCDISK0.RAW..."
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK0.RAW ${CPM_PATH}/CPM00_SYSTEM/*.* 0:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK0.RAW ${CPM_PATH}/CPM01_TURBOP/*.* 1:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK0.RAW ${CPM_PATH}/CPM02_HI_C/*.* 2:
@@ -146,6 +152,7 @@ echo "Creating CPM Disks from all the directories in:$CPM_PATH} matching this fi
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK0.RAW ${CPM_PATH}/CPM33_ZCPR3_COMMON/*.* 14:
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK1.RAW;
echo "SDCDISK1.RAW..."
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK1.RAW ${CPM_PATH}/CPM12_PASCALMTP_v561/*.* 0:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK1.RAW ${CPM_PATH}/CPM26_TPASCAL_v300a/*.* 1:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK1.RAW ${CPM_PATH}/CPM13_MTPUG_01/*.* 2:
@@ -160,6 +167,7 @@ echo "Creating CPM Disks from all the directories in:$CPM_PATH} matching this fi
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK1.RAW ${CPM_PATH}/CPM22_MTPUG_10/*.* 11:
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK2.RAW;
echo "SDCDISK2.RAW..."
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK2.RAW ${CPM_PATH}/CPM23_PLI/*.* 0:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK2.RAW ${CPM_PATH}/CPM24_PLI80_v13/*.* 1:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK2.RAW ${CPM_PATH}/CPM25_PLI80_v14/*.* 2:
@@ -169,6 +177,7 @@ echo "Creating CPM Disks from all the directories in:$CPM_PATH} matching this fi
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK2.RAW ${CPM_PATH}/CPM30_WORDSTAR_v400/*.* 6:
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK3.RAW;
echo "SDCDISK3.RAW..."
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK3.RAW ${CPM_PATH}/CPM_MC_C0/*.* 0:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK3.RAW ${CPM_PATH}/CPM_MC_C1/*.* 1:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK3.RAW ${CPM_PATH}/CPM_MC_C2/*.* 2:
@@ -181,6 +190,7 @@ echo "Creating CPM Disks from all the directories in:$CPM_PATH} matching this fi
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK3.RAW ${CPM_PATH}/CPM_MC_C9/*.* 9:
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK4.RAW;
echo "SDCDISK4.RAW..."
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK4.RAW ${CPM_PATH}/CPM_MC_D0/*.* 0:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK4.RAW ${CPM_PATH}/CPM_MC_D1/*.* 1:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK4.RAW ${CPM_PATH}/CPM_MC_D2/*.* 2:
@@ -194,6 +204,7 @@ echo "Creating CPM Disks from all the directories in:$CPM_PATH} matching this fi
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK4.RAW ${CPM_PATH}/CPM_MC_D9/*.* 9:
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK5.RAW;
echo "SDCDISK5.RAW..."
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK5.RAW ${CPM_PATH}/CPM_MC_E0/*.* 0:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK5.RAW ${CPM_PATH}/CPM_MC_E1/*.* 1:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK5.RAW ${CPM_PATH}/CPM_MC_E2/*.* 2:
@@ -206,6 +217,7 @@ echo "Creating CPM Disks from all the directories in:$CPM_PATH} matching this fi
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK5.RAW ${CPM_PATH}/CPM_MC_E9/*.* 9:
cp ${CPM_PATH}/BLANKFD/BLANK_16M.RAW ${SDC16M_PATH}/RAW/SDCDISK6.RAW;
echo "SDCDISK6.RAW..."
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK6.RAW ${CPM_PATH}/CPM_MC_F0/*.* 0:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK6.RAW ${CPM_PATH}/CPM_MC_F1/*.* 1:
cpmcp -f MZ80A-SDC16M ${SDC16M_PATH}/RAW/SDCDISK6.RAW ${CPM_PATH}/CPM_MC_F2/*.* 2:

1253
tools/make_roms.sh
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File diff suppressed because it is too large Load Diff

8
tools/processMZFfiles.sh
View File

@@ -39,7 +39,8 @@ MZBDIR=${ROOTDIR}/MZB
BLOCKSIZELIST="128 256"
# Build list of files to process.
for SUBDIR in Common MZ-80A MZ-80K MZ-700 MZ-800 MZ-1500 MZ-2000 MZ-80B
# for SUBDIR in Common MZ-80A MZ-80K MZ-700 MZ-800 MZ-1500 MZ-2000 MZ-80B
for SUBDIR in Common MZ-1200 MZ-1500 MZ-2000 MZ-2200 MZ-2500 MZ-2800 MZ-700 MZ-700-2 MZ-800 MZ-80A MZ-80B MZ-80C MZ-80K
do
cd ${MZFDIR}
ls -l ${SUBDIR}/*.MZF ${SUBDIR}/*.mzf 2>/dev/null |\
@@ -82,4 +83,9 @@ do
done
done
done </tmp/filelist
if [[ "${SUBDIR}" = "MZ-700-2" ]]; then
cp ${MZBDIR}/${SUBDIR}/* ${MZBDIR}/MZ-700/
fi
done