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Updates to Video Module

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This commit is contained in:
Philip Smart
2020-11-08 00:18:40 +00:00
parent 82a4166db1
commit 52d0700aca
9 changed files with 74 additions and 55 deletions
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15
CPLD/VideoInterface.vhd
View File

@@ -79,6 +79,7 @@ entity VideoInterface is
VRAMD : inout std_logic_vector(7 downto 0); -- Z80 Data bus from the VRAM chip, gated according to state signals.
--VMEM_CSn : out std_logic; -- Extended memory select to FPGA.
VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VWAITn : in std_logic; -- WAIT signal from FPGA asserted during active frame display period.
VZ80_IORQn : out std_logic; -- IORQn to FPGA.
VZ80_RDn : out std_logic; -- Z80_RDn from tranZPUter to FPGA.
VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA.
@@ -98,7 +99,7 @@ entity VideoInterface is
VMB_LOAD : out std_logic -- shift register load signal from the Colour Card CN! connector.
-- Reserved.
--TBA : in std_logic_vector(4 downto 0) -- Reserved signals.
--TBA : in std_logic_vector(1 downto 0) -- Reserved signals.
);
end entity;
@@ -159,7 +160,7 @@ architecture rtl of VideoInterface is
signal MODE_VIDEO_MZ80C : std_logic := '0'; -- The machine is running in MZ80C mode.
signal MODE_VIDEO_MZ1200 : std_logic := '0'; -- The machine is running in MZ1200 mode.
signal MODE_VIDEO_MZ2000 : std_logic := '0'; -- The machine is running in MZ2000 mode.
signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable.
signal GRAM_PAGE_ENABLE : std_logic; -- Graphics mode page enable.
signal GRAM_MZ80B_ENABLE : std_logic; -- MZ80B Graphics memory enabled flag.
signal MZ80B_VRAM_HI_ADDR : std_logic; -- Video RAM located at D000:FFFF when high.
signal MZ80B_VRAM_LO_ADDR : std_logic; -- Video RAM located at 5000:7FFF when high.
@@ -441,7 +442,7 @@ begin
MODE_VIDEO_MZ80C <= '0';
MODE_VIDEO_MZ1200 <= '0';
MODE_VIDEO_MZ2000 <= '0';
GRAM_PAGE_ENABLE <= "00";
GRAM_PAGE_ENABLE <= '0';
MZ80B_VRAM_HI_ADDR <= '0';
MZ80B_VRAM_LO_ADDR <= '0';
MODE_CPLD_SWITCH <= '0';
@@ -519,9 +520,9 @@ begin
end case;
end if;
-- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' and CS_LAST_LEVEL(2) = '1' then
GRAM_PAGE_ENABLE <= D(1 downto 0);
-- memory page register. [0] switches in 16Kb page (1 of 3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = Off, 1 = Enabled. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' and CS_LAST_LEVEL(2) = '1' and S_VIDEO_WRn = '0' then
GRAM_PAGE_ENABLE <= D(0);
end if;
-- MZ80B Z80 PIO.
@@ -580,7 +581,7 @@ begin
else '1';
CS_DARAMn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11011"
else '1';
CS_EXXXn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11100" and GRAM_PAGE_ENABLE = "00" and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
CS_EXXXn <= '0' when S_IORQn = '1' and VA(15 downto 11) = "11100" and GRAM_PAGE_ENABLE = '0' and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
else '1';
--

4
CPLD/VideoInterface_Toplevel.vhd
View File

@@ -79,6 +79,7 @@ entity VideoInterfaceCPLD is
VZ80_RDn : out std_logic; -- RDn to FPGA.
VZ80_WRn : out std_logic; -- WRn to FPGA.
VVRAM_CS_INn : out std_logic; -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VWAITn : in std_logic; -- WAIT signal from FPGA asserted during active frame display period.
VCSn : out std_logic; -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn : out std_logic; -- Video Gate (GTn)
VRESETn : out std_logic; -- Reset to FPGA.
@@ -96,7 +97,7 @@ entity VideoInterfaceCPLD is
VMB_LOAD : out std_logic -- shift register load signal from the Colour Card CN! connector.
-- Reserved.
--TBA : in std_logic_vector(4 downto 0) -- Reserved signals.
--TBA : in std_logic_vector(1 downto 0) -- Reserved signals.
);
END entity;
@@ -156,6 +157,7 @@ begin
VZ80_RDn => VZ80_RDn, -- RDn to FPGA.
VZ80_WRn => VZ80_WRn, -- WRn to FPGA.
VVRAM_CS_INn => VVRAM_CS_INn, -- Chip Select for access to the Video RAM from the mainboard IC15 socket.
VWAITn => VWAITn, -- WAIT signal from FPGA asserted during active frame display period.
VCSn => VCSn, -- Video RAM Attribute Chip Select (CSn) to FPGA.
VGTn => VGTn, -- Video Gate (GTn)

2
CPLD/build/VideoInterface.qsf
View File

@@ -190,6 +190,7 @@ set_location_assignment PIN_46 -to VCSn
set_location_assignment PIN_47 -to VGTn
set_location_assignment PIN_44 -to VZ80_IORQn
#set_location_assignment PIN_43 -to VMEM_CSn
set_location_assignment PIN_67 -to VWAITn
set_location_assignment PIN_45 -to VZ80_RDn
set_location_assignment PIN_49 -to VRESETn
set_location_assignment PIN_27 -to VVRAM_CS_INn
@@ -197,7 +198,6 @@ set_location_assignment PIN_48 -to VZ80_WRn
# Reserved.
# =========
#set_location_assignment PIN_67 -to TBA[2]
#set_location_assignment PIN_66 -to TBA[1]
#set_location_assignment PIN_65 -to TBA[0]

20
CPLD/build/VideoInterface.srf
View File

@@ -35,5 +35,25 @@
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(128): object \"MODE_CPLD_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(129): object \"MODE_CPLD_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(130): object \"MODE_CPLD_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(131): object \"MODE_CPLD_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(132): object \"MODE_CPLD_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(133): object \"MODE_CPLD_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(134): object \"MODE_CPLD_MZ80B\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(135): object \"MODE_CPLD_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(136): object \"MODE_CPLD_SWITCH\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(137): object \"MODE_CPLD_MB_VIDEOn\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(155): object \"MODE_VIDEO_MZ80A\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(156): object \"MODE_VIDEO_MZ700\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(157): object \"MODE_VIDEO_MZ800\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(159): object \"MODE_VIDEO_MZ80K\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(160): object \"MODE_VIDEO_MZ80C\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(161): object \"MODE_VIDEO_MZ1200\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(162): object \"MODE_VIDEO_MZ2000\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(149): object \"CS_DXXXn\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(151): object \"CS_DVRAMn\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at VideoInterface.vhd(152): object \"CS_DARAMn\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 163076 "" 0 0 "Quartus II" 0 -1 0 ""}

1
CPLD/build/VideoInterface_constraints.sdc
View File

@@ -183,6 +183,7 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VVRAM_CS_INn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_HBLNKn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_LOAD}]

56
FPGA/VideoController.vhd
View File

@@ -82,6 +82,7 @@ entity VideoController is
VZ80_IORQn : in std_logic; -- IORQn to FPGA.
VZ80_RDn : in std_logic; -- RDn to FPGA.
VZ80_WRn : in std_logic; -- WRn to FPGA.
VWAITn : out std_logic; -- WAIT signal to CPU when accessing video RAM when busy.
-- VGA signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
@@ -281,7 +282,7 @@ architecture rtl of VideoController is
signal GRAM_OPT_WRITE : std_logic; -- Graphics write to GRAMI (0) or GRAMII (1) for MZ80B/MZ2000
signal GRAM_OPT_OUT1 : std_logic; -- Graphics enable GRAMI output to display
signal GRAM_OPT_OUT2 : std_logic; -- Graphics enable GRAMII output to display
signal GRAM_PAGE_ENABLE : std_logic_vector(1 downto 0); -- Graphics mode page enable.
signal GRAM_PAGE_ENABLE : std_logic; -- Graphics mode page enable.
signal VIDEO_MODE_REG : std_logic_vector(7 downto 0); -- Programmable mode register to control video mode.
signal PAGE_MODE_REG : std_logic_vector(7 downto 0); -- Current value of the Page register.
signal PALETTE_REG : std_logic_vector(7 downto 0); -- Palette register to apply mapping to the digital RGB output.
@@ -1811,12 +1812,12 @@ begin
-- 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
--
-- IO Range for Graphics enhancements is set by the Video Mode registers at 0xF5->.
-- 0xF8=<val> sets the mode of the Video Module. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
-- 0xF8=<val> sets the mode of the Video Module. [2:0] - 000 = MZ-80K, 001 = MZ-80C, 010 = MZ-1200, 011 = MZ--80A, 100 = MZ-700, 101 = MZ-800, 110 = MZ-80B, 111 = MZ-2000. [3] = 0 - 40 col, 1 - 80 col, [4] = 0 - mono, 1 - colour.
-- 0xF9=<val> sets the graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
-- 0xFA=<val> sets the Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- 0xFB=<val> sets the Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- 0xFC=<val> sets the Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
-- 0xFD=<val> memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
-- 0xFD=<val> memory page register. [0] switches in 16Kb page (1 of 3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = off, 1 = GRAM enabled. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
--
CTRLREGISTERS: process( VRESETn, IF_CLK, CGROM_PAGE, GRAM_PAGE_ENABLE, VIDEOMODE, MZ80B_VRAM_HI_ADDR, MZ80B_VRAM_LO_ADDR )
begin
@@ -1847,7 +1848,7 @@ begin
MODE_CPLD_SWITCH <= '0';
VIDEO_MODE_REG <= "00000000";
VGAMODE <= "00";
GRAM_PAGE_ENABLE <= "00";
GRAM_PAGE_ENABLE <= '0';
CGROM_PAGE <= '0';
DISABLE_INT_DISPLAY <= '0';
DISPLAY_VGATE <= '0';
@@ -2110,9 +2111,9 @@ begin
GRAM_OPT_OUT2 <= VDATA(2);
end if;
-- memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
-- memory page register. [0] switches in 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [0] = page, 0 = off, 1 = GRAM paged in. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
if CS_FB_PAGEn = '0' and VZ80_WRn = '0' and VZ80_WR_LASTn = '1' then
GRAM_PAGE_ENABLE <= VDATA(1 downto 0);
GRAM_PAGE_ENABLE <= VDATA(0);
CGROM_PAGE <= VDATA(7);
end if;
@@ -2257,8 +2258,8 @@ begin
end if;
-- Non-registered signal vectors for readback.
-- Page register: [7] = CGROM Page setting, [6:1] = Current video mode, [1:0] = GRAM Page setting.
PAGE_MODE_REG <= CGROM_PAGE & std_logic_vector(to_unsigned(VIDEOMODE, 5)) & GRAM_PAGE_ENABLE;
-- Page register: [7] = CGROM Page setting, [6:2] = Current video mode, [0] = GRAM enabled setting.
PAGE_MODE_REG <= CGROM_PAGE & std_logic_vector(to_unsigned(VIDEOMODE, 5)) & '0' & GRAM_PAGE_ENABLE;
-- MZ80B Graphics RAM is enabled whenever one of the two control lines goes active.
GRAM_MZ80B_ENABLE <= MZ80B_VRAM_HI_ADDR or MZ80B_VRAM_LO_ADDR;
@@ -2276,17 +2277,17 @@ begin
else '1';
CS_DARAMn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "011"
else '1';
CS_EXXXn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "100" and GRAM_PAGE_ENABLE = "00" and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
CS_EXXXn <= '0' when VZ80_IORQn = '1' and VADDR(13 downto 11) = "100" and GRAM_PAGE_ENABLE = '0' and (MODE_VIDEO_MZ80B = '0' or (MODE_VIDEO_MZ80B = '1' and GRAM_MZ80B_ENABLE = '0')) -- Normal memory mapped I/O if Graphics Option not enabled.
else '1';
-- MZ80B Graphics RAM enabled, range E000:FFFF is mapped to graphics RAMI + II and D000:DFFF to standard video.
CS_GRAMn <= '0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"D000" and unsigned(VADDR(15 downto 0)) <= X"FFFF" and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1'
CS_GRAMn <= '0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"D000" and unsigned(VADDR(15 downto 0)) <= X"FFFF" and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_HI_ADDR = '1'
else
-- MZ80B Graphics RAM enabled, range 6000:7FFF is mapped to graphics RAMI + II and 5000:5FFF to standard video.
'0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"5000" and unsigned(VADDR(15 downto 0)) <= X"7FFF" and GRAM_PAGE_ENABLE = "00" and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1'
'0' when VZ80_IORQn = '1' and unsigned(VADDR(15 downto 0)) >= X"5000" and unsigned(VADDR(15 downto 0)) <= X"7FFF" and GRAM_PAGE_ENABLE = '0' and MODE_VIDEO_MZ80B = '1' and MZ80B_VRAM_LO_ADDR = '1'
else '1';
-- Graphics RAM enabled, range C000:FFFF is mapped to graphics RAM.
CS_FBRAMn <= '0' when VZ80_IORQn = '1' and VADDR(15 downto 14) = "11" and GRAM_PAGE_ENABLE /= "00"
else '0';
CS_FBRAMn <= '0' when VZ80_IORQn = '1' and VADDR(15 downto 14) = "11" and GRAM_PAGE_ENABLE = '1'
else '1';
CS_IO_6XXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "0110"
else '1';
CS_IO_DXXn <= '0' when VZ80_IORQn = '0' and VADDR(7 downto 4) = "1101"
@@ -2381,17 +2382,17 @@ begin
-- Data for CPU to read, dependent on what is being accessed.
VDATA <= VRAM_VIDEO_DATA when VZ80_RDn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0'
else
GRAM_DO_R when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "01" and GRAM_MODE_REG(1 downto 0) = "00" -- For direct framebuffer access, C000:FFFF is assigned to the framebuffer during a read if the GRAM_PAGE_ENABLE register is not 0.
GRAM_DO_R when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_MODE_REG(1 downto 0) = "00" -- For direct framebuffer access, C000:FFFF is assigned to the framebuffer during a read if the GRAM_PAGE_ENABLE register is not 0.
else
GRAM_DO_B when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "10" and GRAM_MODE_REG(1 downto 0) = "01"
GRAM_DO_B when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_MODE_REG(1 downto 0) = "01"
else
GRAM_DO_G when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "11" and GRAM_MODE_REG(1 downto 0) = "10"
GRAM_DO_G when VZ80_RDn = '0' and CS_FBRAMn = '0' and GRAM_MODE_REG(1 downto 0) = "10"
else
GRAM_DO_GI when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '0' -- For MZ80B GRAM I memory read - lower 8K of red framebuffer.
else
GRAM_DO_GII when VZ80_RDn = '0' and CS_GRAMn = '0' and GRAM_OPT_WRITE = '1' -- For MZ80B GRAM II memory read - lower 8K of blue framebuffer.
else
VIDEO_MODE_REG when VZ80_RDn = '0' and CS_FB_VMn = '0'
V_BLANKi & H_BLANKi & VIDEO_MODE_REG(5 downto 0)when VZ80_RDn = '0' and CS_FB_VMn = '0'
else
GRAM_MODE_REG when VZ80_RDn = '0' and CS_FB_CTLn = '0'
else
@@ -2483,6 +2484,11 @@ begin
else
(others=>'Z');
-- Wait state generation, when the GRAM Frame Buffer is being written to and the CPU is attempting to write, pause the CPU.
VWAITn <= '0' when V_BLANKi = '1' and CS_FBRAMn = '0'
else '1';
-- VRAM mux between the CPU signals and the GPU. GPU takes priority.
--
VRAM_ADDR <= VRAM_GPU_ADDR(11 downto 0) when VRAM_GPU_ENABLE = '1'
@@ -2493,7 +2499,7 @@ begin
VDATA;
VRAM_WEN <= '1' when VRAM_GPU_WEN = '1'
else
'1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0' and GRAM_PAGE_ENABLE = "00"
'1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '0' and GRAM_PAGE_ENABLE = '0'
else '0';
VRAM_VIDEO_DATA <= VRAM_DO;
@@ -2516,7 +2522,7 @@ begin
else (others => '1');
CG_ADDR <= CGRAM_ADDR(11 downto 0) when CGRAM_WEn = '0'
else XFER_CGROM_ADDR;
CGROM_WEN <= '1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '1' and GRAM_PAGE_ENABLE = "00"
CGROM_WEN <= '1' when VZ80_WRn = '0' and CS_DXXXn = '0' and CGROM_PAGE = '1' and GRAM_PAGE_ENABLE = '0'
else '0';
@@ -2557,23 +2563,17 @@ begin
GRAM_DO_G <= GRAM_DO_GIII;
GWEN_R <= '1' when GWEN_GPU_R = '1'
else
'1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "01" and GRAM_MODE_REG(3 downto 2) = "00"
else
'1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11"
'1' when VZ80_WRn = '0' and CS_FBRAMn = '0' and (GRAM_MODE_REG(3 downto 2) = "00" or GRAM_MODE_REG(3 downto 2) = "11")
else
'0';
GWEN_B <= '1' when GWEN_GPU_B = '1'
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "11" and GRAM_MODE_REG(3 downto 2) = "10"
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11"
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and (GRAM_MODE_REG(3 downto 2) = "10" or GRAM_MODE_REG(3 downto 2) = "11")
else
'0';
GWEN_G <= '1' when GWEN_GPU_G = '1'
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE = "10" and GRAM_MODE_REG(3 downto 2) = "01"
else
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and GRAM_PAGE_ENABLE /= "00" and GRAM_MODE_REG(3 downto 2) = "11"
'1' when VZ80_WRn='0' and CS_FBRAMn = '0' and (GRAM_MODE_REG(3 downto 2) = "01" or GRAM_MODE_REG(3 downto 2) = "11")
else
'0';

2
FPGA/VideoController_Toplevel.vhd
View File

@@ -51,6 +51,7 @@ entity VideoControllerFPGA is
VZ80_IORQn : in std_logic; -- IORQn to FPGA.
VZ80_RDn : in std_logic; -- RDn to FPGA.
VZ80_WRn : in std_logic; -- WRn to FPGA.
VWAITn : out std_logic; -- WAIT signal to CPU when accessing video RAM when busy.
-- VGA signals.
VGA_R : out std_logic_vector(3 downto 0); -- 16 level Red output.
@@ -150,6 +151,7 @@ begin
VZ80_IORQn => VZ80_IORQn, -- IORQn to FPGA.
VZ80_RDn => VZ80_RDn, -- RDn to FPGA.
VZ80_WRn => VZ80_WRn, -- WRn to FPGA.
VWAITn => VWAITn, -- WAIT signal to CPU when accessing video RAM when busy.
-- VGA signals.
VGA_R => VGA_R, -- 16 level Red output.

10
FPGA/build/VideoController.qsf
View File

@@ -156,6 +156,7 @@ set_location_assignment PIN_114 -to VZ80_RDn
set_location_assignment PIN_110 -to VRESETn
#set_location_assignment PIN_28 -to VVRAM_CS_INn
set_location_assignment PIN_111 -to VZ80_WRn
set_location_assignment PIN_85 -to VWAITn
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VCSn
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGTn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_IORQn
@@ -164,6 +165,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_RDn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VRESETn
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VVRAM_CS_INn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VZ80_WRn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VWAITn
# VGA/RGB signals.
# ================
@@ -250,14 +252,8 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VMB_VIDEO
# Reserved.
# =========
#set_location_assignment PIN_80 -to TBA[4]
#set_location_assignment PIN_83 -to TBA[3]
#set_location_assignment PIN_85 -to TBA[2]
#set_location_assignment PIN_86 -to TBA[1]
#set_location_assignment PIN_87 -to TBA[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[4]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[3]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[2]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[1]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TBA[0]
@@ -282,4 +278,6 @@ set_global_assignment -name SDC_FILE VideoController_constraints.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

7
FPGA/build/VideoController_constraints.sdc
View File

@@ -95,12 +95,6 @@ set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VD
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[9]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[8]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[7]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[6]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[5]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[4]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[3]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[2]}]
#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {TBA[1]}]
@@ -124,6 +118,7 @@ set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {V
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGA_B[2]}]