233 lines
14 KiB
Tcl
233 lines
14 KiB
Tcl
## Generated SDC file "VideoInterface.out.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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## DATE "Mon Aug 17 12:55:02 2020"
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##
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## DEVICE "EPM7512AETC144-12"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {CLOCK_50} -period 20.00 -waveform { 0.000 10.00 } [get_ports { CLOCK_50 }]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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create_clock -name {VideoInterface:myVirtualToplevel|CLK16Mi} -period 62.5 [get_keepers {VideoInterface:myVirtualToplevel|CLK16Mi}]
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create_clock -name {VideoInterface:myVirtualToplevel|CLK24Mi} -period 41.667 [get_keepers {VideoInterface:myVirtualToplevel|CLK24Mi}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLOCK_50}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[13]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[12]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[11]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[10]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[9]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[8]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[7]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[6]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[5]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[4]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[3]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[2]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[1]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {A[0]}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {IORQn}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MEM_CSn}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {WRn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CSn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {GTn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RESETn}]
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#set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {RDn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[3]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[2]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[1]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {INDATA[0]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAM_CS_INn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[7]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[6]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[5]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[4]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[3]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[2]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[1]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[0]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[7]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[6]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[5]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[4]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[3]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[2]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[1]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[0]}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MB_RESETn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MB_HBLNKn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MB_LOAD}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MB_SYNCH}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MB_V_HBLNKn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {MB_VIDEO}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSRVIDEO_OUT}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VSYNCH_OUT}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VVBLNK_OUTn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VHBLNK_OUTn}]
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set_input_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VHSY_OUT}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[7]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[6]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[5]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[4]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {D[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[15]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[14]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[13]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[12]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[11]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[10]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[9]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[8]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[7]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[6]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[5]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[4]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VADDR[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[7]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[6]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[5]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[4]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VDATA[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[7]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[6]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[5]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[4]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[3]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[2]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[1]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRAMD[0]}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {HBLNK_OUTn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {HSY_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SRVIDEO_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {SYNCH_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VBLNK_OUTn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VCSn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VGTn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_IORQn}]
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#set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMEM_CSn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_RDn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VRESETn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VVRAM_CS_INn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VWAITn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VZ80_WRn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_HBLNKn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_LOAD}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_SYNCH}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_V_HBLNKn}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {VMB_VIDEO}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLK_1MHZ_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLK_2MHZ_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {CLK_31_5K_OUT}]
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set_output_delay -add_delay -clock [get_clocks {CLOCK_50}] 1.000 [get_ports {OUTCLK}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -from [get_clocks {VideoInterface:myVirtualToplevel|CLK16Mi}] -to [get_clocks {CLOCK_50}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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