55 lines
2.3 KiB
Plaintext
Executable File
55 lines
2.3 KiB
Plaintext
Executable File
Name CPU decoder PAL;
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Partno CPUDEC 1;
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Date 24/02/88;
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Revision 01;
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Designer P.D. Smart;
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Company Feduptronics;
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Assembly XXXXX;
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Location XXXXX;
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/******************************************************************/
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/* A PAL to decode the 286 I/O ports to generate the 5 select */
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/* signals required. */
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/* */
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/******************************************************************/
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/* Allowable Target Device Types: 16L8 */
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/******************************************************************/
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/** Inputs **/
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Pin 1 = IOWR ; /* IOWR signal from 286 */
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Pin 2 = IORD ; /* IORD signal from 286 */
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Pin 3 = A1 ; /* Address signals from 286 */
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Pin 4 = A2 ; /* */
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Pin 5 = A10 ; /* */
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Pin 6 = A11 ; /* */
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Pin 7 = A19 ; /* */
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Pin 8 = RESET ; /* Reset signal from CPU */
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Pin 9 = MEMRES ; /* Memory reset pin */
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/** Outputs **/
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Pin 19 = LINKWR ; /* Signal to initiate a link write*/
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Pin 18 = LINKRD ; /* Signal to initiate a link read */
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Pin 17 = COMWR ; /* Write to command port */
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Pin 16 = STATRD ; /* Read from status port */
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Pin 15 = FF1 ; /* Flip flop output 1 */
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Pin 14 = FF2 ; /* Flip flop output 2 */
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Pin 13 = ROMSEL ; /* Select ROM */
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Pin 12 = LOADSHIFT ; /* Load shift register signal */
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/** Declarations and Intermediate Variable Definitions **/
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/** Logic Equations **/
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LINKWR = !(IOWR # !IORD # A1 # A2 # !A10 # !A11);
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LINKRD = !IOWR # IORD # A1 # A2 # !A10 # !A11;
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COMWR = !(IOWR # !IORD # !A1 # A2 # !A10 # !A11);
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STATRD = !IOWR # IORD # !A1 # A2 # !A10 # !A11;
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FF1 = !(FF2 & RESET);
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FF2 = !(FF1 & (IOWR # !IORD # A1 # !A2 # !A10 # !A11));
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ROMSEL = !(FF1 & A19);
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LOADSHIFT= !MEMRES;
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