mirror of
https://github.com/MiSTer-devel/ao486_MiSTer.git
synced 2026-04-19 03:05:39 +00:00
124 lines
5.0 KiB
VHDL
124 lines
5.0 KiB
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use STD.textio.all;
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entity cpu_export is
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port
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(
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clk : in std_logic;
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rst_n : in std_logic;
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new_export : in std_logic;
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commandcount : out integer;
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eax : std_logic_vector(31 downto 0);
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ebx : std_logic_vector(31 downto 0);
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ecx : std_logic_vector(31 downto 0);
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edx : std_logic_vector(31 downto 0);
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esp : std_logic_vector(31 downto 0);
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ebp : std_logic_vector(31 downto 0);
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esi : std_logic_vector(31 downto 0);
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edi : std_logic_vector(31 downto 0);
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eip : std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arch of cpu_export is
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signal new_export_1 : std_logic := '0';
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signal rst_n_1 : std_logic := '1';
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begin
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-- synthesis translate_off
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process
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file outfile : text;
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variable f_status : FILE_OPEN_STATUS;
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variable line_out : line;
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variable recordcount : integer := 0;
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constant filenamebase : string := "R:\debug_";
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variable filename : string(1 to 14);
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variable nh : std_logic := '1';
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variable tc : integer := 0;
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variable testrun : integer := 0;
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variable old_eax : std_logic_vector(31 downto 0) := (others => '0');
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variable old_ebx : std_logic_vector(31 downto 0) := (others => '0');
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variable old_ecx : std_logic_vector(31 downto 0) := (others => '0');
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variable old_edx : std_logic_vector(31 downto 0) := (others => '0');
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variable old_esp : std_logic_vector(31 downto 0) := (others => '0');
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variable old_ebp : std_logic_vector(31 downto 0) := (others => '0');
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variable old_esi : std_logic_vector(31 downto 0) := (others => '0');
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variable old_edi : std_logic_vector(31 downto 0) := (others => '0');
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variable old_eip : std_logic_vector(31 downto 0) := (others => '0');
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begin
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filename := filenamebase & to_hstring(to_unsigned(testrun, 4)) & ".txt";
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file_open(f_status, outfile, filename, write_mode);
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while (true) loop
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wait until rising_edge(clk);
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rst_n_1 <= rst_n;
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if (rst_n = '1' and rst_n_1 = '0') then
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nh := '1';
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tc := 0;
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testrun := testrun + 1;
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filename := filenamebase & to_hstring(to_unsigned(testrun, 4)) & ".txt";
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file_close(outfile);
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file_open(f_status, outfile, filename, write_mode);
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file_close(outfile);
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file_open(f_status, outfile, filename, append_mode);
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end if;
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new_export_1 <= new_export;
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if (new_export_1 = '1') then
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write(line_out, string'("#")); write(line_out, tc); writeline(outfile, line_out);
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-- cpu 7
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if (nh = '1' or eax /= old_eax) then write(line_out, string'("eax ")); write(line_out, to_hstring(signed(eax))); writeline(outfile, line_out); old_eax := eax; end if;
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if (nh = '1' or ebx /= old_ebx) then write(line_out, string'("ebx ")); write(line_out, to_hstring(signed(ebx))); writeline(outfile, line_out); old_ebx := ebx; end if;
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if (nh = '1' or ecx /= old_ecx) then write(line_out, string'("ecx ")); write(line_out, to_hstring(signed(ecx))); writeline(outfile, line_out); old_ecx := ecx; end if;
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if (nh = '1' or edx /= old_edx) then write(line_out, string'("edx ")); write(line_out, to_hstring(signed(edx))); writeline(outfile, line_out); old_edx := edx; end if;
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if (nh = '1' or esp /= old_esp) then write(line_out, string'("esp ")); write(line_out, to_hstring(signed(esp))); writeline(outfile, line_out); old_esp := esp; end if;
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if (nh = '1' or ebp /= old_ebp) then write(line_out, string'("ebp ")); write(line_out, to_hstring(signed(ebp))); writeline(outfile, line_out); old_ebp := ebp; end if;
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if (nh = '1' or esi /= old_esi) then write(line_out, string'("esi ")); write(line_out, to_hstring(signed(esi))); writeline(outfile, line_out); old_esi := esi; end if;
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if (nh = '1' or edi /= old_edi) then write(line_out, string'("edi ")); write(line_out, to_hstring(signed(edi))); writeline(outfile, line_out); old_edi := edi; end if;
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--if (nh = '1' or eip /= old_eip) then write(line_out, string'("eip ")); write(line_out, to_hstring(signed(eip))); writeline(outfile, line_out); old_eip := eip; end if;
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recordcount := recordcount + 1;
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tc := tc + 1;
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if (recordcount mod 1000 = 0) then
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file_close(outfile);
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file_open(f_status, outfile, filename, append_mode);
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recordcount := 0;
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end if;
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nh := '0';
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end if;
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commandcount <= tc;
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end loop;
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end process;
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-- synthesis translate_on
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end architecture;
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