ao486_MiSTer/sim/iverilog/memory/Makefile

mirror of https://github.com/MiSTer-devel/ao486_MiSTer.git synced 2026-04-26 03:05:54 +00:00
all:
	iverilog -y. -y./../../rtl/ -y./../../rtl/memory/ -y./../altera/ -y./../../rtl/altera/ -I./../../rtl/ -o tb_memory.vvp tb_memory.v
	`all:`
	`iverilog -y. -y./../../rtl/ -y./../../rtl/memory/ -y./../altera/ -y./../../rtl/altera/ -I./../../rtl/ -o tb_memory.vvp tb_memory.v`