mirror of
https://github.com/MiSTer-devel/ao486_MiSTer.git
synced 2026-04-19 03:05:39 +00:00
702 lines
20 KiB
Verilog
702 lines
20 KiB
Verilog
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module system
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(
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input clk_sys,
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input reset_cpu,
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input reset_sys,
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input [27:0] clock_rate,
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output [1:0] fdd0_request,
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output [2:0] hdd0_request,
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output [2:0] hdd1_request,
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input [13:0] joystick_dig_1,
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input [13:0] joystick_dig_2,
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input [15:0] joystick_ana_1,
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input [15:0] joystick_ana_2,
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input [1:0] joystick_mode,
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input joystick_clk_grav,
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input [15:0] mgmt_address,
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input mgmt_read,
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output [15:0] mgmt_readdata,
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input mgmt_write,
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input [15:0] mgmt_writedata,
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input mgmt_active,
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input ps2_kbclk_in,
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input ps2_kbdat_in,
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output ps2_kbclk_out,
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output ps2_kbdat_out,
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input ps2_mouseclk_in,
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input ps2_mousedat_in,
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output ps2_mouseclk_out,
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output ps2_mousedat_out,
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output ps2_reset_n,
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input memcfg,
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input clk_uart,
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input serial_rx,
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output serial_tx,
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input serial_cts_n,
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input serial_dcd_n,
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input serial_dsr_n,
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output serial_rts_n,
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output serial_dtr_n,
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input serial_midi_rate,
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input clk_opl,
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output [15:0] sound_sample_l,
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output [15:0] sound_sample_r,
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input sound_fm_mode,
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output speaker_out,
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input clk_vga,
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input [27:0] clock_rate_vga,
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output video_ce,
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output video_blank_n,
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output video_hsync,
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output video_vsync,
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output [7:0] video_r,
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output [7:0] video_g,
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output [7:0] video_b,
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input video_f60,
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output [7:0] video_pal_a,
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output [17:0] video_pal_d,
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output video_pal_we,
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output [19:0] video_start_addr,
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output [8:0] video_width,
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output [10:0] video_height,
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output [3:0] video_flags,
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output [8:0] video_stride,
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output video_off,
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input video_fb_en,
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [24:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE
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);
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wire a20_enable;
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wire [7:0] dma_floppy_readdata;
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wire dma_floppy_terminal;
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wire [7:0] dma_floppy_writedata;
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wire dma_floppy_req;
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wire dma_floppy_ack;
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wire dma_soundblaster_req;
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wire dma_soundblaster_terminal;
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wire [7:0] dma_soundblaster_readdata;
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wire [7:0] dma_soundblaster_writedata;
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wire dma_soundblaster_ack;
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wire [7:0] dma_readdata;
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wire dma_waitrequest;
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wire [23:0] dma_address;
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wire dma_read;
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wire dma_readdatavalid;
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wire dma_write;
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wire [7:0] dma_writedata;
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wire [31:0] mgmt_fdd0_readdata;
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wire [31:0] mgmt_hdd0_readdata;
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wire [31:0] mgmt_hdd1_readdata;
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wire [31:0] mgmt_ctl_writedata;
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wire [7:0] mgmt_ctl_address;
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wire mgmt_ctl_read;
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wire mgmt_ctl_write;
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reg mgmt_hdd0_cs;
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reg mgmt_hdd1_cs;
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reg mgmt_fdd0_cs;
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reg mgmt_rtc_cs;
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wire interrupt_done;
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wire interrupt_do;
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wire [7:0] interrupt_vector;
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reg [15:0] interrupt;
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wire irq_0, irq_1, irq_2, irq_4, irq_5, irq_6, irq_8, irq_9, irq_12, irq_14, irq_15;
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wire cpu_io_read_do;
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wire [15:0] cpu_io_read_address;
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wire [2:0] cpu_io_read_length;
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wire [31:0] cpu_io_read_data;
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wire cpu_io_read_done;
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wire cpu_io_write_do;
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wire [15:0] cpu_io_write_address;
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wire [2:0] cpu_io_write_length;
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wire [31:0] cpu_io_write_data;
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wire cpu_io_write_done;
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wire [15:0] iobus_address;
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wire iobus_write;
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wire iobus_read;
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wire [2:0] iobus_datasize;
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wire [31:0] iobus_writedata;
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reg hdd0_cs;
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reg hdd1_cs;
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reg floppy0_cs;
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reg dma_master_cs;
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reg dma_page_cs;
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reg dma_slave_cs;
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reg pic_master_cs;
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reg pic_slave_cs;
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reg pit_cs;
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reg ps2_io_cs;
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reg ps2_ctl_cs;
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reg joy_cs;
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reg rtc_cs;
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reg fm_cs;
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reg sb_cs;
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reg uart_cs;
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reg mpu_cs;
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reg vga_b_cs;
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reg vga_c_cs;
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reg vga_d_cs;
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wire [7:0] sound_readdata;
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wire [7:0] floppy0_readdata;
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wire [31:0] hdd0_readdata;
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wire [31:0] hdd1_readdata;
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wire [7:0] joystick_readdata;
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wire [7:0] pit_readdata;
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wire [7:0] ps2_readdata;
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wire [7:0] rtc_readdata;
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wire [7:0] uart_readdata;
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wire [7:0] dma_io_readdata;
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wire [7:0] pic_readdata;
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wire [7:0] vga_io_readdata;
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wire [29:0] mem_address;
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wire [31:0] mem_writedata;
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wire [31:0] mem_readdata;
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wire [3:0] mem_byteenable;
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wire [3:0] mem_burstcount;
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wire mem_write;
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wire mem_read;
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wire mem_waitrequest;
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wire mem_readdatavalid;
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wire [16:0] vga_address;
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wire [7:0] vga_readdata;
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wire [7:0] vga_writedata;
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wire vga_read;
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wire vga_write;
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wire [2:0] vga_memmode;
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wire [5:0] video_wr_seg;
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wire [5:0] video_rd_seg;
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assign DDRAM_CLK = clk_sys;
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l2_cache cache
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(
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.CLK (clk_sys),
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.RESET (reset_cpu),
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.CPU_ADDR (mem_address),
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.CPU_DIN (mem_writedata),
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.CPU_DOUT (mem_readdata),
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.CPU_DOUT_READY (mem_readdatavalid),
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.CPU_BE (mem_byteenable),
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.CPU_BURSTCNT (mem_burstcount),
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.CPU_BUSY (mem_waitrequest),
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.CPU_RD (mem_read),
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.CPU_WE (mem_write),
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.DDRAM_ADDR (DDRAM_ADDR),
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.DDRAM_DIN (DDRAM_DIN),
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.DDRAM_DOUT (DDRAM_DOUT),
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.DDRAM_DOUT_READY (DDRAM_DOUT_READY),
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.DDRAM_BE (DDRAM_BE),
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.DDRAM_BURSTCNT (DDRAM_BURSTCNT),
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.DDRAM_BUSY (DDRAM_BUSY),
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.DDRAM_RD (DDRAM_RD),
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.DDRAM_WE (DDRAM_WE),
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.VGA_ADDR (vga_address),
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.VGA_DIN (vga_readdata),
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.VGA_DOUT (vga_writedata),
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.VGA_RD (vga_read),
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.VGA_WE (vga_write),
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.VGA_MODE (vga_memmode),
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.VGA_WR_SEG (video_wr_seg),
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.VGA_RD_SEG (video_rd_seg),
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.VGA_FB_EN (video_fb_en)
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);
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ao486 ao486
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(
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.clk (clk_sys),
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.rst_n (~reset_cpu),
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.avm_address (mem_address),
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.avm_writedata (mem_writedata),
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.avm_byteenable (mem_byteenable),
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.avm_burstcount (mem_burstcount),
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.avm_write (mem_write),
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.avm_read (mem_read),
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.avm_waitrequest (mem_waitrequest),
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.avm_readdatavalid (mem_readdatavalid),
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.avm_readdata (mem_readdata),
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.interrupt_do (interrupt_do),
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.interrupt_vector (interrupt_vector),
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.interrupt_done (interrupt_done),
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.io_read_do (cpu_io_read_do),
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.io_read_address (cpu_io_read_address),
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.io_read_length (cpu_io_read_length),
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.io_read_data (cpu_io_read_data),
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.io_read_done (cpu_io_read_done),
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.io_write_do (cpu_io_write_do),
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.io_write_address (cpu_io_write_address),
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.io_write_length (cpu_io_write_length),
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.io_write_data (cpu_io_write_data),
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.io_write_done (cpu_io_write_done),
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.a20_enable (a20_enable),
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.dma_address (dma_address),
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.dma_read (dma_read),
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.dma_readdata (dma_readdata),
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.dma_readdatavalid (dma_readdatavalid),
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.dma_waitrequest (dma_waitrequest),
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.dma_write (dma_write),
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.dma_writedata (dma_writedata)
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);
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always @(posedge clk_sys) begin
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hdd0_cs <= ({iobus_address[15:3], 3'd0} == 16'h01F0) || (iobus_address == 16'h03F6);
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hdd1_cs <= ({iobus_address[15:3], 3'd0} == 16'h0170) || (iobus_address == 16'h0376);
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joy_cs <= ({iobus_address[15:0] } == 16'h0201);
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floppy0_cs <= ({iobus_address[15:3], 3'd0} == 16'h03F0);
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dma_master_cs <= ({iobus_address[15:5], 5'd0} == 16'h00C0);
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dma_page_cs <= ({iobus_address[15:4], 4'd0} == 16'h0080);
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dma_slave_cs <= ({iobus_address[15:4], 4'd0} == 16'h0000);
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pic_master_cs <= ({iobus_address[15:1], 1'd0} == 16'h0020);
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pic_slave_cs <= ({iobus_address[15:1], 1'd0} == 16'h00A0);
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pit_cs <= ({iobus_address[15:2], 2'd0} == 16'h0040) || (iobus_address == 16'h0061);
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ps2_io_cs <= ({iobus_address[15:3], 3'd0} == 16'h0060);
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ps2_ctl_cs <= ({iobus_address[15:4], 4'd0} == 16'h0090);
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rtc_cs <= ({iobus_address[15:1], 1'd0} == 16'h0070);
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fm_cs <= ({iobus_address[15:2], 2'd0} == 16'h0388);
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sb_cs <= ({iobus_address[15:4], 4'd0} == 16'h0220);
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uart_cs <= ({iobus_address[15:3], 3'd0} == 16'h03F8);
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mpu_cs <= ({iobus_address[15:1], 1'd0} == 16'h0330);
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vga_b_cs <= ({iobus_address[15:4], 4'd0} == 16'h03B0);
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vga_c_cs <= ({iobus_address[15:4], 4'd0} == 16'h03C0);
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vga_d_cs <= ({iobus_address[15:4], 4'd0} == 16'h03D0);
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end
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wire [7:0] iobus_readdata8 =
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( floppy0_cs ) ? floppy0_readdata :
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( dma_master_cs|dma_slave_cs|dma_page_cs ) ? dma_io_readdata :
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( pic_master_cs|pic_slave_cs ) ? pic_readdata :
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( pit_cs ) ? pit_readdata :
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( ps2_io_cs|ps2_ctl_cs ) ? ps2_readdata :
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( rtc_cs ) ? rtc_readdata :
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( sb_cs|fm_cs ) ? sound_readdata :
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( uart_cs|mpu_cs ) ? uart_readdata :
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( vga_b_cs|vga_c_cs|vga_d_cs ) ? vga_io_readdata :
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( joy_cs ) ? joystick_readdata :
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8'hFF;
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iobus iobus
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(
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.clk (clk_sys),
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.reset (reset_sys),
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.cpu_read_do (cpu_io_read_do),
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.cpu_read_address (cpu_io_read_address),
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.cpu_read_length (cpu_io_read_length),
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.cpu_read_data (cpu_io_read_data),
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.cpu_read_done (cpu_io_read_done),
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.cpu_write_do (cpu_io_write_do),
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.cpu_write_address (cpu_io_write_address),
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.cpu_write_length (cpu_io_write_length),
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.cpu_write_data (cpu_io_write_data),
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.cpu_write_done (cpu_io_write_done),
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.bus_address (iobus_address),
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.bus_write (iobus_write),
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.bus_read (iobus_read),
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.bus_io32 ((hdd0_cs | hdd1_cs) & ~iobus_address[9]),
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.bus_datasize (iobus_datasize),
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.bus_writedata (iobus_writedata),
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.bus_readdata (hdd0_cs ? hdd0_readdata : hdd1_cs ? hdd1_readdata : iobus_readdata8)
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);
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dma dma
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(
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.clk (clk_sys),
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.rst_n (~reset_sys),
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.avm_address (dma_address),
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.avm_waitrequest (dma_waitrequest),
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.avm_read (dma_read),
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.avm_readdatavalid (dma_readdatavalid),
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.avm_readdata (dma_readdata),
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.avm_write (dma_write),
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.avm_writedata (dma_writedata),
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.io_address (iobus_address[4:0]),
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.io_writedata (iobus_writedata[7:0]),
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.io_read (iobus_read),
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.io_write (iobus_write),
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.io_readdata (dma_io_readdata),
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.io_master_cs (dma_master_cs),
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.io_slave_cs (dma_slave_cs),
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.io_page_cs (dma_page_cs),
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.dma_floppy_req (dma_floppy_req),
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.dma_floppy_ack (dma_floppy_ack),
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.dma_floppy_terminal (dma_floppy_terminal),
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.dma_floppy_readdata (dma_floppy_readdata),
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.dma_floppy_writedata (dma_floppy_writedata),
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.dma_soundblaster_req (dma_soundblaster_req),
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.dma_soundblaster_ack (dma_soundblaster_ack),
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.dma_soundblaster_terminal (dma_soundblaster_terminal),
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.dma_soundblaster_readdata (dma_soundblaster_readdata),
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.dma_soundblaster_writedata (dma_soundblaster_writedata)
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);
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floppy floppy0
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(
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.clk (clk_sys),
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.rst_n (~reset_sys),
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.clock_rate (clock_rate),
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.io_address (iobus_address[2:0]),
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.io_writedata (iobus_writedata[7:0]),
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.io_read (iobus_read & floppy0_cs),
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.io_write (iobus_write & floppy0_cs),
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.io_readdata (floppy0_readdata),
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.dma_req (dma_floppy_req),
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.dma_ack (dma_floppy_ack),
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.dma_terminal (dma_floppy_terminal),
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.dma_readdata (dma_floppy_readdata),
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.dma_writedata (dma_floppy_writedata),
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.mgmt_address (mgmt_ctl_address[3:0]),
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.mgmt_write (mgmt_ctl_write & mgmt_fdd0_cs),
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.mgmt_writedata (mgmt_ctl_writedata),
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.mgmt_read (mgmt_ctl_read & mgmt_fdd0_cs),
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.mgmt_readdata (mgmt_fdd0_readdata),
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.request (fdd0_request),
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.irq (irq_6)
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);
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hdd hdd0
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(
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.clk (clk_sys),
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.rst_n (~reset_sys),
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.io_address ({iobus_address[9],iobus_address[2:0]}),
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.io_writedata (iobus_writedata),
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.io_data_size (iobus_datasize),
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.io_read (iobus_read & hdd0_cs),
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.io_write (iobus_write & hdd0_cs),
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.io_readdata (hdd0_readdata),
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.mgmt_address (mgmt_ctl_address[3:0]),
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.mgmt_write (mgmt_ctl_write & mgmt_hdd0_cs),
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.mgmt_writedata (mgmt_ctl_writedata),
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.mgmt_read (mgmt_ctl_read & mgmt_hdd0_cs),
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.mgmt_readdata (mgmt_hdd0_readdata),
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.request (hdd0_request),
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.irq (irq_14)
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);
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hdd hdd1
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(
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.clk (clk_sys),
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.rst_n (~reset_sys),
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.io_address ({iobus_address[9],iobus_address[2:0]}),
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.io_writedata (iobus_writedata),
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.io_data_size (iobus_datasize),
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.io_read (iobus_read & hdd1_cs),
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.io_write (iobus_write & hdd1_cs),
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.io_readdata (hdd1_readdata),
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.mgmt_address (mgmt_ctl_address[3:0]),
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.mgmt_write (mgmt_ctl_write & mgmt_hdd1_cs),
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.mgmt_writedata (mgmt_ctl_writedata),
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.mgmt_read (mgmt_ctl_read & mgmt_hdd1_cs),
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.mgmt_readdata (mgmt_hdd1_readdata),
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.request (hdd1_request),
|
|
.irq (irq_15)
|
|
);
|
|
|
|
joystick joystick
|
|
(
|
|
.clk (clk_sys),
|
|
.rst_n (~reset_sys),
|
|
|
|
.clk_grav (joystick_clk_grav),
|
|
|
|
.write (iobus_write & joy_cs),
|
|
.readdata (joystick_readdata),
|
|
|
|
.dig_1 (joystick_dig_1),
|
|
.dig_2 (joystick_dig_2),
|
|
.ana_1 (joystick_ana_1),
|
|
.ana_2 (joystick_ana_2),
|
|
.mode (joystick_mode)
|
|
);
|
|
|
|
pit pit
|
|
(
|
|
.clk (clk_sys),
|
|
.rst_n (~reset_sys),
|
|
|
|
.clock_rate (clock_rate),
|
|
|
|
.io_address ({iobus_address[5],iobus_address[1:0]}),
|
|
.io_writedata (iobus_writedata[7:0]),
|
|
.io_read (iobus_read & pit_cs),
|
|
.io_write (iobus_write & pit_cs),
|
|
.io_readdata (pit_readdata),
|
|
|
|
.speaker_out (speaker_out),
|
|
.irq (irq_0)
|
|
);
|
|
|
|
ps2 ps2
|
|
(
|
|
.clk (clk_sys),
|
|
.rst_n (~reset_sys),
|
|
|
|
.io_address (iobus_address[3:0]),
|
|
.io_writedata (iobus_writedata[7:0]),
|
|
.io_read (iobus_read),
|
|
.io_write (iobus_write),
|
|
.io_readdata (ps2_readdata),
|
|
.io_cs (ps2_io_cs),
|
|
.ctl_cs (ps2_ctl_cs),
|
|
|
|
.ps2_kbclk (ps2_kbclk_in),
|
|
.ps2_kbdat (ps2_kbdat_in),
|
|
.ps2_kbclk_out (ps2_kbclk_out),
|
|
.ps2_kbdat_out (ps2_kbdat_out),
|
|
|
|
.ps2_mouseclk (ps2_mouseclk_in),
|
|
.ps2_mousedat (ps2_mousedat_in),
|
|
.ps2_mouseclk_out (ps2_mouseclk_out),
|
|
.ps2_mousedat_out (ps2_mousedat_out),
|
|
|
|
.output_a20_enable (),
|
|
.output_reset_n (ps2_reset_n),
|
|
.a20_enable (a20_enable),
|
|
|
|
.irq_keyb (irq_1),
|
|
.irq_mouse (irq_12)
|
|
);
|
|
|
|
rtc rtc
|
|
(
|
|
.clk (clk_sys),
|
|
.rst_n (~reset_sys),
|
|
|
|
.clock_rate (clock_rate),
|
|
|
|
.io_address (iobus_address[0]),
|
|
.io_writedata (iobus_writedata[7:0]),
|
|
.io_read (iobus_read & rtc_cs),
|
|
.io_write (iobus_write & rtc_cs),
|
|
.io_readdata (rtc_readdata),
|
|
|
|
.mgmt_address (mgmt_ctl_address),
|
|
.mgmt_write (mgmt_ctl_write & mgmt_rtc_cs),
|
|
.mgmt_writedata (mgmt_ctl_writedata[7:0]),
|
|
|
|
.rtc_memcfg (memcfg),
|
|
|
|
.irq (irq_8)
|
|
);
|
|
|
|
sound sound
|
|
(
|
|
.clk (clk_sys),
|
|
.clk_opl (clk_opl),
|
|
.rst_n (~reset_sys),
|
|
|
|
.clock_rate (clock_rate),
|
|
|
|
.address (iobus_address[3:0]),
|
|
.writedata (iobus_writedata[7:0]),
|
|
.read (iobus_read),
|
|
.write (iobus_write),
|
|
.readdata (sound_readdata),
|
|
.sb_cs (sb_cs),
|
|
.fm_cs (fm_cs),
|
|
|
|
.dma_req (dma_soundblaster_req),
|
|
.dma_ack (dma_soundblaster_ack),
|
|
.dma_terminal (dma_soundblaster_terminal),
|
|
.dma_readdata (dma_soundblaster_readdata),
|
|
.dma_writedata (dma_soundblaster_writedata),
|
|
|
|
.sample_l (sound_sample_l),
|
|
.sample_r (sound_sample_r),
|
|
|
|
.fm_mode (sound_fm_mode),
|
|
|
|
.irq (irq_5)
|
|
);
|
|
|
|
uart uart
|
|
(
|
|
.clk (clk_sys),
|
|
.br_clk (clk_uart),
|
|
.reset (reset_sys|reset_cpu),
|
|
|
|
.address (iobus_address[2:0]),
|
|
.writedata (iobus_writedata[7:0]),
|
|
.read (iobus_read),
|
|
.write (iobus_write),
|
|
.readdata (uart_readdata),
|
|
.uart_cs (uart_cs),
|
|
.mpu_cs (mpu_cs),
|
|
|
|
.rx (serial_rx),
|
|
.tx (serial_tx),
|
|
.cts_n (serial_cts_n),
|
|
.dcd_n (serial_dcd_n),
|
|
.dsr_n (serial_dsr_n),
|
|
.rts_n (serial_rts_n),
|
|
.dtr_n (serial_dtr_n),
|
|
.br_out (),
|
|
.ri_n (1),
|
|
|
|
.midi_rate (serial_midi_rate),
|
|
|
|
.irq_uart (irq_4),
|
|
.irq_mpu (irq_9)
|
|
);
|
|
|
|
vga vga
|
|
(
|
|
.clk_sys (clk_sys),
|
|
.rst_n (~reset_sys),
|
|
|
|
.clk_vga (clk_vga),
|
|
.clock_rate_vga (clock_rate_vga),
|
|
|
|
.io_address (iobus_address[3:0]),
|
|
.io_writedata (iobus_writedata[7:0]),
|
|
.io_read (iobus_read),
|
|
.io_write (iobus_write),
|
|
.io_readdata (vga_io_readdata),
|
|
.io_b_cs (vga_b_cs),
|
|
.io_c_cs (vga_c_cs),
|
|
.io_d_cs (vga_d_cs),
|
|
|
|
.mem_address (vga_address),
|
|
.mem_read (vga_read),
|
|
.mem_readdata (vga_readdata),
|
|
.mem_write (vga_write),
|
|
.mem_writedata (vga_writedata),
|
|
|
|
.vga_ce (video_ce),
|
|
.vga_blank_n (video_blank_n),
|
|
.vga_horiz_sync (video_hsync),
|
|
.vga_vert_sync (video_vsync),
|
|
.vga_r (video_r),
|
|
.vga_g (video_g),
|
|
.vga_b (video_b),
|
|
.vga_f60 (video_f60),
|
|
.vga_memmode (vga_memmode),
|
|
.vga_pal_a (video_pal_a),
|
|
.vga_pal_d (video_pal_d),
|
|
.vga_pal_we (video_pal_we),
|
|
.vga_start_addr (video_start_addr),
|
|
.vga_wr_seg (video_wr_seg),
|
|
.vga_rd_seg (video_rd_seg),
|
|
.vga_width (video_width),
|
|
.vga_height (video_height),
|
|
.vga_flags (video_flags),
|
|
.vga_stride (video_stride),
|
|
.vga_off (video_off),
|
|
|
|
.irq (irq_2)
|
|
);
|
|
|
|
pic pic
|
|
(
|
|
.clk (clk_sys),
|
|
.rst_n (~reset_sys),
|
|
|
|
.io_address (iobus_address[0]),
|
|
.io_writedata (iobus_writedata[7:0]),
|
|
.io_read (iobus_read),
|
|
.io_write (iobus_write),
|
|
.io_readdata (pic_readdata),
|
|
.io_master_cs (pic_master_cs),
|
|
.io_slave_cs (pic_slave_cs),
|
|
|
|
.interrupt_vector (interrupt_vector),
|
|
.interrupt_done (interrupt_done),
|
|
.interrupt_do (interrupt_do),
|
|
.interrupt_input (interrupt)
|
|
);
|
|
|
|
always @* begin
|
|
interrupt = 0;
|
|
|
|
interrupt[0] = irq_0;
|
|
interrupt[1] = irq_1;
|
|
interrupt[2] = irq_2;
|
|
interrupt[4] = irq_4;
|
|
interrupt[5] = irq_5;
|
|
interrupt[6] = irq_6;
|
|
interrupt[8] = irq_8;
|
|
interrupt[9] = irq_9;
|
|
interrupt[12] = irq_12;
|
|
interrupt[14] = irq_14;
|
|
interrupt[15] = irq_15;
|
|
end
|
|
|
|
always @(posedge clk_sys) begin
|
|
mgmt_hdd0_cs <= (mgmt_address[15:8] == 8'hF0);
|
|
mgmt_hdd1_cs <= (mgmt_address[15:8] == 8'hF1);
|
|
mgmt_fdd0_cs <= (mgmt_address[15:8] == 8'hF2);
|
|
mgmt_rtc_cs <= (mgmt_address[15:8] == 8'hF4);
|
|
end
|
|
|
|
mgmt mgmt
|
|
(
|
|
.clk (clk_sys),
|
|
|
|
.in_address (mgmt_address),
|
|
.in_read (mgmt_read),
|
|
.in_readdata (mgmt_readdata),
|
|
.in_write (mgmt_write),
|
|
.in_writedata (mgmt_writedata),
|
|
.in_active (mgmt_active),
|
|
|
|
.out_address (mgmt_ctl_address),
|
|
.out_read (mgmt_ctl_read),
|
|
.out_write (mgmt_ctl_write),
|
|
.out_writedata (mgmt_ctl_writedata),
|
|
.out_readdata (mgmt_hdd0_cs ? mgmt_hdd0_readdata : mgmt_hdd1_cs ? mgmt_hdd1_readdata : mgmt_fdd0_readdata)
|
|
);
|
|
|
|
endmodule
|