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109 lines
2.4 KiB
Verilog
109 lines
2.4 KiB
Verilog
// uart.v
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// This file was auto-generated as a prototype implementation of a module
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// created in component editor. It ties off all outputs to ground and
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// ignores all inputs. It needs to be edited to make it do something
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// useful.
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//
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// This file will not be automatically regenerated. You should check it in
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// to your version control system if you want to keep it.
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`timescale 1 ps / 1 ps
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module uart (
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input clk,
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input reset,
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input [2:0] address,
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input write,
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input [7:0] writedata,
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input read,
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output reg [7:0] readdata,
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input uart_cs,
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input mpu_cs,
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input br_clk,
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input rx,
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output tx,
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input cts_n,
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input dcd_n,
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input dsr_n,
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input ri_n,
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output rts_n,
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output br_out,
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output dtr_n,
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input midi_rate,
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output irq_uart,
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output irq_mpu
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);
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assign irq_uart = ~mpu_mode_r & irq;
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assign irq_mpu = read_ack | (mpu_mode_r & ~rx_empty);
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wire xCR_write = uart_cs && write && (address == 2 || address == 3);
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wire mpu_mode = mpu_mode_r & ~xCR_write;
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wire uart_strobe = mpu_mode ? (mpu_cs & ~address[0] & ((read & ~read_ack) | write)) : (uart_cs & (read | write));
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wire irq, rx_empty, tx_empty;
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wire [7:0] data;
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gh_uart_16550 uart_16550
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(
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.clk(clk),
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.BR_clk(br_clk),
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.rst(reset),
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.CS(uart_strobe),
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.WR(write),
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.ADD(address),
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.D(writedata),
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.RD(data),
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.B_CLK(br_out),
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.sRX(rx),
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.CTSn(cts_n),
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.DSRn(dsr_n),
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.RIn(ri_n),
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.DCDn(dcd_n),
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.sTX(tx),
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.DTRn(dtr_n),
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.RTSn(rts_n),
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.IRQ(irq),
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.DIV2(midi_rate),
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.MPU_MODE(mpu_mode),
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.TX_Empty(tx_empty),
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.RX_Empty(rx_empty)
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);
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reg read_ack;
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reg mpu_mode_r;
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reg mpu_dumb;
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always @(posedge clk) begin
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if(reset) begin
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mpu_mode_r <= 0;
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read_ack <= 0;
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mpu_dumb <= 0;
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end
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else begin
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if(read & uart_cs) readdata <= data;
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if(read & mpu_cs) readdata <= address[0] ? {~(read_ack | ~rx_empty), ~tx_empty, 6'd0} : read_ack ? 8'hFE : data;
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if(write & mpu_cs & address[0]) begin
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mpu_mode_r <= 1;
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read_ack <= ~mpu_dumb;
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if(writedata == 8'hFF) mpu_dumb <= 0;
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if(writedata == 8'h3F) mpu_dumb <= 1;
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end
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if(mpu_cs & read & ~address[0]) read_ack <= 0;
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// write to FCR or LCR to switch MPU off
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if(xCR_write) {mpu_mode_r, mpu_dumb} <= 0;
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end
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end
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endmodule
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