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46 lines
1.1 KiB
VHDL
46 lines
1.1 KiB
VHDL
-----------------------------------------------------------------------------
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-- Filename: gh_gray2binary.vhd
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--
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-- Description:
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-- a gray code to binary converter
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--
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-- Copyright (c) 2006 by George Huber
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-- an OpenCores.org Project
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-- free to use, but see documentation for conditions
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--
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-- Revision History:
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-- Revision Date Author Comment
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-- -------- ---------- -------- -----------
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-- 1.0 12/26/06 G Huber Initial revision
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--
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-----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY gh_gray2binary IS
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GENERIC (size: INTEGER := 8);
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PORT(
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G : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); -- gray code in
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B : out STD_LOGIC_VECTOR(size-1 DOWNTO 0) -- binary value out
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);
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END entity;
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ARCHITECTURE a OF gh_gray2binary IS
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signal iB : STD_LOGIC_VECTOR(size-1 DOWNTO 0);
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BEGIN
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B <= iB;
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process (G,iB) is
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begin
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for j in 0 to size-2 loop
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iB(j) <= G(j) xor iB(j+1);
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end loop;
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iB(size-1) <= G(size-1);
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end process;
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END a;
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