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8 lines
624 B
Plaintext
8 lines
624 B
Plaintext
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) bram.vhd ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) simple_fifo.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) simple_fifo_mlab.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) simple_mult.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) simple_ram.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) simple_rom.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) simple_single_rom.v ]
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