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56 lines
1.5 KiB
VHDL
56 lines
1.5 KiB
VHDL
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-- Async Input Synchronization
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-- Copyright 2020 Alvin Albrecht
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--
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-- This file is part of the ZX Spectrum Next Project
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-- <https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/tree/master/cores>
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--
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-- The ZX Spectrum Next FPGA source code is free software: you can
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-- redistribute it and/or modify it under the terms of the GNU General
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-- Public License as published by the Free Software Foundation, either
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-- version 3 of the License, or (at your option) any later version.
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--
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-- The ZX Spectrum Next FPGA source code is distributed in the hope
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-- that it will be useful, but WITHOUT ANY WARRANTY; without even the
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-- implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with the ZX Spectrum Next FPGA source code. If not, see
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-- <https://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity synchronize is
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port
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(
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i_CLK : in std_logic;
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i_signal : in std_logic;
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o_signal : out std_logic
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);
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end entity;
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architecture rtl of synchronize is
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signal sig : std_logic;
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begin
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process (i_CLK)
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begin
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if falling_edge(i_CLK) then
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sig <= i_signal;
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end if;
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end process;
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process (i_CLK)
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begin
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if rising_edge(i_CLK) then
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o_signal <= sig;
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end if;
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end process;
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end architecture;
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