mirror of
https://github.com/MiSTer-devel/ZXNext_MISTer.git
synced 2026-04-19 03:05:38 +00:00
24 lines
1.4 KiB
Tcl
24 lines
1.4 KiB
Tcl
derive_pll_clocks
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derive_clock_uncertainty
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create_generated_clock -source [get_pins {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-name CLK_i0 -divide_by 2 -duty_cycle 50 [get_nets {emu|zxnext_top|CLK_i0}]
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create_generated_clock -source [get_pins {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-name CLK_CPU -divide_by 1 -duty_cycle 50 [get_nets {emu|zxnext_top|CLK_CPU}]
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set clk_sys {*|pll|pll_inst|altera_pll_i|*[0].*|divclk}
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set clk_56m {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}
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set clk_14m {*|pll|pll_inst|altera_pll_i|*[2].*|divclk}
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set clk_7m {*|pll|pll_inst|altera_pll_i|*[3].*|divclk}
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set clk_mem {*|pll|pll_inst|altera_pll_i|*[4].*|divclk}
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set_multicycle_path -from [get_clocks $clk_sys] -to [get_clocks $clk_7m] -start -setup 2
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set_multicycle_path -from [get_clocks $clk_sys] -to [get_clocks $clk_7m] -start -hold 1
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set_multicycle_path -from [get_clocks $clk_56m] -to [get_clocks CLK_CPU] -start -setup 2
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set_multicycle_path -from [get_clocks $clk_56m] -to [get_clocks CLK_CPU] -start -hold 1
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set_multicycle_path -from [get_clocks $clk_mem] -to [get_clocks CLK_CPU] -start -setup 2
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set_multicycle_path -from [get_clocks $clk_mem] -to [get_clocks CLK_CPU] -start -hold 1
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set_multicycle_path -from [get_clocks CLK_CPU] -to [get_clocks $clk_mem] -setup 2
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set_multicycle_path -from [get_clocks CLK_CPU] -to [get_clocks $clk_mem] -hold 1
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