From fe7946b23c5355407fcd64faafeec4e2ebacf142 Mon Sep 17 00:00:00 2001 From: sorgelig Date: Fri, 2 Apr 2021 01:40:14 +0800 Subject: [PATCH] Update sys. --- ZX-Spectrum.sv | 11 +-- sys/hps_io.v | 37 +++---- sys/sd_card.sv | 253 ++++++++++++++++++++++++++---------------------- sys/sys_top.sdc | 2 + sys/sys_top.v | 186 +++++++++++++++-------------------- 5 files changed, 235 insertions(+), 254 deletions(-) diff --git a/ZX-Spectrum.sv b/ZX-Spectrum.sv index 1095ac5..c3ac0e9 100644 --- a/ZX-Spectrum.sv +++ b/ZX-Spectrum.sv @@ -55,7 +55,7 @@ module emu input [11:0] HDMI_WIDTH, input [11:0] HDMI_HEIGHT, -`ifdef USE_FB +`ifdef MISTER_FB // Use framebuffer in DDRAM (USE_FB=1 in qsf) // FB_FORMAT: // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp @@ -73,6 +73,7 @@ module emu input FB_LL, output FB_FORCE_BLANK, +`ifdef MISTER_FB_PALETTE // Palette control for 8bit modes. // Ignored for other video modes. output FB_PAL_CLK, @@ -80,6 +81,7 @@ module emu output [23:0] FB_PAL_DOUT, input [23:0] FB_PAL_DIN, output FB_PAL_WR, +`endif `endif output LED_USER, // 1 - ON, 0 - OFF. @@ -111,7 +113,6 @@ module emu output SD_CS, input SD_CD, -`ifdef USE_DDRAM //High latency DDR3 RAM interface //Use for non-critical time purposes output DDRAM_CLK, @@ -124,9 +125,7 @@ module emu output [63:0] DDRAM_DIN, output [7:0] DDRAM_BE, output DDRAM_WE, -`endif -`ifdef USE_SDRAM //SDRAM interface with lower latency output SDRAM_CLK, output SDRAM_CKE, @@ -139,10 +138,10 @@ module emu output SDRAM_nCAS, output SDRAM_nRAS, output SDRAM_nWE, -`endif -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM //Secondary SDRAM + //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 input SDRAM2_EN, output SDRAM2_CLK, output [12:0] SDRAM2_A, diff --git a/sys/hps_io.v b/sys/hps_io.v index 9431c95..f784a8a 100644 --- a/sys/hps_io.v +++ b/sys/hps_io.v @@ -87,14 +87,9 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) // SD block level access input [31:0] sd_lba, - input [VD:0] sd_rd, // only single sd_rd can be active at any given time - input [VD:0] sd_wr, // only single sd_wr can be active at any given time - output reg sd_ack, - - // do not use in new projects. - // CID and CSD are fake except CSD image size field. - input sd_conf, - output reg sd_ack_conf, + input [VD:0] sd_rd, + input [VD:0] sd_wr, + output reg [VD:0] sd_ack, // SD byte level access. Signals for 2-PORT altsyncram. output reg [AW:0] sd_buff_addr, @@ -161,7 +156,7 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) assign EXT_BUS[31:16] = HPS_BUS[31:16]; assign EXT_BUS[35:33] = HPS_BUS[35:33]; -localparam MAX_W = $clog2((512 > (STRLEN+1)) ? 512 : (STRLEN+1))-1; +localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1; localparam DW = (WIDE) ? 15 : 7; localparam AW = (WIDE) ? 7 : 8; @@ -199,7 +194,7 @@ wire [15:0] sd_cmd = (VDNUM>=3) ? sd_rd[2] : 1'b0, (VDNUM>=2) ? sd_rd[1] : 1'b0, - 4'h5, sd_conf, 1'b1, + 4'h5, 1'b0, 1'b0, sd_wr[0], sd_rd[0] }; @@ -237,6 +232,7 @@ wire pressed = (ps2_key_raw[15:8] != 8'hf0); wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); reg [MAX_W:0] byte_cnt; +wire [7:0] disk = 4'd1 << (io_din[10:8]-1'd1); always@(posedge clk_sys) begin : uio_block reg [15:0] cmd; @@ -282,7 +278,6 @@ always@(posedge clk_sys) begin : uio_block cmd <= 0; byte_cnt <= 0; sd_ack <= 0; - sd_ack_conf <= 0; io_dout <= 0; ps2skip <= 0; img_mounted <= 0; @@ -295,10 +290,9 @@ always@(posedge clk_sys) begin : uio_block if(byte_cnt == 0) begin cmd <= io_din; - case(io_din) - 'h19: sd_ack_conf <= 1; - 'h17, - 'h18: sd_ack <= 1; + casex(io_din) + 'hX17, + 'hX18: sd_ack <= VD ? disk[VD:0] : 1'd1; 'h29: io_dout <= {4'hA, stflg}; 'h2B: io_dout <= 1; 'h2F: io_dout <= 1; @@ -311,7 +305,7 @@ always@(posedge clk_sys) begin : uio_block if(io_din == 5) ps2_key_raw <= 0; end else begin - case(cmd) + casex(cmd) // buttons and switches 'h01: cfg <= io_din; 'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din; @@ -353,7 +347,7 @@ always@(posedge clk_sys) begin : uio_block end // reading config string, returning a byte from string - 'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8]; + 'h14: if(byte_cnt <= STRLEN) io_dout[7:0] <= conf_str[{(STRLEN - byte_cnt),3'b000} +:8]; // reading sd card status 'h16: if(!byte_cnt[MAX_W:3]) begin @@ -365,20 +359,15 @@ always@(posedge clk_sys) begin : uio_block endcase end - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 'h19, // send sector IO -> FPGA // flag that download begins - 'h17: begin + 'hX17: begin sd_buff_dout <= io_din[DW:0]; b_wr <= 1; end // reading sd card write data - 'h18: begin + 'hX18: begin if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; io_dout <= sd_buff_din; end diff --git a/sys/sd_card.sv b/sys/sd_card.sv index a2aad7e..57d3c7c 100644 --- a/sys/sd_card.sv +++ b/sys/sd_card.sv @@ -27,37 +27,36 @@ module sd_card #(parameter WIDE = 0) ( - input clk_sys, - input reset, + input clk_sys, + input reset, - input sdhc, - - output [31:0] sd_lba, - output reg sd_rd, - output reg sd_wr, - input sd_ack, - input sd_ack_conf, + input sdhc, + input img_mounted, + input [63:0] img_size, - input [AW:0] sd_buff_addr, - input [DW:0] sd_buff_dout, - output [DW:0] sd_buff_din, - input sd_buff_wr, + output reg [31:0] sd_lba, + output reg sd_rd, + output reg sd_wr, + input sd_ack, + + input [AW:0] sd_buff_addr, + input [DW:0] sd_buff_dout, + output [DW:0] sd_buff_din, + input sd_buff_wr, // SPI interface - input clk_spi, + input clk_spi, - input ss, - input sck, - input mosi, - output reg miso + input ss, + input sck, + input mosi, + output reg miso ); localparam AW = WIDE ? 7 : 8; localparam DW = WIDE ? 15 : 7; -assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]}; - -wire[31:0] OCR = { 1'b1, sdhc, 30'd0 }; // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished +wire[31:0] OCR = { 1'b1, csd_sdhc, 30'd0 }; // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished wire [7:0] READ_DATA_TOKEN = 8'hfe; wire [7:0] WRITE_DATA_RESPONSE = 8'h05; @@ -78,40 +77,95 @@ localparam WR_STATE_RECV_CRC1 = 4; localparam WR_STATE_SEND_DRESP = 5; localparam WR_STATE_BUSY = 6; -sdbuf #(WIDE) buffer +localparam PREF_STATE_IDLE = 0; +localparam PREF_STATE_RD = 1; +localparam PREF_STATE_FINISH = 2; + +altsyncram sdbuf ( - .clock_a(clk_sys), - .address_a(sd_buff_addr), - .data_a(sd_buff_dout), - .wren_a(sd_ack & sd_buff_wr), - .q_a(sd_buff_din), + .clock0 (clk_sys), + .address_a ({sd_buf,sd_buff_addr}), + .data_a (sd_buff_dout), + .wren_a (sd_ack & sd_buff_wr), + .q_a (sd_buff_din), - .clock_b(clk_spi), - .address_b(buffer_ptr), - .data_b(buffer_din), - .wren_b(buffer_wr), - .q_b(buffer_dout) + .clock1 (clk_spi), + .address_b ({spi_buf,buffer_ptr}), + .data_b (buffer_din), + .wren_b (buffer_wr), + .q_b (buffer_dout), + + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .eccstatus(), + .rden_a(1'b1), + .rden_b(1'b1) ); +defparam + sdbuf.numwords_a = 1<<(AW+3), + sdbuf.widthad_a = AW+3, + sdbuf.width_a = DW+1, + sdbuf.numwords_b = 2048, + sdbuf.widthad_b = 11, + sdbuf.width_b = 8, + sdbuf.address_reg_b = "CLOCK1", + sdbuf.clock_enable_input_a = "BYPASS", + sdbuf.clock_enable_input_b = "BYPASS", + sdbuf.clock_enable_output_a = "BYPASS", + sdbuf.clock_enable_output_b = "BYPASS", + sdbuf.indata_reg_b = "CLOCK1", + sdbuf.intended_device_family = "Cyclone V", + sdbuf.lpm_type = "altsyncram", + sdbuf.operation_mode = "BIDIR_DUAL_PORT", + sdbuf.outdata_aclr_a = "NONE", + sdbuf.outdata_aclr_b = "NONE", + sdbuf.outdata_reg_a = "UNREGISTERED", + sdbuf.outdata_reg_b = "UNREGISTERED", + sdbuf.power_up_uninitialized = "FALSE", + sdbuf.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + sdbuf.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + sdbuf.width_byteena_a = 1, + sdbuf.width_byteena_b = 1, + sdbuf.wrcontrol_wraddress_reg_b = "CLOCK1"; -sdbuf #(WIDE) conf -( - .clock_a(clk_sys), - .address_a(sd_buff_addr), - .data_a(sd_buff_dout), - .wren_a(sd_ack_conf & sd_buff_wr), +reg [26:0] csd_size; +reg csd_sdhc; +always @(posedge clk_sys) begin + if (img_mounted) begin + csd_sdhc <= sdhc; + if (sdhc) begin + csd_size[0] <= 0; + csd_size[22:1] <= img_size[40:19]; // in 512K units + csd_size[26:23] <= 0; + end + else begin + csd_size[2:0] <= 7; // C_SIZE_MULT + csd_size[14:3] <= 12'b101101101101; + csd_size[26:15] <= img_size[29:18]; // in 256K units ((2**(C_SIZE_MULT+2))*512) + end + end +end - .clock_b(clk_spi), - .address_b(buffer_ptr), - .q_b(config_dout) -); +wire [127:0] CSD = {1'b0,csd_sdhc,6'h00,8'h0e,8'h00,8'h32,8'h5b,8'h59,6'h00,csd_size,7'h7f,8'h80,8'h0a,8'h40,8'h40,8'hf1}; +wire [127:0] CID = {8'hcd,8'hc7,8'h00,8'h93,8'h6f,8'h2f,8'h73,8'h00,8'h00,8'h44,8'h32,8'h38,8'h34,8'h00,8'h00,8'h3e}; -reg [31:0] lba, new_lba; +reg [31:0] new_lba; reg [8:0] buffer_ptr; reg [7:0] buffer_din; wire [7:0] buffer_dout; wire [7:0] config_dout; reg buffer_wr; +reg [1:0] sd_buf, spi_buf; + always @(posedge clk_spi) begin reg [2:0] read_state; reg [2:0] write_state; @@ -128,16 +182,40 @@ always @(posedge clk_spi) begin reg old_sck; reg synced; reg [5:0] ack; - reg io_ack; reg [4:0] idle_cnt = 0; reg [2:0] wait_m_cnt; + reg [1:0] pref_state; if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1; buffer_wr <= 0; ack <= {ack[4:0], sd_ack}; - if(ack[5:4] == 2'b10) io_ack <= 1; if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0; + if(ack[5:4] == 2'b10) begin + sd_buf <= sd_buf + 1'd1; + sd_lba <= sd_lba + 1; + end + + case(pref_state) + PREF_STATE_IDLE: + if(((sd_buf - spi_buf) < 2) && (read_state != RD_STATE_IDLE)) begin + sd_rd <= 1; + pref_state <= PREF_STATE_RD; + end + + PREF_STATE_RD: + if(read_state == RD_STATE_IDLE) begin + pref_state <= PREF_STATE_IDLE; + end + else if(ack[5:4] == 2'b10) begin + pref_state <= (cmd == 'h52) ? PREF_STATE_IDLE : PREF_STATE_FINISH; + end + + PREF_STATE_FINISH: + if(read_state == RD_STATE_IDLE) begin + pref_state <= PREF_STATE_IDLE; + end + endcase old_sck <= sck; @@ -152,8 +230,10 @@ always @(posedge clk_spi) begin sbuf <= 7'b1111111; tx_finish <= 0; rx_finish <= 0; + cmd <= 0; read_state <= RD_STATE_IDLE; write_state <= WR_STATE_IDLE; + pref_state <= PREF_STATE_IDLE; end if(old_sck & ~sck & ~ss) begin @@ -174,10 +254,10 @@ always @(posedge clk_spi) begin // CMD17/CMD18 if((cmd == 'h51) | (cmd == 'h52)) begin - io_ack <= 0; + spi_buf <= 0; + sd_buf <= 0; + sd_lba <= csd_sdhc ? new_lba : {9'd0, new_lba[31:9]}; read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller - lba <= new_lba; - sd_rd <= 1; // trigger request to io controller end end end @@ -197,7 +277,7 @@ always @(posedge clk_spi) begin // waiting for io controller to return data RD_STATE_WAIT_IO: begin - if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN; + if((sd_buf != spi_buf) & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN; end // send data token @@ -207,14 +287,13 @@ always @(posedge clk_spi) begin if(bit_cnt == 7) begin read_state <= RD_STATE_SEND_DATA; // next: send data buffer_ptr <= 0; - if(cmd == 'h49) buffer_ptr <= 16; end end // send data RD_STATE_SEND_DATA: begin - miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt]; + miso <= (cmd == 'h49) ? CSD[{buffer_ptr[3:0],~bit_cnt}] : (cmd == 'h4A) ? CID[{buffer_ptr[3:0],~bit_cnt}] : buffer_dout[~bit_cnt]; if(bit_cnt == 7) begin @@ -237,9 +316,7 @@ always @(posedge clk_spi) begin if(bit_cnt == 7) begin wait_m_cnt <= wait_m_cnt + 1'd1; if(&wait_m_cnt) begin - lba <= lba + 1; - io_ack <= 0; - sd_rd <= 1; + spi_buf <= spi_buf + 1'd1; read_state <= RD_STATE_WAIT_IO; end end @@ -368,6 +445,7 @@ always @(posedge clk_spi) begin // CMD18: READ_MULTIPLE 'h52: reply <= 0; // ok + // ACMD23: SET_WR_BLK_ERASE_COUNT 'h57: reply <= 0; //ok @@ -378,7 +456,9 @@ always @(posedge clk_spi) begin reply <= 0; // ok write_state <= WR_STATE_EXP_DTOKEN; // expect data token rx_finish <=0; - lba <= new_lba; + sd_lba <= csd_sdhc ? new_lba : {9'd0, new_lba[31:9]}; + spi_buf <= 0; + sd_buf <= 0; end // ACMD41: APP_SEND_OP_COND @@ -444,16 +524,16 @@ always @(posedge clk_spi) begin // send data response WR_STATE_SEND_DRESP: begin write_state <= WR_STATE_BUSY; - io_ack <= 0; + spi_buf <= spi_buf + 1'd1; sd_wr <= 1; end // wait for io controller to accept data WR_STATE_BUSY: - if(io_ack) begin + if(spi_buf == sd_buf) begin if(cmd == 'h59) begin write_state <= WR_STATE_EXP_DTOKEN; - lba <= lba + 1; + sd_lba <= sd_lba + 1; end else begin write_state <= WR_STATE_IDLE; @@ -478,60 +558,3 @@ always @(posedge clk_spi) begin end endmodule - -module sdbuf #(parameter WIDE) -( - input clock_a, - input [AW:0] address_a, - input [DW:0] data_a, - input wren_a, - output reg [DW:0] q_a, - - input clock_b, - input [8:0] address_b, - input [7:0] data_b, - input wren_b, - output reg [7:0] q_b -); - -localparam AW = WIDE ? 7 : 8; -localparam DW = WIDE ? 15 : 7; - -always@(posedge clock_a) begin - if(wren_a) begin - ram[address_a] <= data_a; - q_a <= data_a; - end - else begin - q_a <= ram[address_a]; - end -end - -generate - if(WIDE) begin - reg [1:0][7:0] ram[1<<8]; - always@(posedge clock_b) begin - if(wren_b) begin - ram[address_b[8:1]][address_b[0]] <= data_b; - q_b <= data_b; - end - else begin - q_b <= ram[address_b[8:1]][address_b[0]]; - end - end - end - else begin - reg [7:0] ram[1<<9]; - always@(posedge clock_b) begin - if(wren_b) begin - ram[address_b] <= data_b; - q_b <= data_b; - end - else begin - q_b <= ram[address_b]; - end - end - end -endgenerate - -endmodule diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 8187969..cf2d492 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -67,3 +67,5 @@ set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*} set_false_path -from {ascal|o_htotal* ascal|o_vtotal*} set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*} set_false_path -from {ascal|o_hsize* ascal|o_vsize*} + +set_false_path -from {mcp23009|sd_cd} diff --git a/sys/sys_top.v b/sys/sys_top.v index 8f0043c..3d45001 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -19,18 +19,6 @@ // //============================================================================ -`ifndef ARCADE_SYS - `define USE_DDRAM - `define USE_SDRAM -`endif - -`ifndef USE_DDRAM - `ifdef USE_FB - `define USE_DDRAM - `endif -`endif - - module sys_top ( /////////// CLOCK ////////// @@ -68,7 +56,7 @@ module sys_top output SDRAM_CLK, output SDRAM_CKE, -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM ////////// SDR #2 ////////// output [12:0] SDRAM2_A, inout [15:0] SDRAM2_DQ, @@ -139,20 +127,14 @@ module sys_top ////////////////////// Secondary SD /////////////////////////////////// wire SD_CS, SD_CLK, SD_MOSI; -`ifdef ARCADE_SYS - assign SD_CS = 1'bZ; - assign SD_CLK = 1'bZ; - assign SD_MOSI = 1'bZ; +`ifndef MISTER_DUAL_SDRAM + wire sd_miso = SW[3] | SDIO_DAT[0]; `else - `ifndef DUAL_SDRAM - wire sd_miso = SW[3] | SDIO_DAT[0]; - `else - wire sd_miso = 1; - `endif - wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO; + wire sd_miso = 1; `endif +wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO; -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM assign SDIO_DAT[2:1]= 2'bZZ; assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS; assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK; @@ -175,7 +157,7 @@ wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); wire led_u = ~led_user; wire led_locked; -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM assign LED_POWER = (SW[3] | led_p) ? 1'bZ : 1'b0; assign LED_HDD = (SW[3] | led_d) ? 1'bZ : 1'b0; assign LED_USER = (SW[3] | led_u) ? 1'bZ : 1'b0; @@ -185,7 +167,7 @@ wire led_locked; assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); wire btn_r, btn_o, btn_u; -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM assign {btn_r,btn_o,btn_u} = {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; `else assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; @@ -243,7 +225,7 @@ wire io_ss0 = gp_outr[18]; wire io_ss1 = gp_outr[19]; wire io_ss2 = gp_outr[20]; -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI wire io_osd_hdmi = io_ss1 & ~io_ss0; `endif @@ -268,7 +250,7 @@ always @(posedge clk_sys) begin gp_outd <= gp_out; end -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM wire [7:0] core_type = 'hA8; // generic core, dual SDRAM. `else wire [7:0] core_type = 'hA4; // generic core. @@ -290,7 +272,7 @@ reg cfg_set = 0; wire vga_fb = cfg[12] | vga_force_scaler; wire [1:0] hdmi_limited = {cfg[11],cfg[8]}; -`ifdef DEBUG_NOHDMI +`ifdef MISTER_DEBUG_NOHDMI wire direct_video = 1; `else wire direct_video = cfg[10]; @@ -301,7 +283,7 @@ wire audio_96k = cfg[6]; wire csync_en = cfg[3]; wire ypbpr_en = cfg[5]; wire io_osd_vga = io_ss1 & ~io_ss2; -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM wire sog = cfg[9]; wire vga_scaler = cfg[2] | vga_force_scaler; `endif @@ -399,7 +381,7 @@ always@(posedge clk_sys) begin 6: if(VS != io_din[11:0]) VS <= io_din[11:0]; 7: if(VBP != io_din[11:0]) VBP <= io_din[11:0]; endcase -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI if(cnt == 1) begin cfg_custom_p1 <= 0; cfg_custom_p2 <= 0; @@ -481,9 +463,7 @@ end cyclonev_hps_interface_peripheral_uart uart ( - .ri(0) -`ifndef ARCADE_SYS - , + .ri(0), .dsr(uart_dsr), .dcd(uart_dsr), .dtr(uart_dtr), @@ -492,7 +472,6 @@ cyclonev_hps_interface_peripheral_uart uart .rts(uart_rts), .rxd(uart_rxd), .txd(uart_txd) -`endif ); wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso; @@ -547,7 +526,6 @@ sysmem_lite sysmem //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. .reset_hps_cold_req(btn_r), -`ifdef USE_DDRAM //64-bit DDR3 RAM access .ram1_clk(ram_clk), .ram1_address(ram_address), @@ -559,7 +537,6 @@ sysmem_lite sysmem .ram1_writedata(ram_writedata), .ram1_byteenable(ram_byteenable), .ram1_write(ram_write), -`endif //64-bit DDR3 RAM access .ram2_clk(clk_audio), @@ -642,14 +619,18 @@ wire vbuf_write; wire [23:0] hdmi_data; wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl; -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI wire clk_hdmi = hdmi_clk_out; ascal #( .RAMBASE(32'h20000000), -`ifndef USE_FB +`ifndef MISTER_FB .PALETTE2("false"), +`else + `ifndef MISTER_FB_PALETTE + .PALETTE2("false"), + `endif `endif .N_DW(128), .N_AW(28) @@ -709,13 +690,15 @@ ascal .pal1_a (pal_a), .pal1_wr (pal_wr), -`ifdef USE_FB - .pal2_clk (fb_pal_clk), - .pal2_dw (fb_pal_d), - .pal2_dr (fb_pal_q), - .pal2_a (fb_pal_a), - .pal2_wr (fb_pal_wr), - .pal_n (fb_en), +`ifdef MISTER_FB + `ifdef MISTER_FB_PALETTE + .pal2_clk (fb_pal_clk), + .pal2_dw (fb_pal_d), + .pal2_dr (fb_pal_q), + .pal2_a (fb_pal_a), + .pal2_wr (fb_pal_wr), + .pal_n (fb_en), + `endif `endif .o_fb_ena (FB_EN), @@ -775,7 +758,7 @@ always @(posedge clk_sys) begin end end -`ifdef USE_FB +`ifdef MISTER_FB reg fb_vbl; always @(posedge clk_vid) fb_vbl <= hdmi_vbl; `endif @@ -899,7 +882,7 @@ always @(posedge clk_vid) begin vmax <= vmaxi; end -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI wire [15:0] lltune; pll_hdmi_adj pll_hdmi_adj ( @@ -942,7 +925,7 @@ end ///////////////////////// HDMI output ///////////////////////////////// -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI wire hdmi_clk_out; pll_hdmi pll_hdmi ( @@ -974,7 +957,7 @@ reg adj_write; reg [5:0] adj_address; reg [31:0] adj_data; -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI pll_cfg pll_cfg ( .mgmt_clk(FPGA_CLK1_50), @@ -1063,11 +1046,11 @@ cyclonev_hps_interface_peripheral_i2c hdmi_i2c .sda(HDMI_I2C_SDA) ); -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI wire [23:0] hdmi_data_sl; wire hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl; -`ifdef USE_FB +`ifdef MISTER_FB reg dis_output; always @(posedge clk_hdmi) begin reg dis; @@ -1115,10 +1098,6 @@ osd hdmi_osd .hs_out(hdmi_hs_osd), .vs_out(hdmi_vs_osd), .de_out(hdmi_de_osd) -`ifndef ARCADE_SYS - , - .osd_status(osd_status) -`endif ); `endif @@ -1167,7 +1146,7 @@ always @(posedge clk_vid) begin end wire hdmi_tx_clk; -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI cyclonev_clkselect hdmi_clk_sw ( .clkselect({1'b1, ~vga_fb & direct_video}), @@ -1257,6 +1236,7 @@ osd vga_osd .io_osd(io_osd_vga), .io_strobe(io_strobe), .io_din(io_din), + .osd_status(osd_status), .clk_video(clk_vid), .din(vga_data_sl), @@ -1272,7 +1252,7 @@ osd vga_osd wire vga_cs_osd; csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM wire [23:0] vgas_o; wire vgas_hs, vgas_vs, vgas_cs; vga_out vga_scaler_out @@ -1343,7 +1323,7 @@ end assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ; -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM wire analog_l, analog_r; assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif; @@ -1390,7 +1370,7 @@ audio_out audio_out .i2s_bclk(HDMI_SCLK), .i2s_lrclk(HDMI_LRCLK), .i2s_data(HDMI_I2S), -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM .dac_l(analog_l), .dac_r(analog_r), `endif @@ -1457,18 +1437,16 @@ wire hvs_fix, hhs_fix, hde_emu; wire clk_vid, ce_pix, clk_ihdmi, ce_hpix; wire vga_force_scaler; -`ifdef USE_DDRAM - wire ram_clk; - wire [28:0] ram_address; - wire [7:0] ram_burstcount; - wire ram_waitrequest; - wire [63:0] ram_readdata; - wire ram_readdatavalid; - wire ram_read; - wire [63:0] ram_writedata; - wire [7:0] ram_byteenable; - wire ram_write; -`endif +wire ram_clk; +wire [28:0] ram_address; +wire [7:0] ram_burstcount; +wire ram_waitrequest; +wire [63:0] ram_readdata; +wire ram_readdatavalid; +wire ram_read; +wire [63:0] ram_writedata; +wire [7:0] ram_byteenable; +wire ram_write; wire led_user; wire [1:0] led_power; @@ -1480,10 +1458,6 @@ sync_fix sync_h(clk_vid, hs_emu, hs_fix); wire [6:0] user_out, user_in; -`ifndef USE_SDRAM -assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = {39'bZ}; -`endif - assign clk_ihdmi= clk_vid; assign ce_hpix = ce_pix; assign hr_out = r_out; @@ -1493,19 +1467,14 @@ assign hhs_fix = hs_fix; assign hvs_fix = vs_fix; assign hde_emu = de_emu; -`ifdef ARCADE_SYS - assign audio_mix = 0; - assign {ADC_SCK, ADC_SDI, ADC_CONVST} = 0; - assign btn = 0; -`else - wire uart_dtr; - wire uart_dsr; - wire uart_cts; - wire uart_rts; - wire uart_rxd; - wire uart_txd; - wire osd_status; -`endif +wire uart_dtr; +wire uart_dsr; +wire uart_cts; +wire uart_rts; +wire uart_rxd; +wire uart_txd; + +wire osd_status; wire fb_en; wire [4:0] fb_fmt; @@ -1514,13 +1483,16 @@ wire [11:0] fb_height; wire [31:0] fb_base; wire [13:0] fb_stride; -`ifdef USE_FB - wire fb_pal_clk; - wire [7:0] fb_pal_a; - wire [23:0] fb_pal_d; - wire [23:0] fb_pal_q; - wire fb_pal_wr; - wire fb_force_blank; + +`ifdef MISTER_FB + `ifdef MISTER_FB_PALETTE + wire fb_pal_clk; + wire [7:0] fb_pal_a; + wire [23:0] fb_pal_d; + wire [23:0] fb_pal_q; + wire fb_pal_wr; + `endif + wire fb_force_blank; `else assign fb_en = 0; assign fb_fmt = 0; @@ -1557,7 +1529,7 @@ emu emu .VIDEO_ARX(ARX), .VIDEO_ARY(ARY), -`ifdef USE_FB +`ifdef MISTER_FB .FB_EN(fb_en), .FB_FORMAT(fb_fmt), .FB_WIDTH(fb_width), @@ -1568,11 +1540,14 @@ emu emu .FB_LL(lowlat), .FB_FORCE_BLANK(fb_force_blank), +`ifdef MISTER_FB_PALETTE .FB_PAL_CLK (fb_pal_clk), .FB_PAL_ADDR(fb_pal_a), .FB_PAL_DOUT(fb_pal_d), .FB_PAL_DIN (fb_pal_q), .FB_PAL_WR (fb_pal_wr), +`endif + `endif .LED_USER(led_user), @@ -1583,13 +1558,10 @@ emu emu .AUDIO_L(audio_l), .AUDIO_R(audio_r), .AUDIO_S(audio_s), - -`ifndef ARCADE_SYS .AUDIO_MIX(audio_mix), - .ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}), -`endif -`ifdef USE_DDRAM + .ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}), + .DDRAM_CLK(ram_clk), .DDRAM_ADDR(ram_address), .DDRAM_BURSTCNT(ram_burstcount), @@ -1600,9 +1572,7 @@ emu emu .DDRAM_DIN(ram_writedata), .DDRAM_BE(ram_byteenable), .DDRAM_WE(ram_write), -`endif -`ifdef USE_SDRAM .SDRAM_DQ(SDRAM_DQ), .SDRAM_A(SDRAM_A), .SDRAM_DQML(SDRAM_DQML), @@ -1614,9 +1584,8 @@ emu emu .SDRAM_nCAS(SDRAM_nCAS), .SDRAM_CLK(SDRAM_CLK), .SDRAM_CKE(SDRAM_CKE), -`endif -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM .SDRAM2_DQ(SDRAM2_DQ), .SDRAM2_A(SDRAM2_A), .SDRAM2_BA(SDRAM2_BA), @@ -1628,14 +1597,14 @@ emu emu .SDRAM2_EN(SW[3]), `endif -`ifndef ARCADE_SYS .BUTTONS(btn), .OSD_STATUS(osd_status), + .SD_SCK(SD_CLK), .SD_MOSI(SD_MOSI), .SD_MISO(SD_MISO), .SD_CS(SD_CS), -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM .SD_CD(mcp_sdcd), `else .SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))), @@ -1647,7 +1616,6 @@ emu emu .UART_TXD(uart_rxd), .UART_DTR(uart_dsr), .UART_DSR(uart_dtr), -`endif .USER_OUT(user_out), .USER_IN(user_in)