From c12c376d4bc52af4415d00a325bc536f8e7696f9 Mon Sep 17 00:00:00 2001 From: sorgelig Date: Sun, 19 Aug 2018 07:16:56 +0800 Subject: [PATCH] GS: refactoring, convert output to signed. --- gs.v | 60 ++++++++++++++++++++++----------------------------- zxspectrum.sv | 31 +++++++++++++------------- 2 files changed, 41 insertions(+), 50 deletions(-) diff --git a/gs.v b/gs.v index a95e80d..5c557c1 100644 --- a/gs.v +++ b/gs.v @@ -4,6 +4,7 @@ General Sound ----------------------------------------------------------------------------- 18.08.2018 Reworked first verilog version + 19.08.2018 Produce proper signed output CPU: Z80 @ 28MHz ROM: 32K @@ -70,20 +71,19 @@ module gs #(parameter PAGES=4, ROMFILE="gs105a.mif") input CLK, input CE, - input [15:0] A, + input A, input [7:0] DI, output [7:0] DO, + input CS_n, input WR_n, input RD_n, - input IORQ_n, - input MUTE, - output reg [14:0] OUTL, - output reg [14:0] OUTR + output [14:0] OUTL, + output [14:0] OUTR ); // port #xxBB : #xxB3 -assign DO = A[3] ? {bit7, 6'b111111, bit0} : port_03; +assign DO = A ? {bit7, 6'b111111, bit0} : port_03; // CPU reg int_n; @@ -144,12 +144,10 @@ always @(posedge CLK) begin 'hB: bit0 <= port_09[5]; endcase end - else if (~IORQ_n) begin - if (A[7:0] == 8'hB3) begin - if (~RD_n) bit7 <= 0; - if (~WR_n) bit7 <= 1; - end - if (A[7:0] == 8'hBB && ~WR_n) bit0 <= 1; + else if (~CS_n) begin + if (~A & ~RD_n) bit7 <= 0; + if (~A & ~WR_n) bit7 <= 1; + if ( A & ~WR_n) bit0 <= 1; end end @@ -161,24 +159,16 @@ always @(posedge CLK) begin port_BB <= 0; port_B3 <= 0; end - else if (~IORQ_n && ~WR_n) begin - if(A[7:0] == 8'hBB) port_BB <= DI; - if(A[7:0] == 8'hB3) port_B3 <= DI; + else if (~CS_n && ~WR_n) begin + if(A) port_BB <= DI; + else port_B3 <= DI; end end - -reg [7:0] ch_a; -reg [7:0] ch_b; -reg [7:0] ch_c; -reg [7:0] ch_d; - reg [3:0] port_00; reg [7:0] port_03; -reg [5:0] port_06; -reg [5:0] port_07; -reg [5:0] port_08; -reg [5:0] port_09; +reg signed [6:0] port_06, port_07, port_08, port_09; +reg signed [7:0] ch_a, ch_b, ch_c, ch_d; always @(posedge CLK) begin if (RESET) begin @@ -199,15 +189,13 @@ always @(posedge CLK) begin if (~cpu_mreq_n && ~cpu_rd_n && cpu_a_bus[15:13] == 3) begin case(cpu_a_bus[9:8]) - 0: ch_a <= mem_do; - 1: ch_b <= mem_do; - 2: ch_c <= mem_do; - 3: ch_d <= mem_do; + 0: ch_a <= {~mem_do[7],mem_do[6:0]}; + 1: ch_b <= {~mem_do[7],mem_do[6:0]}; + 2: ch_c <= {~mem_do[7],mem_do[6:0]}; + 3: ch_d <= {~mem_do[7],mem_do[6:0]}; endcase end end - - if(MUTE) {ch_a,ch_b,ch_c,ch_d} <= 0; end wire [7:0] cpu_di_bus = @@ -227,7 +215,7 @@ dpram #(.ADDRWIDTH(19), .NUMWORDS((PAGES+1)*32768), .MEM_INIT_FILE(ROMFILE)) mem .q_a(mem_do) ); -reg [13:0] out_a,out_b,out_c,out_d; +reg signed [14:0] out_a,out_b,out_c,out_d; always @(posedge CLK) begin if(CE) begin out_a <= ch_a * port_06; @@ -237,11 +225,15 @@ always @(posedge CLK) begin end end +reg signed [14:0] outl, outr; always @(posedge CLK) begin if(CE) begin - OUTL <= {1'b0, out_a} + {1'b0, out_b}; - OUTR <= {1'b0, out_c} + {1'b0, out_d}; + outl <= out_a + out_b; + outr <= out_c + out_d; end end +assign OUTL = outl; +assign OUTR = outr; + endmodule diff --git a/zxspectrum.sv b/zxspectrum.sv index c91e936..7f7cc17 100644 --- a/zxspectrum.sv +++ b/zxspectrum.sv @@ -124,8 +124,6 @@ localparam CONF_STR1 = { "O89,Video timings,ULA-48,ULA-128,Pentagon;", "O45,Aspect ratio,Original,Wide,Zoom;", "OFG,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "-;", - "O1,General Sound,Enabled,Disabled;", "O23,Stereo mix,none,25%,50%,100%;", "-;", "OHJ,Joystick,Kempston,Sinclair I,Sinclair II,Sinclair I+II,Cursor;", @@ -566,7 +564,7 @@ end //////////////////// AUDIO /////////////////// wire [7:0] sound_data; -wire [11:0] psg_ch_l, psg_ch_r; +wire [11:0] ts_l, ts_r; wire psg_enable = addr[0] & addr[15] & ~addr[1]; wire psg_we = psg_enable & ~nIORQ & ~nWR & nM1; reg psg_reset; @@ -585,8 +583,8 @@ turbosound turbosound .BC(addr[14]), .DI(cpu_dout), .DO(sound_data), - .CHANNEL_L(psg_ch_l), - .CHANNEL_R(psg_ch_r) + .CHANNEL_L(ts_l), + .CHANNEL_R(ts_r) ); reg ce_saa; //8MHz @@ -599,8 +597,8 @@ always @(negedge clk_sys) begin ce_saa <= !counter; end -wire [7:0] saa_ch_l; -wire [7:0] saa_ch_r; +wire [7:0] saa_l; +wire [7:0] saa_r; saa1099 saa1099 ( @@ -611,8 +609,8 @@ saa1099 saa1099 .a0(addr[8]), .wr_n(nWR), .din(cpu_dout), - .out_l(saa_ch_l), - .out_r(saa_ch_r) + .out_l(saa_l), + .out_r(saa_r) ); wire [7:0] gs_dout; @@ -621,24 +619,25 @@ wire [14:0] gs_l, gs_r; // GS 352KB gs #(11) gs ( - .RESET(aud_reset | status[1]), + .RESET(aud_reset), .CLK(clk_sys), .CE(ce_28m), - .A(addr), + + .A(addr[3]), .DI(cpu_dout), .DO(gs_dout), + .CS_n(nIORQ | ~gs_sel), .WR_n(nWR), .RD_n(nRD), - .IORQ_n(nIORQ), - .MUTE(status[1]), + .OUTL(gs_l), .OUTR(gs_r) ); -wire gs_sel = (addr[7:4] == 'b1011 && addr[2:0] == 'b011) && ~status[1]; +wire gs_sel = (addr[7:0] ==? 'b1011?011); -wire [11:0] audio_l = psg_ch_l + {2'b00, saa_ch_l, 2'b00} + {2'b00, gs_l[14:5]} + {3'b000, ear_out, mic_out, tape_in, 6'b000000}; -wire [11:0] audio_r = psg_ch_r + {2'b00, saa_ch_r, 2'b00} + {2'b00, gs_r[14:5]} + {3'b000, ear_out, mic_out, tape_in, 6'b000000}; +wire [11:0] audio_l = ts_l + {{3{gs_l[14]}}, gs_l[13:5]} + {2'b00, saa_l, 2'b00} + {3'b000, ear_out, mic_out, tape_in, 6'b000000}; +wire [11:0] audio_r = ts_r + {{3{gs_r[14]}}, gs_r[13:5]} + {2'b00, saa_r, 2'b00} + {3'b000, ear_out, mic_out, tape_in, 6'b000000}; compressor compressor (