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https://github.com/MiSTer-devel/Vectrex_MiSTer.git
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560 lines
14 KiB
Systemverilog
560 lines
14 KiB
Systemverilog
//============================================================================
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// Vectrex
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//
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// Port to MiSTer
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// Copyright (C) 2017-2019 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE, // analog out is off
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign LED_USER = ioctl_download;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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assign VGA_SCALER= 0;
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assign VGA_DISABLE = 0;
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assign HDMI_FREEZE = 0;
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wire [1:0] ar = status[17:16];
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video_freak video_freak
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(
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.*,
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.VGA_DE_IN(VGA_DE),
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.VGA_DE(),
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.ARX((!ar) ? (status[20] ? 12'd11 : 12'd9 ) : (ar - 1'd1)),
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.ARY((!ar) ? (status[20] ? 12'd9 : 12'd11) : 12'd0),
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.CROP_SIZE(0),
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.CROP_OFF(0),
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.SCALE(status[19:18])
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);
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`include "build_id.v"
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localparam CONF_STR = {
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"VECTREX;;",
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"-;",
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"f1,OVR;",
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"F1,VECBINROM;",
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"F2,OVR,Load Overlay;",
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"OB,Skip logo,No,Yes;",
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"-;",
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"OK,Orientation,Horz,Vert;",
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"OGH,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"OIJ,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
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"O9,Frame,No,Yes;",
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//"O4,Resolution,High,Low;", // AJS - remove this because it ruins the
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//overlay
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"O23,Phosphor persistance,1,2,3,4;",
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"O56,Pseudocolor,Off,1,2,3;",
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"O8,Overburn,No,Yes;",
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"-;",
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// overlay alpha is useful for debugging
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"OD,Overlay Alpha,On,Off;",
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// blend the vector with the overlay
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"OE,Color Vector,Overlay On,White always;",
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// tint the vector towards white
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"OF,Tint Vector White,On,Off;",
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"-;",
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"OC,Port 2,Joystick,Speech;",
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"OA,CPU Model,1,2;",
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"-;",
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"R7,Reset;",
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"J1,Button 1,Button 2,Button 3,Button 4;",
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"V,v",`BUILD_DATE
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};
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//////////////////// CLOCKS ///////////////////
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wire clk_sys;
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wire clk_mem;
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wire clk_48;
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wire pll_locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys),
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.outclk_1(clk_mem),
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.outclk_2(clk_48),
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.locked(pll_locked)
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);
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///////////////////////////////////////////////////
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wire [31:0] status;
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wire [1:0] buttons;
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wire [15:0] sdram_sz;
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wire [15:0] joystick_0, joystick_1;
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wire [15:0] joya_0, joya_1;
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wire ioctl_download;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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wire [15:0] ioctl_index;
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.buttons(buttons),
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.status(status),
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.ioctl_download(ioctl_download),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_index(ioctl_index),
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.ioctl_wait(0),
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.sdram_sz(sdram_sz),
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.joystick_l_analog_0(joya_0),
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.joystick_l_analog_1(joya_1),
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.joystick_0(joystick_0),
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.joystick_1(joystick_1)
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);
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wire [9:0] audio;
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assign AUDIO_L = {audio, 6'd0};
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assign AUDIO_R = {audio, 6'd0};
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assign AUDIO_S = 1;
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assign AUDIO_MIX = 0;
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wire reset = (RESET | status[0] | status[7] | buttons[1] | ioctl_download | second_reset);
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reg second_reset = 0;
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always @(posedge clk_sys) begin
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integer timeout = 0;
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if(ioctl_download && status[11]) timeout <= 5000000;
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else begin
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if(!timeout) second_reset <= 0;
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else begin
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timeout <= timeout - 1;
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if(timeout < 1000) second_reset <= 1;
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end
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end
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end
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wire hblank, vblank;
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assign CLK_VIDEO = clk_sys;
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assign CE_PIXEL = 1;
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assign VGA_SL = 0;
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assign VGA_F1 = 0;
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assign VGA_HS = hblank;
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assign VGA_VS = vblank;
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assign VGA_DE = ~(hblank | vblank);
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reg ce_pix;
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always @(posedge clk_48) ce_pix <= !ce_pix;
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wire [4:0] pers[4] = '{8,4,2,1};
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wire [9:0] width[2] = '{540, 332};
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wire [9:0] height[2] = '{720, 410};
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wire [19:0] wm[2] = '{539*720, 331*410};
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wire frame_line;
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wire [7:0] r,g,b;
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assign VGA_R = status[9] & frame_line ? 8'h40 : new_r;
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assign VGA_G = status[9] & frame_line ? 8'h00 : new_g;
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assign VGA_B = status[9] & frame_line ? 8'h00 : new_b;
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//assign VGA_R = bg_r;
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wire fg = |{r,g,b};
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wire bg = |{bg_r,bg_g,bg_b};
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//
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// if fg is non zero, then the beam is at this pixel
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// make the color either:
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// -- the background color (no alpha) if pixel is dark
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// -- the background color tinted towards white if the beam is bright
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// if fg is zero, we use the background after an alpha * black has been applied
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wire [7:0] new_r = fg ? bbrw : ~status[13] ? bga_r : {bg_r,bg_r};
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wire [7:0] new_g = fg ? bbgw : ~status[13] ? bga_g : {bg_g,bg_g};
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wire [7:0] new_b = fg ? bbbw : ~status[13] ? bga_b : {bg_b,bg_b};
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wire [7:0] bbrw = ~status[15] ? blend_r_w : blend_r;
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wire [7:0] bbgw = ~status[15] ? blend_g_w : blend_g;
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wire [7:0] bbbw = ~status[15] ? blend_b_w : blend_b;
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// tint it towards white when it is brighter, otherwise use the background
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// color (no alpha)
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// r + (255-r)*tint
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// to simplify we want tint ~ 3/4 = ( 1/4 + 1/2 )
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wire [7:0] blend_r_w = r > 108 ? (blend_r + ((8'd255-blend_r)>>1) + ((8'd255-blend_r)>>2) ) : blend_r;
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wire [7:0] blend_g_w = r > 108 ? (blend_g + ((8'd255-blend_g)>>1) + ((8'd255-blend_g)>>2) ) : blend_g;
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wire [7:0] blend_b_w = r > 108 ? (blend_b + ((8'd255-blend_b)>>1) + ((8'd255-blend_b)>>2) ) : blend_b;
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wire [7:0] blend_r = ~status[14] ? bg ? { bg_r << 2 | bg_r[0] , bg_r << 2 | bg_r[0]} : r : r;
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wire [7:0] blend_g = ~status[14] ? bg ? { bg_g << 2 | bg_g[0] , bg_g << 2 | bg_g[0]} : g : g;
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wire [7:0] blend_b = ~status[14] ? bg ? { bg_b << 2 | bg_b[0] , bg_b << 2 | bg_b[0]} : b : b;
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wire rom_download = ioctl_download && (ioctl_index[4:0] <= 1) && (ioctl_index[9:8] == 0);
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wire bg_download = ioctl_download && ((ioctl_index[4:0] == 2) || (ioctl_index[9:8] == 1));
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reg [14:0] addr_mask;
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always @(posedge clk_sys) begin
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reg old_download;
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old_download <= rom_download;
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if(~old_download & rom_download) addr_mask <= 0;
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if(rom_download && ioctl_wr && (ioctl_addr[14:0] & ~addr_mask)) addr_mask <= ((addr_mask<<1)|15'd1);
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end
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vectrex vectrex
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(
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.reset(reset),
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.clock(clk_sys),
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.cpu(status[10]),
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.cart_data(ioctl_dout),
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.cart_addr(ioctl_addr),
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.cart_mask(addr_mask),
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.cart_wr(ioctl_wr & ioctl_download & rom_download ),
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.video_r(r),
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.video_g(g),
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.video_b(b),
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.video_hblank(hblank),
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.video_vblank(vblank),
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.v_orient(status[20]),
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.v_width(width[0]), //status[4]]),
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.v_height(height[0]), //status[4]]),
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.color(status[6:5]),
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.pers(pers[status[3:2]]),
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.overburn(status[8]),
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.frame_line(frame_line),
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.speech_mode(status[12]),
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.audio_out(audio),
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.up_1(joystick_0[4]),
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.dn_1(joystick_0[5]),
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.lf_1(joystick_0[6]),
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.rt_1(joystick_0[7]),
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.pot_x_1(joya_0[7:0] ? joya_0[7:0] : {joystick_0[1], {7{joystick_0[0]}}}),
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.pot_y_1(joya_0[15:8] ? ~joya_0[15:8] : {joystick_0[2], {7{joystick_0[3]}}}),
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.up_2(joystick_1[4]),
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.dn_2(joystick_1[5]),
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.lf_2(joystick_1[6]),
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.rt_2(joystick_1[7]),
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.pot_x_2(joya_1[7:0] ? joya_1[7:0] : {joystick_1[1], {7{joystick_1[0]}}}),
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.pot_y_2(joya_1[15:8] ? ~joya_1[15:8] : {joystick_1[2], {7{joystick_1[3]}}})
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);
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//
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// Load 16bit color data from the ioctl as a file load
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//
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// the format is RBGA with each channel taking 4 bits
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//
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reg dl_wr;
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reg [15:0] dl_data;
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reg [23:0] dl_addr;
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always @(posedge clk_sys) begin
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reg [7:0] ioctl_dout_r;
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reg [19:0] y;
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reg [9:0] vcnt, x;
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dl_wr <= 0;
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if(ioctl_wr) begin
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dl_wr <= 1;
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dl_addr <= ioctl_addr[24:1];
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if(~ioctl_addr[0]) begin
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ioctl_dout_r <= ioctl_dout;
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if(!dl_addr) begin
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vcnt <= width[0]-1'd1;
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x <= 0;
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y <= wm[0] - height[0];
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dl_addr <= wm[0] + 24'h100000;
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end
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else begin
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y <= y - height[0];
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dl_addr <= y + x + 24'h100000;
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vcnt <= vcnt - 1'd1;
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if(!vcnt) begin
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vcnt <= width[0]-1'd1;
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x <= x + 1'd1;
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y <= wm[0] - height[0];
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dl_addr <= wm[0] + x + 24'h100001;
|
|
end
|
|
end
|
|
end
|
|
else begin
|
|
dl_data <= {ioctl_dout, ioctl_dout_r};
|
|
end
|
|
end
|
|
end
|
|
|
|
wire [31:0] sd_data;
|
|
wire ram_ready;
|
|
wire [24:0] sdram_addr = bg_download ? dl_addr : {status[20],pic_addr2[19:0]};
|
|
|
|
sdram sdram
|
|
(
|
|
.*,
|
|
|
|
.init(~pll_locked),
|
|
.clk(clk_mem),
|
|
.ch1_addr({sdram_addr[19:1],sdram_addr[20],sdram_addr[0]}),
|
|
.ch1_dout(sd_data),
|
|
.ch1_din(dl_data),
|
|
.ch1_req(bg_download ? dl_wr : pic_req),
|
|
.ch1_rnw(~bg_download)
|
|
);
|
|
|
|
//
|
|
// Alpha Blend is a table lookup to mix the color with black
|
|
//
|
|
// we can't hardcode it, because when the light comes through
|
|
// the overlay we need the original color
|
|
//
|
|
wire [7:0] bga_r,bga_g,bga_b;
|
|
alphablend alphablend(
|
|
.clk(clk_48),
|
|
.bg_a(bg_a),
|
|
.bg_r(bg_r),
|
|
.bg_g(bg_g),
|
|
.bg_b(bg_b),
|
|
.bga_r(bga_r),
|
|
.bga_g(bga_g),
|
|
.bga_b(bga_b)
|
|
);
|
|
|
|
wire VSync = VGA_VS;
|
|
|
|
wire[23:0] pic_addr2 = {pic_addr[24:2],1'b0};
|
|
|
|
reg [15:0] pic_data[2];
|
|
reg pic_req;
|
|
reg [24:1] pic_addr;
|
|
reg [3:0] bg_r,bg_g,bg_b,bg_a;
|
|
always @(posedge clk_48) begin
|
|
reg old_vs;
|
|
reg use_bg = 0;
|
|
reg [1:0] cnt;
|
|
|
|
if(rom_download) use_bg <= 0;
|
|
if(bg_download && sdram_sz[2:0]) use_bg <= 1;
|
|
|
|
pic_req <= 0;
|
|
|
|
if(use_bg & ~bg_download) begin
|
|
if(ce_pix) begin
|
|
|
|
cnt <= cnt >> 1;
|
|
if(cnt[0]) {pic_data[1],pic_data[0]} <= sd_data;
|
|
|
|
old_vs <= VSync;
|
|
if(~(hblank|vblank)) begin
|
|
{bg_a,bg_b,bg_g,bg_r} <= pic_data[~pic_addr[1]];
|
|
pic_addr <= pic_addr + 2'd1;
|
|
if(pic_addr[1]) begin
|
|
pic_req <= 1;
|
|
cnt <= 2;
|
|
end
|
|
end
|
|
|
|
if(~old_vs & VSync) begin
|
|
pic_addr <= 0;
|
|
pic_req <= 1;
|
|
cnt <= 2;
|
|
end
|
|
end
|
|
end
|
|
else begin
|
|
{bg_a,bg_b,bg_g,bg_r} <= 0;
|
|
end
|
|
end
|
|
|
|
endmodule
|